HDLRuby 3.0.0 → 3.1.0

data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb

@@ -16,34 +16,34 @@ system :my_seqencer do
     [8].inner :res0, :res1
 
     sequencer(clk.posedge,rst) do
-        hprint("#0\n")
+        # hprint("#0\n")
         res0 <= 0
         res1 <= 0
         res0 <= vals.ssum
         res1 <= res0.ssum(_h00)
-        hprint("#1 res0=",res0," res1=",res1,"\n")
+        # hprint("#1 res0=",res0," res1=",res1,"\n")
     end
 
     [8].inner :res2, :res3
 
     sequencer(clk.posedge,rst) do
-        hprint("$0\n")
+        # hprint("$0\n")
         res2 <= 0
         res3 <= 0
-        res2 <= (1..5).sum
+        res2 <= (1..5).ssum(_h00)
         res3 <= (res3..res2).ssum
-        hprint("$1 res2=",res2," res3=",res3,"\n")
+        # hprint("$1 res2=",res2," res3=",res3,"\n")
     end
 
     [8].inner :res4, :res5
 
     sequencer(clk.posedge,rst) do
-        hprint("!0\n")
+        # hprint("!0\n")
         res4 <= 0
         res5 <= 0
         res4 <= [_h01,_h02,_h03,_h04].ssum
-        res5 <= [1,2,3,4,5].ssum
-        hprint("!1 res4=",res4," res5=",res5,"\n")
+        res5 <= [1,2,3,4,5].ssum(_h00)
+        # hprint("!1 res4=",res4," res5=",res5,"\n")
     end
 
     bit[8][-8].inner mem: [ _h01, _h02, _h03, _h04, _h30, _h30, _h30, _h30 ]
@@ -59,10 +59,10 @@ system :my_seqencer do
     end
 
     sequencer(clk.posedge,rst) do
-        hprint("~0\n")
+        # hprint("~0\n")
         res6 <= 0
         res6 <= mem_enum.ssum
-        hprint("~1 res6=",res6,"\n")
+        # hprint("~1 res6=",res6,"\n")
     end
 
 

data/lib/HDLRuby/hdr_samples/with_sequencer_func.rb

@@ -0,0 +1,63 @@
+require 'std/sequencer_func.rb'
+
+include HDLRuby::High::Std
+
+
+# A factorial with default stack depth.
+sdef(:fact) do |n|
+    hprint("n=",n,"\n")
+    sif(n > 1) { sreturn(n*fact(n-1,20)) } #Recurse setting the stack depth to 20
+    selse      { sreturn(1) }
+end
+
+# A factiorial with very low stack depth for checking overflow.
+sdef(:fact_over,2,proc { stack_overflow_error <= 1 }) do |n|
+    hprint("n2=",n,"\n")
+    sif(n > 1) { sreturn(n*fact_over(n-1)) }
+    selse      { sreturn(1) }
+end
+
+# Checking the usage of sequencers functions.
+system :my_seqencer do
+
+    inner :clk,:rst
+
+    [16].inner :val
+    [16].inner :res
+
+    inner stack_overflow_error: 0
+
+    sequencer(clk.posedge,rst) do
+        5.stimes do |i|
+            val <= i
+            res <= fact(val)
+        end
+        hprint("Going to overflow...\n")
+        4.stimes do |i|
+            val <= i
+            res <= fact_over(val)
+        end
+        hprint("stack_overflow_error=",stack_overflow_error,"\n")
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        repeat(500) do
+            !10.ns
+            clk <= ~clk
+        end
+    end
+end

data/lib/HDLRuby/hdrcc.rb

@@ -821,7 +821,7 @@ elsif $options[:verilog] then
     $top_system.each_systemT_deep do |systemT|
         HDLRuby.show? "signal2subs step..."
         # Ensure there is not implicit assign to sub signals.
-        systemT.signal2subs!
+        systemT.signal2subs!(true)
         # HDLRuby.show "casts_without_expression! step..."
         # systemT.casts_without_expression!
         # HDLRuby.show Time.now

data/lib/HDLRuby/hruby_high.rb

@@ -2198,29 +2198,48 @@ module HDLRuby::High
     #
     # NOTE: a function is a short-cut for a method that creates a scope.
     def function(name, &ruby_block)
+        warn("Construct 'function' is deprecated, use 'hdef' instead.")
         # Ensure there is a block.
         ruby_block = proc {} unless block_given?
         if HDLRuby::High.in_system? then
             define_singleton_method(name.to_sym) do |*args,&other_block|
-                # sub do
                 sub(HDLRuby.uniq_name(name)) do
                     HDLRuby::High.top_user.instance_exec(*args,*other_block,
                                                          &ruby_block)
-                    # ruby_block.call(*args)
                 end
             end
         else
             define_method(name.to_sym) do |*args,&other_block|
-                # sub do
                 sub(HDLRuby.uniq_name(name)) do
                     HDLRuby::High.top_user.instance_exec(*args,*other_block,
                                                          &ruby_block)
-                    # ruby_block.call(*args,*other_block)
                 end
             end
         end
     end
 
+    # Declares a function named +name+ using +ruby_block+ as body.
+    #
+    # NOTE: a function is a short-cut for a method that creates a scope.
+    def hdef(name, &ruby_block)
+        # Ensure there is a block.
+        ruby_block = proc {} unless block_given?
+        if HDLRuby::High.in_system? then
+            define_singleton_method(name.to_sym) do |*args,&other_block|
+                sub(HDLRuby.uniq_name(name)) do
+                    HDLRuby::High.top_user.instance_exec(*args,*other_block,
+                                                         &ruby_block)
+                end
+            end
+        else
+            define_method(name.to_sym) do |*args,&other_block|
+                sub(HDLRuby.uniq_name(name)) do
+                    HDLRuby::High.top_user.instance_exec(*args,*other_block,
+                                                         &ruby_block)
+                end
+            end
+        end
+    end
 
 
 
@@ -3134,7 +3153,6 @@ module HDLRuby::High
 
         # Converts the unary expression to HDLRuby::Low.
         def to_low
-            # return HDLRuby::Low::Cast.new(self.type.to_low,self.child.to_low)
             castL =HDLRuby::Low::Cast.new(self.type.to_low,self.child.to_low)
             # # For debugging: set the source high object 
             # castL.properties[:low2high] = self.hdr_id

data/lib/HDLRuby/hruby_low_without_subsignals.rb

@@ -18,10 +18,24 @@ module HDLRuby::Low
         ## Extends the SystemT class with functionality for decomposing the
         #  hierachical signals in the statements.
 
+        # # Decompose the hierarchical signals in the statements.
+        # def signal2subs!
+        #     self.scope.signal2subs!
+        # end
+
         # Decompose the hierarchical signals in the statements.
-        def signal2subs!
+        # If +decompose_vec2d+ is true then also decompose 2 dimension vectors
+        # (e.g., for Verilog HDL that does not support handling such signals
+        #  as usual expressions).
+        def signal2subs!(decompose_vec2d = false)
+            @@decompose_vec2d = decompose_vec2d == true
             self.scope.signal2subs!
         end
+
+        ## Tell if 2d vector signals must be decomposed too.
+        def self.decompose_vec2d?
+            @@decompose_vec2d
+        end
     end
 
 
@@ -230,16 +244,41 @@ module HDLRuby::Low
         # from signal +sig+ and add to result to +subrefs+
         def flatten_to(sig,subrefs)
             # puts "flatten_to with sig name=#{sig.name}"
-            # Work on the sub signals if any.
-            sig.each_signal do |sub|
-                # Create a reference for the sub.
-                subref = RefName.new(sub.type,self.clone,sub.name)
-                # Recruse on it.
-                subref.flatten_to(sub,subrefs)
-                # Was it a leaf?
-                unless sub.each_signal.any? then
-                    # Yes, add its new ref to the list of subs.
-                    subrefs << subref
+            # Shall we decompose 2d vectors, and is the current signal
+            # for one of them?
+            if SystemT.decompose_vec2d? and sig.type.is_a?(TypeVector) and
+                    sig.type.base.is_a?(TypeVector) then
+                # Is the reference used other than for a memory access?
+                unless self.parent.is_a?(RefIndex) then
+                    # Yes, do the decomposition.
+                    # Selects the direction.
+                    rng = sig.type.range
+                    if rng.first > rng.last then
+                        itr = (rng.last..rng.first).each
+                    else
+                        itr = rng.reverse_each
+                    end
+                    # Iterate on each element.
+                    itr.each do |i|
+                        # Create a reference fo the sub.
+                        subref = RefIndex.new(sig.type.base,self.clone,
+                                                  Value.new(TypeUnsigned.new(:""),i))
+                        # Add it.
+                        subrefs << subref
+                    end
+                end
+            else
+                # Work on the sub signals if any.
+                sig.each_signal do |sub|
+                    # Create a reference for the sub.
+                    subref = RefName.new(sub.type,self.clone,sub.name)
+                    # Recurse on it.
+                    subref.flatten_to(sub,subrefs)
+                    # Was it a leaf?
+                    unless sub.each_signal.any? then
+                        # Yes, add its new ref to the list of subs.
+                        subrefs << subref
+                    end
                 end
             end
         end

data/lib/HDLRuby/hruby_types.rb

@@ -42,13 +42,13 @@ module HDLRuby
             elsif type.float? then
                 return type
             elsif self.signed? then
-                return self
+                if type.signed? then
+                    return self.width >= type.width ? self : type
+                else
+                    return self
+                end
             elsif type.signed? then
                 return type
-            elsif self.unsigned? then
-                return self
-            elsif type.unsigned? then
-                return type
             elsif self.width >= type.width then
                 return self
             else

data/lib/HDLRuby/hruby_values.rb

@@ -253,6 +253,7 @@ module HDLRuby
         # Cast to +type+.
         # NOTE: nodir tells if the direction is to be ignored.
         def cast(type,nodir = false)
+            # puts "cast with content=#{self.content} type.signed=#{type.signed?} type.width=#{type.width}"
             # Handle the direction.
             if !nodir && type.direction != self.type.direction then
                 if self.content.is_a?(Numeric) then
@@ -281,19 +282,18 @@ module HDLRuby
                     res_content.positive!
                 end
             end
-            if type.signed && res_content.is_a?(Numeric) && res_content >= (1 << (type.width-1)) then
+            if type.signed? && res_content.is_a?(Numeric) && res_content >= (1 << (type.width-1)) then
                 res_content = (-1 << type.width) + res_content
             end
-            # # truncs to the right size if necessary.
-            # if res_content.is_a?(BitString) then
-            #     res_content.trunc!(type.width)
-            # else 
-            #     res_content = self.trunc(res_content,type.width)
-            # end
             # Generate the resulting value.
+            # puts "res_content=#{res_content}"
             return self.class.new(type,res_content)
         end
 
+        def as(typ)
+            return self.cast(typ)
+        end
+
         # Concat the content of +vals+.
         def self.concat(*vals)
             # Compute the resulting type.

data/lib/HDLRuby/hruby_verilog.rb

@@ -89,10 +89,10 @@ module HDLRuby::Low
             # Convert the ranges to arrays.
             rngI,rngS = self.r2a(rngI), self.r2a(rngS)
             # Generate the name.
-            return "trunc_#{rngI[0]}_#{rngI[1]}_#{rngS[0]}_#{rngS[1]}"
+            return "truncer_#{rngI[0]}_#{rngI[1]}_#{rngS[0]}_#{rngS[1]}"
         end
 
-        # Generate the truncating functionds.
+        # Generate the truncating functions.
         def dump
             # Ensure there is only one truncating function per range.
             @truncers.sort!.uniq!
@@ -117,6 +117,53 @@ module HDLRuby::Low
     TruncersI = Truncers.new
 
 
+    # Class for generating the truncating functions in verilog.
+    # Such function are necessary as expression cannot be truncated directly.
+    class Indexers
+        def initialize
+            @indexers = []
+        end
+
+        # Add an indexer to of expression of verilog type +typI+ returning 
+        # verilog type +typR+.
+        def add(typI,typR)
+            # Add them
+            @indexers << [typI,typR]
+        end
+        alias_method :<<, :add
+
+
+        # Generate an indexer function name for expression of verilog type
+        # +typI+ returning verilog type +typR+.
+        def indexer_name(typI,typR)
+            # Generate the name.
+            return "indexer_#{name_to_verilog(typI)}_#{name_to_verilog(typR)}"
+        end
+
+        # Generate the indexing functions.
+        def dump
+            # Ensure there is only one indexing function per range.
+            @indexers.sort!.uniq!
+            # Generate the resulting code.
+            codeT = ""
+            @indexers.each do |(typI,typR)|
+                codeT << "     function #{typR} "
+                codeT << self.indexer_name(typI,typR) 
+                codeT << "(input #{typI} val, input integer idx);\n"
+                codeT << "         " << self.indexer_name(typI,typR) << " = "
+                codeT << "val[idx];\n"
+                codeT << "      endfunction\n\n"
+            end
+            # Clears the indexers.
+            @indexers = []
+            return codeT
+        end
+    end
+
+    # Declaration of the truncating function generator.
+    IndexersI = Indexers.new
+
+
     class Binary
         ## Enhances Binary with verilog generation.
 
@@ -1479,7 +1526,16 @@ module HDLRuby::Low
 
         # Converts the system to Verilog code.
         def to_verilog
-            return "#{self.ref.to_verilog}[#{self.index.to_verilog}]"
+            # return "#{self.ref.to_verilog}[#{self.index.to_verilog}]"
+            if self.ref.is_a?(RefName) then
+                return "#{self.ref.to_verilog}[#{self.index.to_verilog}]"
+            else
+                # No a pure signal, need to use a function for accessing.
+                at = self.ref.type.to_verilog
+                rt = self.type.to_verilog
+                IndexersI.add(at,rt)
+                return "#{IndexersI.indexer_name(at,rt)}(#{self.ref.to_verilog},#{self.index.to_verilog})"
+            end
         end
     end
 
@@ -1505,7 +1561,15 @@ module HDLRuby::Low
 
         # Converts the system to Verilog code.
         def to_verilog(unknown = false)
-            return "#{self.ref.to_verilog}[#{self.range.first.to_getrange}:#{self.range.last.to_getrange}]"
+            if self.ref.is_a?(RefName) then
+                return "#{self.ref.to_verilog}[#{self.range.first.to_getrange}:#{self.range.last.to_getrange}]"
+            else
+                # No a pure signal, need to use a function for accessing.
+                sr = self.range.first.to_i..self.range.last.to_i
+                cr = (self.type.width-1)..0
+                TruncersI.add(cr,sr)
+                return "#{TruncersI.truncer_name(cr,sr)}(#{self.ref.to_verilog})"
+            end
         end
     end
 
@@ -1576,20 +1640,28 @@ module HDLRuby::Low
             # end
             # return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
             if self.content.is_a?(Numeric) then
-                if self.content < 0 then
-                    # str = (2**self.type.width + self.content).to_s(2)
-                    str = self.content.to_s(2)
-                    str = "0" * (self.type.width-str.length+1) + str[1..-1]
-                    return "-#{self.type.width}'b#{str}"
+                if self.type.signed? then
+                    if self.content < 0 then
+                        # str = (2**self.type.width + self.content).to_s(2)
+                        str = self.content.to_s(2)
+                        str = "0" * (self.type.width-str.length+1) + str[1..-1]
+                        return "-#{self.type.width}'sb#{str}"
+                    else
+                        str = self.content.to_s(2)
+                        str = "0" * (self.type.width-str.length) + str
+                        return "#{self.type.width}'sb#{str}"
+                    end
                 else
-                    str = self.content.to_s(2)
-                    str = "0" * (self.type.width-str.length) + str
-                    return "#{self.type.width}'b#{str}"
+                    return "#{self.type.width}'b#{self.content.to_s(2)}"
                 end
                 # return "#{self.type.width}'b#{str}"
             else
                 str = self.content.to_verilog
-                return "#{str.length}'b#{str}"
+                if self.content.negative? then
+                    return "#{str.length}'sb#{str}"
+                else
+                    return "#{str.length}'b#{str}"
+                end
             end
         end
         # How to use when simply obtaining the width
@@ -1770,10 +1842,20 @@ module HDLRuby::Low
             cw = self.child.type.width
             sw = self.type.width
             if self.type.signed? then
-                if (sw>cw) then
-                    # Need to sign extend.
-                    return "$signed({{#{sw-cw}{#{self.child.to_verilog}[#{cw-1}]}}," +
-                        "#{self.child.to_verilog}})"
+                # Need to sign extend.
+                if cw == 1 then
+                    return "$signed({#{sw}{#{self.child.to_verilog}}})"
+                elsif (sw>cw) then
+                    # return "$signed({{#{sw-cw}{#{self.child.to_verilog}[#{cw-1}]}}," + "#{self.child.to_verilog}})"
+                    if self.child.is_a?(RefName) then
+                        return "$signed({{#{sw-cw}{#{self.child.to_verilog}[#{cw-1}]}}," + "#{self.child.to_verilog}})"
+                    else
+                        # No a pure signal, need to use a function for accessing.
+                        at = self.child.type.to_verilog
+                        rt = bit.to_verilog
+                        IndexersI.add(at,rt)
+                        return "$signed({{#{sw-cw}{#{IndexersI.indexer_name(at,rt)}(#{self.child.to_verilog},#{cw-1})}}," + "#{self.child.to_verilog}})"
+                    end
                 elsif (sw<cw) then
                     # Need to truncate
                     # return "$signed(#{self.child.to_verilog}[#{sw-1}:0])"
@@ -2288,6 +2370,8 @@ module HDLRuby::Low
 
             # Adds the truncing functions.
             code << TruncersI.dump
+            # Adds the indexing functions.
+            code << IndexersI.dump
             # Adds the content code.
             code << codeC
             return code

data/lib/HDLRuby/hruby_verilog_name.rb

@@ -1,42 +1,49 @@
-# Program with inverse conversion
-# last update 2019 01 29
-
-module HDLRuby::Verilog
-
-  # This is sample.
-  # n = "abc_ABC_いろは"
-  # puts n            
-  # name = n.split("")
-
-  @@hdr2verilog = {}
-
-  # Since it is possible to use $ and numbers other than the beginning of the character string, it is divided.
-  def name_to_verilog(name)
-      # name = name.to_s
-      # # Convert special characters.
-      # name = name.each_char.map do |c|
-      #     if c=~ /[a-z0-9]/ then
-      #         c
-      #     elsif c == "_" then
-      #         "__"
-      #     else
-      #         "_" + c.ord.to_s
-      #     end
-      # end.join
-      # # First character: only letter is possible.
-      # unless name[0] =~ /[a-z_]/ then
-      #     name = "_" + name
-      # end
-      # return name
-      name = name.to_s
-      vname = @@hdr2verilog[name]
-      unless vname then
-          vname = "_v#{@@hdr2verilog.size}_#{name.split(/[^a-zA-Z_0-9]/)[-1]}"
-            @@hdr2verilog[name] = vname
-      end
-      return vname
-  end
-
-  #puts ref
-
-end
+# Program with inverse conversion
+# last update 2019 01 29
+
+module HDLRuby::Verilog
+
+  # This is sample.
+  # n = "abc_ABC_いろは"
+  # puts n            
+  # name = n.split("")
+
+  @@hdr2verilog = {}
+
+  # Since it is possible to use $ and numbers other than the beginning of the character string, it is divided.
+  def name_to_verilog(name)
+      # name = name.to_s
+      # # Convert special characters.
+      # name = name.each_char.map do |c|
+      #     if c=~ /[a-z0-9]/ then
+      #         c
+      #     elsif c == "_" then
+      #         "__"
+      #     else
+      #         "_" + c.ord.to_s
+      #     end
+      # end.join
+      # # First character: only letter is possible.
+      # unless name[0] =~ /[a-z_]/ then
+      #     name = "_" + name
+      # end
+      # return name
+      name = name.to_s
+      vname = @@hdr2verilog[name]
+      unless vname then
+          # Shall we change the string?
+          if name.match?(/^[_a-zA-Z][_a-zA-Z0-9]*$/) then
+              # No, just clone
+              vname = name.clone
+          else
+              # Yes, ensure it is a verilog-compatible name.
+              vname = "_v#{@@hdr2verilog.size}_#{name.split(/[^a-zA-Z_0-9]/)[-1]}"
+          end
+          @@hdr2verilog[name] = vname
+      end
+      return vname
+  end
+
+  #puts ref
+
+end

data/lib/HDLRuby/std/fsm.rb

@@ -219,7 +219,11 @@ module HDLRuby::High::Std
                             # The default code.
                             default_codes.each(&:call)
                             # Depending on the state.
-                            hcase(this.cur_state_sig)
+                            if (type == :sync) then
+                                hcase(this.next_state_sig)
+                            else
+                                hcase(this.cur_state_sig)
+                            end
                             states.each do |st|
                                 # Register the working state (for the gotos)
                                 this.work_state = st
@@ -345,6 +349,11 @@ module HDLRuby::High::Std
 
 
         ## The interface for building the fsm
+        
+        # Gets the current number of states.
+        def size
+            @states.size
+        end
 
         # Sets the event synchronizing the fsm.
         def for_event(event = nil,&ruby_block)