HDLRuby 2.7.5 → 2.9.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 4995e808d0aa2901a483011a4848bb9416d68850c95c74b9c2f2bf1fb3f648dc
-  data.tar.gz: 729643cd60228ab9ba4f3ab719e434b48963805ed6f4ac01dbcff2fdd6eb54b9
+  metadata.gz: 96e1ddbe94d4b2b40301b61373ed4cea3b2b5bcb461338844af6ebd23380ad4f
+  data.tar.gz: e8e3c5bdc2c7a91c25f41964a15a80a39701c54a49b09540c637b14130bc08e6
 SHA512:
-  metadata.gz: 82316dd87a532dbfa67d86fcdb13ade3f8329912bb6aa56ae0b5a4efe0a6110922912f52ae3558c4683147bb224ae2ed0b67e1d60e265d5d30624b3a2bee77be
-  data.tar.gz: 4df2cfb5c257838246fa2f953b3eeaa751902900ae4ea5319a69ca81f9e7eae49b75163fc621a81b2af1b399360c030ccf8717916c2abb7a5d2ffaad27d2b5df
+  metadata.gz: 2c63c50fb2aa3683cb43246b0036ccbe89155ad08d122f738a6ba68bd0886a089608ddc6592d0a728dc7476d00e480ed1f8e0ba4ac97dd97dcbb994099598f90
+  data.tar.gz: 04ee073e082ab0cc9993a7f7888d85959570e969bf83b3247874df6888559be8c4a8d561d5276a9c9d8042f86302b95d4454bb7803aec0e41210c1c747cc4fba

data/README.md

@@ -439,7 +439,7 @@ The description above is straight forward, but it would be necessary to rewrite
 
 ```ruby
 system :sumprod do |typ,coefs|
-   typ[coefs.size].input ins
+   typ[coefs.size].input :ins
    typ.output :o
    
    o <= coefs.each_with_index.reduce(_0) do |sum,(coef,i)|

data/lib/HDLRuby/hdr_samples/adder_gen.rb

@@ -5,3 +5,25 @@ system :adder do |w|
 
     s <= x.as(bit[w+1]) + y
 end
+
+
+# Testing the generic adder.
+system :adder_bench do
+    width = 4
+    [width].inner :x,:y
+    [width+1].inner :z
+
+    adder(width).(:my_adder).(x,y,z)
+
+    timed do
+        x <= 0
+        y <= 0
+        !10.ns
+        x <= 1
+        !10.ns
+        y <= 1
+        !10.ns
+        x <= 15
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/adder_gen_gen.rb

@@ -0,0 +1,40 @@
+# A simple generic adder
+system :adder do |w|
+    [(w-1)..0].input :i,:j
+    [w..0].output :k
+
+    k <= i.as(bit[w+1]) + j
+end
+
+# A module embedding two generic adders.
+system :two_adders do |w|
+    [w*2].input :x, :y
+    [(w+1)*2].output :z
+
+    adder(w).(:adderI0).(x[(w-1)..0],y[(w-1)..0],z[w..0])
+    adder(w).(:adderI1).(x[(w*2-1)..w],y[(w*2-1)..w],z[(w*2+1)..(w+1)])
+end
+
+
+# Testing the generic adder.
+system :adder_bench do
+    width = 4
+    [width*2].inner :a,:b
+    [(width+1)*2].inner :c
+
+    two_adders(width).(:my_adders).(a,b,c)
+
+    timed do
+        a <= 0
+        b <= 0
+        !10.ns
+        a <= 1
+        !10.ns
+        b <= 1
+        !10.ns
+        a <= 255
+        !10.ns
+        b <= 128
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/dff_unit.rb

@@ -6,7 +6,7 @@
 3.times do |i|
 
     # A simple D-FF
-    system:"dff#{i}" do
+    system :"dff#{i}" do
         input :clk, :rst, :d
         output :q, :qb
 

data/lib/HDLRuby/hdr_samples/parseq_bench.rb

@@ -0,0 +1,61 @@
+# Check of various par and seq.
+
+# A benchmark for the dff.
+system :parseq_bench do
+    [4].inner :x0, :x1, :x2, :x3
+    [4].inner :y0, :y1, :y2, :y3
+    [4].inner :z00, :z01
+    [4].inner :z10, :z11
+    [4].inner :z20, :z21
+    [4].inner :z30, :z31
+    [4].inner :u0, :u1, :u2, :u3
+    bit[4][-16].constant mem: 16.times.to_a
+
+    par(x0) do
+        z00 <= x0 + y0
+        z01 <= z00 + 1
+        u0 <= mem[z00]
+    end
+
+    seq(y1) do
+        z10 <= x1 + y1
+        z11 <= z10 + 1
+        u1 <= mem[z10]
+    end
+
+    seq(x2,y2) do
+        z20 <= x2 + y2
+        z21 <= z20 + 1
+        u2 <= mem[z20]
+    end
+
+    par do
+        bit[4].constant inc: 1
+        z30 <= x3 + y3
+        z31 <= z30 + inc
+        u3 <= mem[z30]
+    end
+
+
+    timed do
+        x0 <= 1
+        x1 <= 1
+        x2 <= 1
+        x3 <= 1
+        !10.ns
+        y0 <= 2
+        y1 <= 2
+        y2 <= 2
+        y3 <= 2
+        !10.ns
+        x0 <= 3
+        x1 <= 3
+        x2 <= 3
+        x3 <= 3
+        y0 <= 4
+        y1 <= 4
+        y2 <= 4
+        y3 <= 4
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/range_bench.rb

@@ -3,13 +3,16 @@
 # A benchmark for the index access..
 system :if_bench do
     [8].inner :x
-    [2].inner :r0,:r1,:r2,:r3
+    [2].inner :r0,:r1,:r2,:r3, :r4
+    inner :r5
 
     par do
         r0 <= x[1..0]
         r1 <= x[3..2]
         r2 <= x[5..4]
         r3 <= x[7..6]
+        r4 <= x[-1..-2]
+        r5 <= x[-1]
     end
 
     timed do

data/lib/HDLRuby/hdr_samples/rom_nest.rb

@@ -0,0 +1,27 @@
+# Rom access generator, def case.
+def rom_gen(addr,&func)
+    bit[8][-8].constant tbl? => 8.times.map {|i| func.(i).to_i }
+    tbl![addr]
+end
+
+
+
+system :test_rom do
+    [2..0].inner :addr
+    [7..0].inner :data0, :data1, :data2, :data3
+
+    data0 <= rom_gen(addr) { |i| i*i }
+    data1 <= rom_gen(addr) { |i| i*i }
+
+    par do
+        data2 <= rom_gen(addr) { |i| i*i }
+        data3 <= rom_gen(addr) { |i| i*i }
+    end
+
+    timed do
+        8.times do |i|
+            addr <= i
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_channel_other.rb

@@ -0,0 +1,128 @@
+require 'std/channel.rb'
+require 'std/hruby_unit.rb'
+
+include HDLRuby::High::Std
+
+# A clocked handshake channel for testing purpuse.
+channel(:handshake) do |typ,clk|
+    inner has_data: 0
+    inner :set_data
+    inner :get_data
+    typ.inner :data, :data_val
+
+    writer_input :has_data
+    writer_output :set_data, :data_val
+    reader_input :has_data, :data
+    reader_output :get_data
+
+    par(clk.negedge) do
+        hif(set_data) do
+            data <= data_val
+            has_data <= 1
+        end
+        helsif(get_data) do
+            has_data <= 0
+        end
+    end
+
+    # The writer.
+    writer do |blk,target|
+        hif(~has_data) do
+            set_data <= 1
+            data_val <= target
+            blk.call if blk
+        end
+        helse { set_data <= 0 }
+    end
+
+    # The reader
+    reader do |blk,target|
+        hif(has_data) do
+            target <= data
+            get_data <= 1
+            blk.call if blk
+        end
+        helse { get_data <= 0 }
+    end
+end
+
+
+
+# A system writing indefinitely to a channel.
+# Checking usage of channel without declaring a port.
+system :producer8 do |channel|
+    # Inputs of the producer: clock and reset.
+    input :clk, :rst
+    # Inner 8-bit counter for generating values.
+    [8].inner :counter
+
+    # The value production process
+    par(clk.posedge) do
+        hif(rst) { counter <= 0 }
+        helse do
+            channel.write(counter) { counter <= counter + 1 }
+        end
+    end
+end
+
+# A system reading indefinitely from a channel.
+system :consummer8 do |channel|
+    # Input of the consummer: a clock is enough.
+    input :clk
+    # # Instantiate the channel ports
+    # channel.input :ch
+    # Inner buffer for storing the cunsummed value.
+    [8].inner :buf
+
+    # The value consumption process
+    par(clk.posedge) do
+        channel.read(buf)
+    end
+end
+
+
+# A system testing the handshaker.
+Unit.system :hs_test do
+    inner :clk,:rst
+
+    # Declares two handshakers
+    handshake(bit[8],clk).(:hs)
+
+    # For the first handshake
+
+    # Instantiate the producer.
+    producer8(hs).(:producerI).(clk,rst)
+
+    # Instantiate the consummer.
+    consummer8(hs).(:consummerI).(clk)
+
+    test do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        10.times do
+            clk <= 0
+            !10.ns
+            clk <= 1
+            !10.ns
+        end
+    end
+
+end

data/lib/HDLRuby/hdr_samples/with_def.rb

@@ -0,0 +1,29 @@
+# A test of def.
+def lut84(content,addr)
+   bit[8][-4].inner tbl? => content.to_a
+   tbl![addr]
+end
+
+
+# A benchmark for testing the initialization of signals.
+system :def_bench do
+
+    [2].inner :addr
+    [8].inner :val0, :val1
+
+    par do
+        val0 <= lut84([0,1,4,9],addr)
+        val1 <= lut84([0,1,4,9],3-addr)
+    end
+
+    timed do
+        addr <= 0
+        !10.ns
+        addr <= 1
+        !10.ns
+        addr <= 2
+        !10.ns
+        addr <= 3
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_of.rb

@@ -0,0 +1,51 @@
+# Some abstract system.
+system :sysA do
+    input :clk,:rst
+    input :d
+    output :q
+end
+
+# Some inheriting system.
+system :sysH, sysA do
+    par(clk.posedge, rst.posedge) do
+        hprint("sys1\n")
+        q <= d & ~rst
+    end
+end
+
+# Another system that have nothing to see with the others.
+# Some abstract system.
+system :sysO do
+    input :clk,:rst
+    input :d
+    output :q
+
+    par(clk.posedge, rst.posedge) do
+        hprint("sys1\n")
+        q <= d & ~rst
+    end
+end
+
+
+# A system for testing inheritance and of?
+system :with_reconf do
+    input :clk,:rst
+    input :d
+    output :q
+
+    # Instantiate the abstract system.
+    sysA(:my_dffA).(clk,rst,d,q)
+
+    # Test the of?
+    puts "my_dffA.systemT.of?(sysA)=#{my_dffA.systemT.of?(sysA)}"
+    puts "my_dffA.systemT.of?(sysH)=#{my_dffA.systemT.of?(sysH)}"
+    puts "my_dffA.systemT.of?(sysO)=#{my_dffA.systemT.of?(sysO)}"
+
+    # Instantiate the inheriting system.
+    sysH(:my_dffH).(clk,rst,d,q)
+
+    # Test the of?
+    puts "my_dffH.systemT.of?(sysH)=#{my_dffH.systemT.of?(sysH)}"
+    puts "my_dffH.systemT.of?(sysA)=#{my_dffH.systemT.of?(sysA)}"
+    puts "my_dffH.systemT.of?(sysO)=#{my_dffH.systemT.of?(sysO)}"
+end

data/lib/HDLRuby/hdr_samples/with_reconf.rb

@@ -1,63 +1,14 @@
-require 'std/reconf.rb'
 
-include HDLRuby::High::Std
-
-
-
-
-# Implementation of a vivado partial reconfiguration system.
-reconf(:vivado_reconf) do |clk,rst|
-
-    # Get access to the interface of the reconfigurable component.
-    inputs = each_input
-    outputs = each_output
-    inouts = each_inout
-
-    # Create the main system with the interface and a channel for
-    # handling the reconfiguration.
-    main = system do
-        # Declares the inputs.
-        inputs.each do |i|
-            i.type.input(i.name)
-        end
-        # Declares the outputs.
-        outputs.each do |o|
-            o.type.output(o.name)
-        end
-        # Declares the inouts.
-        inouts.each do |io|
-            io.type.inout(io.name)
-        end
-        # An that's all: in vivado the main system is to be a black-box.
-    end
-
-    # And set it as the main system.
-    set_main(main)
-
-    # The switching circuit.
-    # reconfer = vivado_reconfigurer :do_reconf # Will be that later
-    # reconfer.clk <= clk 
-    # reconfer.rst <= rst 
-    reconfer = proc do |idx|
-        puts "Instantiating reconfiguration circuits with #{idx}"
-    end
-
-    # Defines the reconfiguring procedure: switch to system idx.
-    switcher do |idx,ruby_block|
-        reconfer.call(idx)
-        ruby_block.call
-    end
-
-end
-
-
-# Some system that can be used for recponfiguration.
+# Some system that can be used for reconfiguration.
 system :sys0 do
     input :clk,:rst
     input :d
     output :q
 
-    q <= d
+    par(clk.posedge) do
+        hprint("sys0\n")
+        q <= d & ~rst
+    end
 end
 
 system :sys1 do
@@ -65,7 +16,10 @@ system :sys1 do
     input :d
     output :q
 
-    (q <= d).at(clk.posedge)
+    par(clk.posedge, rst.posedge) do
+        hprint("sys1\n")
+        q <= d & ~rst
+    end
 end
 
 system :sys2 do
@@ -73,7 +27,10 @@ system :sys2 do
     input :d
     output :q
 
-    (q <= d & ~rst).at(clk.posedge)
+    par(clk.posedge, rst.negedge) do
+        hprint("sys2\n")
+        q <= d & ~rst
+    end
 end
 
 # A system with a reconfifurable part.
@@ -81,23 +38,69 @@ system :with_reconf do
     input :clk,:rst
     input :d
     output :q
-    [2].input :conf # The configuration number
-
-    inner :wait_reconf
 
-    # Create a reconfigurable component.
-    vivado_reconf(clk,rst).(:my_reconf)
-    # It is to be reconfigured to sys0, sys1 or sys2
-    my_reconf.(sys0, sys1, sys2)
-
-    # Connect the reconfigurable instance.
-    my_reconf.instance.(clk,rst,d,q)
-
-    par(clk.posedge) do
-        hif(rst) { wait_reconf <= 0 }
-        helsif(conf != 0 && my_reconf.index != conf && wait_reconf == 0) do
-            wait_reconf <= 1
-            my_reconf.switch(conf) { wait_reconf <= 0 }
+    # Instantiate the default configuration.
+    sys0(:my_dff).(clk,rst,d,q)
+
+    # Adds the additional configuration.
+    my_dff.choice(conf1: sys1, conf2: sys2)
+
+    timed do
+        clk <= 0
+        rst <= 0
+        d <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        3.times do |i|
+            clk <= 1
+            !10.ns
+            clk <= 0
+            d <= 1
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+            d <= 0
+            !10.ns
+            clk <= 1
+            my_dff.configure((i+1)%3)
+            !10.ns
+            clk <= 0
+            !10.ns
         end
+        clk <= 1
+        !10.ns
+        clk <= 0
+        d <= 1
+        !10.ns
+        clk <= 1
+        my_dff.configure(:conf1)
+        !10.ns
+        clk <= 0
+        d <= 0
+        !10.ns
+        clk <= 1
+        my_dff.configure(:conf2)
+        !10.ns
+        clk <= 0
+        d <= 1
+        !10.ns
+        clk <= 1
+        my_dff.configure(:my_dff)
+        !10.ns
+        clk <= 0
+        d <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
     end
 end

data/lib/HDLRuby/hdr_samples/with_terminate.rb

@@ -0,0 +1,32 @@
+
+# A benchmark for testing the terminate statement.
+system :with_terminate do
+    [8].constant cst0: 127
+    constant cst1: _1
+    [8].inner sig0: _10000000
+    inner sig1: _1
+    [8].inner :sig2
+    [8].inner count: 0
+
+    timed do
+        !20.ns
+        100.times do
+            count <= count + 1
+            !20.ns
+        end
+    end
+
+    timed do
+        !10.ns
+        sig2  <= cst0 + cst1
+        sig0  <= sig0 + sig1
+        !10.ns
+        sig2 <= sig2 + sig1
+        !10.ns
+        terminate
+        sig0 <= sig0 + sig0
+        !10.ns
+        sig0 <= sig0 + sig0
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdrcc.rb

@@ -647,12 +647,19 @@ elsif $options[:clang] then
         init_visualizer = $options[:vcd] ? "init_vcd_visualizer" :
                                            "init_default_visualizer"
 
+        # Gather the system to generate and sort them in the right order
+        # to ensure references are generated before being used.
+        # Base: reverse order of the tree.
+        # Then, multiple configuration of a system instance must be
+        # reverversed so that the base configuration is generated first.
+        c_systems = $top_system.each_systemT_deep_ref
         # Generate the code of the main function.
         # HDLRuby start code
         $main << HDLRuby::Low::Low2C.main("hruby_simulator",
                                          init_visualizer,
                                          $top_system,
-                                         $top_system.each_systemT_deep.to_a.reverse,$hnames)
+                                         c_systems,
+                                         $hnames)
         $main.close
 
         $top_system.each_systemT_deep do |systemT|