HDLRuby 2.7.1 → 2.8.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 4ca0e2aba73e7ceb55e145dd22286398ae7605d04d46212f870ba895d3f983d9
-  data.tar.gz: 434ae3eb4d974a00ea1510b0e23d66dc51d5f6ac5ef0e4b79af288b5d05f6985
+  metadata.gz: 90d139cd510b6600a32249a2e27969f6c415a49d9b26ba51ed84d20dcc82f2ba
+  data.tar.gz: b064d08cfbd46ae6fa4dffc7536a2dece4aed9c1c7588118502df79dd288c5bb
 SHA512:
-  metadata.gz: d097cbd7793ef60fd94c70f7a8acb2e49b13915fd799b7618523c1ba57300195a9ca8a7a61d6e50a8f89779ce6bf64a484bdf5267de93b3159f61186f40e6a82
-  data.tar.gz: 27db7c7e988abe14635a515572c2774e8a76d44e7f0e85bfb6ec8b1c9dfed85f61ef49e1f597c59fc9b725b6aacc53b976f73a3b49f816820c5ca9691e253559
+  metadata.gz: 40ced20f6723ff46f4c02a033c1d194e5ce267c75e7f2c22e6c70dd6f51ae9b530ebdc7dc7150970f3fefbf2ec4663c965a3a3fddf1c1b2369d6dac42317ba0c
+  data.tar.gz: 7782898ea6de9b5e42015f84dc56929ecd038baf42337c1f69f96bc644f0692ddd00ada0db0f9910b8ae7d93d2516ed4b3819c9f8735268d0a952f72b56bb37e

data/lib/HDLRuby/hdr_samples/adder_gen.rb

@@ -5,3 +5,25 @@ system :adder do |w|
 
     s <= x.as(bit[w+1]) + y
 end
+
+
+# Testing the generic adder.
+system :adder_bench do
+    width = 4
+    [width].inner :x,:y
+    [width+1].inner :z
+
+    adder(width).(:my_adder).(x,y,z)
+
+    timed do
+        x <= 0
+        y <= 0
+        !10.ns
+        x <= 1
+        !10.ns
+        y <= 1
+        !10.ns
+        x <= 15
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/adder_gen_gen.rb

@@ -0,0 +1,40 @@
+# A simple generic adder
+system :adder do |w|
+    [(w-1)..0].input :i,:j
+    [w..0].output :k
+
+    k <= i.as(bit[w+1]) + j
+end
+
+# A module embedding two generic adders.
+system :two_adders do |w|
+    [w*2].input :x, :y
+    [(w+1)*2].output :z
+
+    adder(w).(:adderI0).(x[(w-1)..0],y[(w-1)..0],z[w..0])
+    adder(w).(:adderI1).(x[(w*2-1)..w],y[(w*2-1)..w],z[(w*2+1)..(w+1)])
+end
+
+
+# Testing the generic adder.
+system :adder_bench do
+    width = 4
+    [width*2].inner :a,:b
+    [(width+1)*2].inner :c
+
+    two_adders(width).(:my_adders).(a,b,c)
+
+    timed do
+        a <= 0
+        b <= 0
+        !10.ns
+        a <= 1
+        !10.ns
+        b <= 1
+        !10.ns
+        a <= 255
+        !10.ns
+        b <= 128
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/case_bench.rb

@@ -1,30 +1,35 @@
 # Test the comparison operators.
 
-# A benchmark for the case statement.
+# A benchmark for the if statement.
 system :if_bench do
-    [8].inner :x, :y
+    [8].inner :x, :z
 
     par do
         hcase(x)
-        hwhen(0) { y <= _10000000 }
-        hwhen(1) { y <= _10000001 }
-        hwhen(2) { y <= _10000010 }
-        hwhen(3) { y <= _10000011 }
-        helse    { y <= _00000000 }
+        hwhen(0)  { z <= 0 }
+        hwhen(1)  { z <= 1 }
+        hwhen(2)  { z <= 4 }
+        hwhen(3)  { z <= 9 }
+        hwhen(4)  { z <= 16 }
+        hwhen(5)  { z <= 25 }
+        hwhen(6)  { z <= 36 }
+        hwhen(7)  { z <= 49 }
+        hwhen(8)  { z <= 64 }
+        hwhen(9)  { z <= 81 }
+        hwhen(10) { z <= 100 }
+        hwhen(11) { z <= 121 }
+        hwhen(12) { z <= 144 }
+        hwhen(13) { z <= 169 }
+        hwhen(14) { z <= 196 }
+        hwhen(15) { z <= 225 }
+        helse    { z <= _zzzzzzzz }
     end
 
     timed do
-        x <= 0
-        !10.ns
-        x <= 1
-        !10.ns
-        x <= 2
-        !10.ns
-        x <= 3
-        !10.ns
-        x <= 4
-        !10.ns
-        x <= 5
         !10.ns
+        20.times do |i|
+            x <= i
+            !10.ns
+        end
     end
 end

data/lib/HDLRuby/hdr_samples/dff_unit.rb

@@ -6,7 +6,7 @@
 3.times do |i|
 
     # A simple D-FF
-    system:"dff#{i}" do
+    system :"dff#{i}" do
         input :clk, :rst, :d
         output :q, :qb
 

data/lib/HDLRuby/hdr_samples/parseq_bench.rb

@@ -0,0 +1,61 @@
+# Check of various par and seq.
+
+# A benchmark for the dff.
+system :parseq_bench do
+    [4].inner :x0, :x1, :x2, :x3
+    [4].inner :y0, :y1, :y2, :y3
+    [4].inner :z00, :z01
+    [4].inner :z10, :z11
+    [4].inner :z20, :z21
+    [4].inner :z30, :z31
+    [4].inner :u0, :u1, :u2, :u3
+    bit[4][-16].constant mem: 16.times.to_a
+
+    par(x0) do
+        z00 <= x0 + y0
+        z01 <= z00 + 1
+        u0 <= mem[z00]
+    end
+
+    seq(y1) do
+        z10 <= x1 + y1
+        z11 <= z10 + 1
+        u1 <= mem[z10]
+    end
+
+    seq(x2,y2) do
+        z20 <= x2 + y2
+        z21 <= z20 + 1
+        u2 <= mem[z20]
+    end
+
+    par do
+        bit[4].constant inc: 1
+        z30 <= x3 + y3
+        z31 <= z30 + inc
+        u3 <= mem[z30]
+    end
+
+
+    timed do
+        x0 <= 1
+        x1 <= 1
+        x2 <= 1
+        x3 <= 1
+        !10.ns
+        y0 <= 2
+        y1 <= 2
+        y2 <= 2
+        y3 <= 2
+        !10.ns
+        x0 <= 3
+        x1 <= 3
+        x2 <= 3
+        x3 <= 3
+        y0 <= 4
+        y1 <= 4
+        y2 <= 4
+        y3 <= 4
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/range_bench.rb

@@ -3,13 +3,16 @@
 # A benchmark for the index access..
 system :if_bench do
     [8].inner :x
-    [2].inner :r0,:r1,:r2,:r3
+    [2].inner :r0,:r1,:r2,:r3, :r4
+    inner :r5
 
     par do
         r0 <= x[1..0]
         r1 <= x[3..2]
         r2 <= x[5..4]
         r3 <= x[7..6]
+        r4 <= x[-1..-2]
+        r5 <= x[-1]
     end
 
     timed do

data/lib/HDLRuby/hdr_samples/rom_nest.rb

@@ -0,0 +1,27 @@
+# Rom access generator, def case.
+def rom_gen(addr,&func)
+    bit[8][-8].constant tbl? => 8.times.map {|i| func.(i).to_i }
+    tbl![addr]
+end
+
+
+
+system :test_rom do
+    [2..0].inner :addr
+    [7..0].inner :data0, :data1, :data2, :data3
+
+    data0 <= rom_gen(addr) { |i| i*i }
+    data1 <= rom_gen(addr) { |i| i*i }
+
+    par do
+        data2 <= rom_gen(addr) { |i| i*i }
+        data3 <= rom_gen(addr) { |i| i*i }
+    end
+
+    timed do
+        8.times do |i|
+            addr <= i
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_channel_other.rb

@@ -0,0 +1,128 @@
+require 'std/channel.rb'
+require 'std/hruby_unit.rb'
+
+include HDLRuby::High::Std
+
+# A clocked handshake channel for testing purpuse.
+channel(:handshake) do |typ,clk|
+    inner has_data: 0
+    inner :set_data
+    inner :get_data
+    typ.inner :data, :data_val
+
+    writer_input :has_data
+    writer_output :set_data, :data_val
+    reader_input :has_data, :data
+    reader_output :get_data
+
+    par(clk.negedge) do
+        hif(set_data) do
+            data <= data_val
+            has_data <= 1
+        end
+        helsif(get_data) do
+            has_data <= 0
+        end
+    end
+
+    # The writer.
+    writer do |blk,target|
+        hif(~has_data) do
+            set_data <= 1
+            data_val <= target
+            blk.call if blk
+        end
+        helse { set_data <= 0 }
+    end
+
+    # The reader
+    reader do |blk,target|
+        hif(has_data) do
+            target <= data
+            get_data <= 1
+            blk.call if blk
+        end
+        helse { get_data <= 0 }
+    end
+end
+
+
+
+# A system writing indefinitely to a channel.
+# Checking usage of channel without declaring a port.
+system :producer8 do |channel|
+    # Inputs of the producer: clock and reset.
+    input :clk, :rst
+    # Inner 8-bit counter for generating values.
+    [8].inner :counter
+
+    # The value production process
+    par(clk.posedge) do
+        hif(rst) { counter <= 0 }
+        helse do
+            channel.write(counter) { counter <= counter + 1 }
+        end
+    end
+end
+
+# A system reading indefinitely from a channel.
+system :consummer8 do |channel|
+    # Input of the consummer: a clock is enough.
+    input :clk
+    # # Instantiate the channel ports
+    # channel.input :ch
+    # Inner buffer for storing the cunsummed value.
+    [8].inner :buf
+
+    # The value consumption process
+    par(clk.posedge) do
+        channel.read(buf)
+    end
+end
+
+
+# A system testing the handshaker.
+Unit.system :hs_test do
+    inner :clk,:rst
+
+    # Declares two handshakers
+    handshake(bit[8],clk).(:hs)
+
+    # For the first handshake
+
+    # Instantiate the producer.
+    producer8(hs).(:producerI).(clk,rst)
+
+    # Instantiate the consummer.
+    consummer8(hs).(:consummerI).(clk)
+
+    test do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        10.times do
+            clk <= 0
+            !10.ns
+            clk <= 1
+            !10.ns
+        end
+    end
+
+end

data/lib/HDLRuby/hdr_samples/with_def.rb

@@ -0,0 +1,29 @@
+# A test of def.
+def lut84(content,addr)
+   bit[8][-4].inner tbl? => content.to_a
+   tbl![addr]
+end
+
+
+# A benchmark for testing the initialization of signals.
+system :def_bench do
+
+    [2].inner :addr
+    [8].inner :val0, :val1
+
+    par do
+        val0 <= lut84([0,1,4,9],addr)
+        val1 <= lut84([0,1,4,9],3-addr)
+    end
+
+    timed do
+        addr <= 0
+        !10.ns
+        addr <= 1
+        !10.ns
+        addr <= 2
+        !10.ns
+        addr <= 3
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_init.rb

@@ -0,0 +1,18 @@
+
+# A benchmark for testing the initialization of signals.
+system :with_init do
+    [8].constant cst0: 127
+    constant cst1: _1
+    [8].inner sig0: _10000000
+    inner sig1: _1
+    [8].inner :sig2
+
+    timed do
+        !10.ns
+        sig2  <= cst0 + cst1
+        sig0  <= sig0 + sig1
+        !10.ns
+        sig2 <= sig2 + sig1
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_instance.rb

@@ -0,0 +1,42 @@
+
+
+
+# A benchmark for testing the instantiations.
+
+system :adder do |typ|
+    typ.input :x, :y
+    typ.output :z
+
+    z <= x + y
+end
+
+system :truc do
+    [8].input :u, :v
+    [8].output :q
+end
+
+
+
+system :with_instance do
+
+    [8].inner :x0, :y0, :z0, :x1, :y1, :z1
+
+    truc(:montruc).(x0,y0,z0)
+
+    adder(bit[8]).(:adderI0).(x0,y0,z0)
+    adder(bit[8]).(:adderI1).(x: x1, y: y1, z: z1)
+
+    timed do
+        !10.ns
+        x0 <= 0
+        y0 <= 0
+        x1 <= 1
+        y1 <= 1
+        !10.ns
+        x0 <= 1
+        y0 <= 1
+        x1 <= 2
+        y1 <= 2
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_reconf.rb

@@ -4,60 +4,16 @@ include HDLRuby::High::Std
 
 
 
-
-# Implementation of a vivado partial reconfiguration system.
-reconf(:vivado_reconf) do |clk,rst|
-
-    # Get access to the interface of the reconfigurable component.
-    inputs = each_input
-    outputs = each_output
-    inouts = each_inout
-
-    # Create the main system with the interface and a channel for
-    # handling the reconfiguration.
-    main = system do
-        # Declares the inputs.
-        inputs.each do |i|
-            i.type.input(i.name)
-        end
-        # Declares the outputs.
-        outputs.each do |o|
-            o.type.output(o.name)
-        end
-        # Declares the inouts.
-        inouts.each do |io|
-            io.type.inout(io.name)
-        end
-        # An that's all: in vivado the main system is to be a black-box.
-    end
-
-    # And set it as the main system.
-    set_main(main)
-
-    # The switching circuit.
-    # reconfer = vivado_reconfigurer :do_reconf # Will be that later
-    # reconfer.clk <= clk 
-    # reconfer.rst <= rst 
-    reconfer = proc do |idx|
-        puts "Instantiating reconfiguration circuits with #{idx}"
-    end
-
-    # Defines the reconfiguring procedure: switch to system idx.
-    switcher do |idx,ruby_block|
-        reconfer.call(idx)
-        ruby_block.call
-    end
-
-end
-
-
-# Some system that can be used for recponfiguration.
+# Some system that can be used for reconfiguration.
 system :sys0 do
     input :clk,:rst
     input :d
     output :q
 
-    q <= d
+    par(clk.posedge) do
+        hprint("sys0\n")
+        q <= d & ~rst
+    end
 end
 
 system :sys1 do
@@ -65,7 +21,10 @@ system :sys1 do
     input :d
     output :q
 
-    (q <= d).at(clk.posedge)
+    par(clk.posedge, rst.posedge) do
+        hprint("sys1\n")
+        q <= d & ~rst
+    end
 end
 
 system :sys2 do
@@ -73,7 +32,10 @@ system :sys2 do
     input :d
     output :q
 
-    (q <= d & ~rst).at(clk.posedge)
+    par(clk.posedge, rst.negedge) do
+        hprint("sys2\n")
+        q <= d & ~rst
+    end
 end
 
 # A system with a reconfifurable part.
@@ -81,23 +43,69 @@ system :with_reconf do
     input :clk,:rst
     input :d
     output :q
-    [2].input :conf # The configuration number
-
-    inner :wait_reconf
 
-    # Create a reconfigurable component.
-    vivado_reconf(clk,rst).(:my_reconf)
-    # It is to be reconfigured to sys0, sys1 or sys2
-    my_reconf.(sys0, sys1, sys2)
-
-    # Connect the reconfigurable instance.
-    my_reconf.instance.(clk,rst,d,q)
-
-    par(clk.posedge) do
-        hif(rst) { wait_reconf <= 0 }
-        helsif(conf != 0 && my_reconf.index != conf && wait_reconf == 0) do
-            wait_reconf <= 1
-            my_reconf.switch(conf) { wait_reconf <= 0 }
+    # Instantiate the default configuration.
+    sys0(:my_dff).(clk,rst,d,q)
+
+    # Adds the additional configuration.
+    my_dff.choice(conf1: sys1, conf2: sys2)
+
+    timed do
+        clk <= 0
+        rst <= 0
+        d <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        3.times do |i|
+            clk <= 1
+            !10.ns
+            clk <= 0
+            d <= 1
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+            d <= 0
+            !10.ns
+            clk <= 1
+            my_dff.configure((i+1)%3)
+            !10.ns
+            clk <= 0
+            !10.ns
         end
+        clk <= 1
+        !10.ns
+        clk <= 0
+        d <= 1
+        !10.ns
+        clk <= 1
+        my_dff.configure(:conf1)
+        !10.ns
+        clk <= 0
+        d <= 0
+        !10.ns
+        clk <= 1
+        my_dff.configure(:conf2)
+        !10.ns
+        clk <= 0
+        d <= 1
+        !10.ns
+        clk <= 1
+        my_dff.configure(:my_dff)
+        !10.ns
+        clk <= 0
+        d <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
     end
 end

data/lib/HDLRuby/hdr_samples/with_terminate.rb

@@ -0,0 +1,32 @@
+
+# A benchmark for testing the terminate statement.
+system :with_terminate do
+    [8].constant cst0: 127
+    constant cst1: _1
+    [8].inner sig0: _10000000
+    inner sig1: _1
+    [8].inner :sig2
+    [8].inner count: 0
+
+    timed do
+        !20.ns
+        100.times do
+            count <= count + 1
+            !20.ns
+        end
+    end
+
+    timed do
+        !10.ns
+        sig2  <= cst0 + cst1
+        sig0  <= sig0 + sig1
+        !10.ns
+        sig2 <= sig2 + sig1
+        !10.ns
+        terminate
+        sig0 <= sig0 + sig0
+        !10.ns
+        sig0 <= sig0 + sig0
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_values.rb

@@ -27,6 +27,9 @@ system :with_values do
         v64 <= 1
         v96 <= 1
         !10.ns
+        v1  <= _1010[2]
+        v8  <= _uhFF00[12..4]
+        !10.ns
         v8  <= 128
         v16 <= 128
         v32 <= 128