HDLRuby 2.6.23 → 2.7.5

Sign up to get free protection for your applications and to get access to all the features.
Files changed (30) hide show
  1. checksums.yaml +4 -4
  2. data/lib/HDLRuby/hdr_samples/case_bench.rb +35 -0
  3. data/lib/HDLRuby/hdr_samples/constant_in_function.rb +1 -1
  4. data/lib/HDLRuby/hdr_samples/if_bench.rb +24 -0
  5. data/lib/HDLRuby/hdr_samples/index_bench.rb +37 -0
  6. data/lib/HDLRuby/hdr_samples/range_bench.rb +47 -0
  7. data/lib/HDLRuby/hdr_samples/with_casts.rb +30 -0
  8. data/lib/HDLRuby/hdr_samples/with_concat.rb +26 -0
  9. data/lib/HDLRuby/hdr_samples/with_init.rb +18 -0
  10. data/lib/HDLRuby/hdr_samples/with_instance.rb +42 -0
  11. data/lib/HDLRuby/hdr_samples/with_ref_array.rb +26 -0
  12. data/lib/HDLRuby/hdr_samples/with_subsums.rb +33 -0
  13. data/lib/HDLRuby/hdr_samples/with_values.rb +61 -0
  14. data/lib/HDLRuby/hdrcc.rb +38 -25
  15. data/lib/HDLRuby/hruby_high.rb +37 -5
  16. data/lib/HDLRuby/hruby_low.rb +13 -1
  17. data/lib/HDLRuby/hruby_low2c.rb +1339 -556
  18. data/lib/HDLRuby/hruby_low_casts_without_expression.rb +1 -1
  19. data/lib/HDLRuby/hruby_low_mutable.rb +12 -0
  20. data/lib/HDLRuby/hruby_low_with_port.rb +21 -6
  21. data/lib/HDLRuby/hruby_low_without_namespace.rb +4 -2
  22. data/lib/HDLRuby/hruby_tools.rb +8 -1
  23. data/lib/HDLRuby/hruby_verilog.rb +218 -149
  24. data/lib/HDLRuby/sim/hruby_sim.h +117 -0
  25. data/lib/HDLRuby/sim/hruby_sim_calc.c +38 -9
  26. data/lib/HDLRuby/sim/hruby_sim_stack_calc.c +250 -0
  27. data/lib/HDLRuby/sim/hruby_sim_stack_calc.c.sav +100 -0
  28. data/lib/HDLRuby/sim/hruby_value_pool.c +36 -0
  29. data/lib/HDLRuby/version.rb +1 -1
  30. metadata +15 -2
data/lib/HDLRuby/hruby_verilog.rb CHANGED
@@ -56,7 +56,64 @@ module HDLRuby::Low
56
56
  end
57
57
 
58
58
  # Declaration of fm to manage each hash.
59
- $fm = Fm.new
59
+ # $fm = Fm.new
60
+ FmI = Fm.new
61
+
62
+
63
+ # Class for generating the truncating functions in verilog.
64
+ # Such function are necessary as expression cannot be truncated directly.
65
+ class Truncers
66
+ def initialize
67
+ @truncers = []
68
+ end
69
+
70
+ # Convert a range to an array.
71
+ def r2a(rng)
72
+ return [rng.first,rng.last]
73
+ end
74
+
75
+ # Add a truncer to of expression of bit range +rngI+ using +rngS+ slice.
76
+ def add(rngI,rngS)
77
+ # Convert the ranges to arrays.
78
+ rngI,rngS = self.r2a(rngI), self.r2a(rngS)
79
+ # Add them
80
+ @truncers << [rngI,rngS]
81
+ end
82
+ alias_method :<<, :add
83
+
84
+
85
+ # Generate a truncer function name for expression of bit range +rngI+ using +rngS+ slice.
86
+ def truncer_name(rngI,rngS)
87
+ # Convert the ranges to arrays.
88
+ rngI,rngS = self.r2a(rngI), self.r2a(rngS)
89
+ # Generate the name.
90
+ return "trunc_#{rngI[0]}_#{rngI[1]}_#{rngS[0]}_#{rngS[1]}"
91
+ end
92
+
93
+ # Generate the truncating functionds.
94
+ def dump
95
+ # Ensure there is only one truncating function per range.
96
+ @truncers.sort!.uniq!
97
+ # Generate the resulting code.
98
+ codeT = ""
99
+ @truncers.each do |(rngI,rngS)|
100
+ rngO = [rngS[0]-rngS[1],0]
101
+ codeT << " function [#{rngO[0]}:#{rngO[1]}] "
102
+ codeT << self.truncer_name(rngI,rngS)
103
+ codeT << "(input [#{rngI[0]}:#{rngI[1]}] val);\n"
104
+ codeT << " " << self.truncer_name(rngI,rngS) << " = "
105
+ codeT << "val[#{rngS[0]}:#{rngS[1]}];\n"
106
+ codeT << " endfunction\n\n"
107
+ end
108
+ # Clears the truncers.
109
+ @truncers = []
110
+ return codeT
111
+ end
112
+ end
113
+
114
+ # Declaration of the truncating function generator.
115
+ TruncersI = Truncers.new
116
+
60
117
 
61
118
  # A class that translates the left-hand side, operator, and right-hand side into form of expression.
62
119
  class Binary
@@ -75,10 +132,10 @@ module HDLRuby::Low
75
132
  left = self.left.to_change(mode)
76
133
  else
77
134
  # If you need to replace the variable, replace it. Otherwise we will get a clone.
78
- if $fm.fm_par.has_key?(self.left.to_verilog) && mode == :par then
79
- left = $fm.fm_par["#{self.left.to_verilog}"]
80
- elsif $fm.fm_seq.has_key?(self.left.to_verilog) && mode == :seq then
81
- left = $fm.fm_seq["#{self.left.to_verilog}"]
135
+ if FmI.fm_par.has_key?(self.left.to_verilog) && mode == :par then
136
+ left = FmI.fm_par["#{self.left.to_verilog}"]
137
+ elsif FmI.fm_seq.has_key?(self.left.to_verilog) && mode == :seq then
138
+ left = FmI.fm_seq["#{self.left.to_verilog}"]
82
139
  else
83
140
  left = self.left.clone
84
141
  end
@@ -88,10 +145,10 @@ module HDLRuby::Low
88
145
  right = self.right.to_change(mode)
89
146
  else
90
147
  # If you need to replace the variable, replace it. Otherwise we will get a clone.
91
- if $fm.fm_par.has_key?(self.right.to_verilog) && mode == :par then
92
- right = $fm.fm_par["#{self.right.to_verilog}"]
93
- elsif $fm.fm_seq.has_key?(self.right.to_verilog) && mode == :seq then
94
- right = $fm.fm_seq["#{self.right.to_verilog}"]
148
+ if FmI.fm_par.has_key?(self.right.to_verilog) && mode == :par then
149
+ right = FmI.fm_par["#{self.right.to_verilog}"]
150
+ elsif FmI.fm_seq.has_key?(self.right.to_verilog) && mode == :seq then
151
+ right = FmI.fm_seq["#{self.right.to_verilog}"]
95
152
  else
96
153
  right = self.right.clone
97
154
  end
@@ -230,7 +287,7 @@ module HDLRuby::Low
230
287
  code << "\n #{statement.to_verilog(block.mode.to_s)}"
231
288
  end
232
289
 
233
- $fm.fm_par.clear()
290
+ FmI.fm_par.clear()
234
291
 
235
292
  code << "\n end\n\n"
236
293
  end
@@ -283,9 +340,9 @@ module HDLRuby::Low
283
340
 
284
341
  new_statement = Transmit.new(search_refname(statement.left,"#"),statement.right.clone)
285
342
 
286
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
343
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
287
344
 
288
- $fm.fm_par["#{statement.left.to_verilog}"] = new_statement.left
345
+ FmI.fm_par["#{statement.left.to_verilog}"] = new_statement.left
289
346
  new_default.add_statement(new_statement.clone)
290
347
  else
291
348
  new_default.add_statement(statement.clone)
@@ -317,9 +374,9 @@ module HDLRuby::Low
317
374
 
318
375
  new_smt = Transmit.new(search_refname(statement.left,"#"),statement.right.clone)
319
376
 
320
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
377
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
321
378
 
322
- $fm.fm_par["#{statement.left.to_verilog}"] = new_smt.left
379
+ FmI.fm_par["#{statement.left.to_verilog}"] = new_smt.left
323
380
  new_when_smt.add_statement(new_smt.clone)
324
381
  else
325
382
  new_when_smt.add_statement(statement.clone)
@@ -335,11 +392,11 @@ module HDLRuby::Low
335
392
 
336
393
  new_block.add_statement(new_statement)
337
394
 
338
- $fm.rep_sharp.each_key do |key|
339
- new_smt = Transmit.new(key.clone,$fm.rep_sharp[key].clone)
395
+ FmI.rep_sharp.each_key do |key|
396
+ new_smt = Transmit.new(key.clone,FmI.rep_sharp[key].clone)
340
397
  new_block.add_statement(new_smt.clone)
341
398
  end
342
- $fm.rep_sharp.clear() # Deactivate rep that has become obsolete.
399
+ FmI.rep_sharp.clear() # Deactivate rep that has become obsolete.
343
400
 
344
401
  # If the statement is if, there is a block for each of yes, no, noifs, so translate each.
345
402
  elsif statement.is_a?(If) then
@@ -372,12 +429,12 @@ module HDLRuby::Low
372
429
 
373
430
  new_statement = Transmit.new(search_refname(statement.left,"#"),statement.right.clone)
374
431
 
375
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
432
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
376
433
 
377
434
  new_yes.add_statement(new_statement.clone)
378
435
 
379
436
 
380
- $fm.fm_par["#{statement.left.to_verilog}"] = new_statement.left
437
+ FmI.fm_par["#{statement.left.to_verilog}"] = new_statement.left
381
438
 
382
439
  else
383
440
  new_yes.add_statement(statement.clone)
@@ -419,9 +476,9 @@ module HDLRuby::Low
419
476
 
420
477
  new_statement = Transmit.new(search_refname(statement.left,"#"),statement.right.clone)
421
478
 
422
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
479
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
423
480
 
424
- $fm.fm_par["#{statement.left.to_verilog}"] = new_statement.left
481
+ FmI.fm_par["#{statement.left.to_verilog}"] = new_statement.left
425
482
  new_no.add_statement(new_statement.clone)
426
483
  else
427
484
  new_no.add_statement(statement.clone)
@@ -468,9 +525,9 @@ module HDLRuby::Low
468
525
 
469
526
  new_statement = Transmit.new(search_refname(statement.left,"#"),statement.right.clone)
470
527
 
471
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
528
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
472
529
 
473
- $fm.fm_par["#{statement.left.to_verilog}"] = new_statement.left
530
+ FmI.fm_par["#{statement.left.to_verilog}"] = new_statement.left
474
531
  new_noif.add_statement(new_statement.clone)
475
532
  else
476
533
  new_noif.add_statement(statement.clone)
@@ -485,17 +542,17 @@ module HDLRuby::Low
485
542
 
486
543
  new_block.add_statement(new_statement.clone)
487
544
 
488
- $fm.rep_sharp.each_key do |key|
489
- new_smt = Transmit.new(key.clone,$fm.rep_sharp[key].clone)
545
+ FmI.rep_sharp.each_key do |key|
546
+ new_smt = Transmit.new(key.clone,FmI.rep_sharp[key].clone)
490
547
  new_block.add_statement(new_smt.clone)
491
548
  end
492
- $fm.rep_sharp.clear() # Deactivate rep that has become obsolete.
549
+ FmI.rep_sharp.clear() # Deactivate rep that has become obsolete.
493
550
 
494
551
  # Process when "statement" is "Transmit" (just expression).
495
552
  # Record the expression in fm_par used for par-> seq and add the expression to new_block which is the "new block".
496
553
  elsif statement.is_a?(Transmit) then
497
554
  if self.mode == :seq then
498
- $fm.fm_par["#{statement.left.to_verilog}"] = statement.right
555
+ FmI.fm_par["#{statement.left.to_verilog}"] = statement.right
499
556
  end
500
557
  new_block.add_statement(statement.clone)
501
558
 
@@ -517,7 +574,7 @@ module HDLRuby::Low
517
574
  smt.each_statement do |tmt|
518
575
  # Retrieve the RefName of the variable on the left side and store it in this_name.
519
576
  if ((tmt.is_a? (Transmit)) && (self.mode == :seq)) then
520
- $fm.fm_par["#{tmt.left.to_verilog}"] = tmt.right
577
+ FmI.fm_par["#{tmt.left.to_verilog}"] = tmt.right
521
578
  end
522
579
  new_block.add_statement(tmt.clone)
523
580
  end
@@ -566,9 +623,9 @@ module HDLRuby::Low
566
623
 
567
624
  new_statement = Transmit.new(search_refname(statement.left,"#"),statement.right.clone)
568
625
 
569
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
626
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
570
627
 
571
- $fm.fm_par["#{statement.left.to_verilog}"] = new_statement.left
628
+ FmI.fm_par["#{statement.left.to_verilog}"] = new_statement.left
572
629
  new_yes.add_statement(new_statement.clone)
573
630
  else
574
631
  new_yes.add_statement(statement.clone)
@@ -610,9 +667,9 @@ module HDLRuby::Low
610
667
 
611
668
  new_statement = Transmit.new(search_refname(statement.left,"#"),statement.right.clone)
612
669
 
613
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
670
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
614
671
 
615
- $fm.fm_par["#{statement.left.to_verilog}"] = new_statement.left
672
+ FmI.fm_par["#{statement.left.to_verilog}"] = new_statement.left
616
673
  new_no.add_statement(new_statement.clone)
617
674
  else
618
675
  new_no.add_statement(statement.clone)
@@ -658,9 +715,9 @@ module HDLRuby::Low
658
715
 
659
716
  new_statement = Transmit.new(search_refname(statement.left,"#"),statement.right.clone)
660
717
 
661
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
718
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
662
719
 
663
- $fm.fm_par["#{statement.left.to_verilog}"] = new_statement.left
720
+ FmI.fm_par["#{statement.left.to_verilog}"] = new_statement.left
664
721
  new_noif.add_statement(new_statement.clone)
665
722
  else
666
723
  new_noif.add_statement(statement.clone)
@@ -675,11 +732,11 @@ module HDLRuby::Low
675
732
 
676
733
  new_block.add_statement(new_statement.clone)
677
734
 
678
- $fm.rep_sharp.each_key do |key|
679
- new_smt = Transmit.new(key.clone,$fm.rep_sharp[key].clone)
735
+ FmI.rep_sharp.each_key do |key|
736
+ new_smt = Transmit.new(key.clone,FmI.rep_sharp[key].clone)
680
737
  new_block.add_statement(new_smt.clone)
681
738
  end
682
- $fm.rep_sharp.clear() # Deactivate rep that has become obsolete.
739
+ FmI.rep_sharp.clear() # Deactivate rep that has become obsolete.
683
740
 
684
741
  elsif statement.is_a?(Case) then
685
742
  if statement.default.is_a?(Block)
@@ -714,8 +771,8 @@ module HDLRuby::Low
714
771
  if (self.each_statement.find {|stmnt| stmnt.is_a?(Block)} || (self.each_statement.find {|stmnt| stmnt.is_a?(If)}) || (self.each_statement.find {|stmnt| stmnt.is_a?(Case)}))then
715
772
  # In the case of seq, the lower layer is par. Isolate fm_par so that it is not crosstalked.
716
773
  if(self.mode == :seq) then
717
- fm_buckup = $fm.fm_par.clone
718
- $fm.fm_par.clear()
774
+ fm_buckup = FmI.fm_par.clone
775
+ FmI.fm_par.clear()
719
776
 
720
777
  new_block = change_branch(self)
721
778
  else
@@ -727,7 +784,7 @@ module HDLRuby::Low
727
784
  # If statement is If, convert yes, no, noif and add them to flat.
728
785
  if statement.is_a?(Case) then
729
786
  if(self.mode == :seq) then
730
- fm_buckup_if = $fm.fm_par.clone
787
+ fm_buckup_if = FmI.fm_par.clone
731
788
  end
732
789
 
733
790
  if statement.default.is_a?(Block)
@@ -745,7 +802,7 @@ module HDLRuby::Low
745
802
  statement.each_when do |whens|
746
803
  if(self.mode == :seq) then
747
804
  fm_buckup_if.each_key do |key|
748
- $fm.fm_par[key] = fm_buckup_if[key]
805
+ FmI.fm_par[key] = fm_buckup_if[key]
749
806
  end
750
807
  end
751
808
 
@@ -757,7 +814,7 @@ module HDLRuby::Low
757
814
 
758
815
  elsif statement.is_a?(If) then
759
816
  if(self.mode == :seq) then
760
- fm_buckup_if = $fm.fm_par.clone
817
+ fm_buckup_if = FmI.fm_par.clone
761
818
  end
762
819
 
763
820
  # Since yes always exist, convert without confirming.
@@ -768,7 +825,7 @@ module HDLRuby::Low
768
825
 
769
826
  if(self.mode == :seq) then
770
827
  fm_buckup_if.each_key do |key|
771
- $fm.fm_par[key] = fm_buckup_if[key]
828
+ FmI.fm_par[key] = fm_buckup_if[key]
772
829
  end
773
830
  end
774
831
 
@@ -781,7 +838,7 @@ module HDLRuby::Low
781
838
  statement.each_noif do |condition, block|
782
839
  if(self.mode == :seq) then
783
840
  fm_buckup_if.each_key do |key|
784
- $fm.fm_par[key] = fm_buckup_if[key]
841
+ FmI.fm_par[key] = fm_buckup_if[key]
785
842
  end
786
843
  end
787
844
 
@@ -794,7 +851,7 @@ module HDLRuby::Low
794
851
  # If statement is Transmit, record the expression in fm_par and add the expression to flat as it is.
795
852
  elsif statement.is_a?(Transmit) then
796
853
  if(self.mode == :seq) then
797
- $fm.fm_par["#{statement.left.to_verilog}"] = statement.right.clone
854
+ FmI.fm_par["#{statement.left.to_verilog}"] = statement.right.clone
798
855
  end
799
856
 
800
857
  flat.add_statement(statement.clone)
@@ -821,7 +878,7 @@ module HDLRuby::Low
821
878
  # If it is seq, the expression after conversion is also likely to be used, so record the expression.
822
879
  smt.each_statement do |tmt|
823
880
  if self.mode == :seq then
824
- $fm.fm_par["#{tmt.left.to_verilog}"] = tmt.right.clone
881
+ FmI.fm_par["#{tmt.left.to_verilog}"] = tmt.right.clone
825
882
  end
826
883
  flat.add_statement(tmt.clone)
827
884
  end
@@ -830,9 +887,9 @@ module HDLRuby::Low
830
887
 
831
888
  # Overwrite to restore fm_par which was quarantined.
832
889
  if(self.mode == :seq) then
833
- $fm.fm_par.clear()
890
+ FmI.fm_par.clear()
834
891
  fm_buckup.each_key do |key|
835
- $fm.fm_par[key] = fm_buckup[key]
892
+ FmI.fm_par[key] = fm_buckup[key]
836
893
  end
837
894
  end
838
895
 
@@ -846,11 +903,11 @@ module HDLRuby::Low
846
903
  trans.each_statement do |statement|
847
904
  replase.add_statement(statement.clone)
848
905
  if statement.is_a?(If)
849
- $fm.rep_sharp.each_key do |key|
850
- new_statement = Transmit.new(key.clone,$fm.rep_sharp[key].clone)
906
+ FmI.rep_sharp.each_key do |key|
907
+ new_statement = Transmit.new(key.clone,FmI.rep_sharp[key].clone)
851
908
  replase.add_statement(new_statement.clone)
852
909
  end
853
- $fm.rep_sharp.clear() # Deactivate rep that has become obsolete.
910
+ FmI.rep_sharp.clear() # Deactivate rep that has become obsolete.
854
911
  end
855
912
  end
856
913
 
@@ -882,7 +939,7 @@ module HDLRuby::Low
882
939
  list = []
883
940
 
884
941
  if rst == false then
885
- fm_seq_backup = $fm.fm_seq.dup
942
+ fm_seq_backup = FmI.fm_seq.dup
886
943
  end
887
944
 
888
945
  # The statement is divided (since it is the lowest layer, there is only Transmit).
@@ -896,12 +953,12 @@ module HDLRuby::Low
896
953
  elsif statement.is_a?(Case) then
897
954
 
898
955
  if statement.default.is_a?(Block)
899
- rep_buckup = $fm.rep.dup
900
- $fm.rep.clear()
956
+ rep_buckup = FmI.rep.dup
957
+ FmI.rep.clear()
901
958
  default = statement.default.to_conversion(mode,false,false)
902
- $fm.rep.clear()
959
+ FmI.rep.clear()
903
960
  rep_buckup.each_key do |key|
904
- $fm.rep[key] = rep_buckup[key]
961
+ FmI.rep[key] = rep_buckup[key]
905
962
  end
906
963
 
907
964
  new_default = Block.new(default.mode,"")
@@ -931,9 +988,9 @@ module HDLRuby::Low
931
988
 
932
989
  new_smt = Transmit.new(search_refname(statement.left,"#"),statement.right.clone)
933
990
 
934
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
991
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
935
992
 
936
- $fm.fm_par["#{statement.left.to_verilog}"] = new_smt.left
993
+ FmI.fm_par["#{statement.left.to_verilog}"] = new_smt.left
937
994
  new_default.add_statement(new_smt.clone)
938
995
  else
939
996
  new_default.add_statement(statement.clone)
@@ -949,12 +1006,12 @@ module HDLRuby::Low
949
1006
 
950
1007
  statement.each_when do |whens|
951
1008
 
952
- rep_buckup = $fm.rep.dup
953
- $fm.rep.clear()
1009
+ rep_buckup = FmI.rep.dup
1010
+ FmI.rep.clear()
954
1011
  when_smt = whens.statement.to_conversion(mode,false,false)
955
- $fm.rep.clear()
1012
+ FmI.rep.clear()
956
1013
  rep_buckup.each_key do |key|
957
- $fm.rep[key] = rep_buckup[key]
1014
+ FmI.rep[key] = rep_buckup[key]
958
1015
  end
959
1016
 
960
1017
  new_when_smt = Block.new(when_smt.mode,"")
@@ -974,9 +1031,9 @@ module HDLRuby::Low
974
1031
 
975
1032
  new_smt = Transmit.new(search_refname(statement.left,"#"),statement.right.clone)
976
1033
 
977
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
1034
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
978
1035
 
979
- $fm.fm_par["#{statement.left.to_verilog}"] = new_smt.left
1036
+ FmI.fm_par["#{statement.left.to_verilog}"] = new_smt.left
980
1037
  new_when_smt.add_statement(new_smt.clone)
981
1038
  else
982
1039
  new_when_smt.add_statement(statement.clone)
@@ -992,12 +1049,12 @@ module HDLRuby::Low
992
1049
 
993
1050
  elsif statement.is_a?(If) then
994
1051
 
995
- rep_buckup = $fm.rep.dup
996
- $fm.rep.clear()
1052
+ rep_buckup = FmI.rep.dup
1053
+ FmI.rep.clear()
997
1054
  yes = statement.yes.to_conversion(mode, false,false)
998
- $fm.rep.clear()
1055
+ FmI.rep.clear()
999
1056
  rep_buckup.each_key do |key|
1000
- $fm.rep[key] = rep_buckup[key]
1057
+ FmI.rep[key] = rep_buckup[key]
1001
1058
  end
1002
1059
 
1003
1060
  yes.each_inner do |inner|
@@ -1020,9 +1077,9 @@ module HDLRuby::Low
1020
1077
 
1021
1078
  yes_statement = Transmit.new(search_refname(smt.left,"#"),smt.right.clone)
1022
1079
 
1023
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
1080
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
1024
1081
 
1025
- $fm.fm_par["#{smt.left.to_verilog}"] = yes_statement.left
1082
+ FmI.fm_par["#{smt.left.to_verilog}"] = yes_statement.left
1026
1083
  new_yes.add_statement(yes_statement)
1027
1084
  else
1028
1085
  new_yes.add_statement(smt.clone)
@@ -1030,12 +1087,12 @@ module HDLRuby::Low
1030
1087
  end
1031
1088
 
1032
1089
  if statement.no.is_a? (Block) then
1033
- rep_buckup = $fm.rep.dup
1034
- $fm.rep.clear()
1090
+ rep_buckup = FmI.rep.dup
1091
+ FmI.rep.clear()
1035
1092
  no = statement.no.to_conversion(mode,false,false)
1036
- $fm.rep.clear()
1093
+ FmI.rep.clear()
1037
1094
  rep_buckup.each_key do |key|
1038
- $fm.rep[key] = rep_buckup[key]
1095
+ FmI.rep[key] = rep_buckup[key]
1039
1096
  end
1040
1097
 
1041
1098
  no.each_inner do |inner|
@@ -1058,9 +1115,9 @@ module HDLRuby::Low
1058
1115
 
1059
1116
  no_statement = Transmit.new(search_refname(smt.left,"#"),smt.right.clone)
1060
1117
 
1061
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
1118
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
1062
1119
 
1063
- $fm.fm_par["#{smt.left.to_verilog}"] = no_statement.left
1120
+ FmI.fm_par["#{smt.left.to_verilog}"] = no_statement.left
1064
1121
  new_no.add_statement(no_statement)
1065
1122
  else
1066
1123
  new_no.add_statement(smt.clone)
@@ -1071,12 +1128,12 @@ module HDLRuby::Low
1071
1128
  new_statement = If.new(statement.condition.clone,new_yes.clone,statement.no ? new_no.clone : nil)
1072
1129
 
1073
1130
  statement.each_noif do |condition, block|
1074
- rep_buckup = $fm.rep.dup
1075
- $fm.rep.clear()
1131
+ rep_buckup = FmI.rep.dup
1132
+ FmI.rep.clear()
1076
1133
  noif = block.to_conversion(mode,false,false)
1077
- $fm.rep.clear()
1134
+ FmI.rep.clear()
1078
1135
  rep_buckup.each_key do |key|
1079
- $fm.rep[key] = rep_buckup[key]
1136
+ FmI.rep[key] = rep_buckup[key]
1080
1137
  end
1081
1138
 
1082
1139
  noif.each_inner do |inner|
@@ -1099,9 +1156,9 @@ module HDLRuby::Low
1099
1156
 
1100
1157
  noif_statement = Transmit.new(search_refname(smt.left,"#"),smt.right.clone)
1101
1158
 
1102
- $fm.rep_sharp[statement.left] = search_refname(statement.left,"#")
1159
+ FmI.rep_sharp[statement.left] = search_refname(statement.left,"#")
1103
1160
 
1104
- $fm.fm_par["#{smt.left.to_verilog}"] = noif_statement.left
1161
+ FmI.fm_par["#{smt.left.to_verilog}"] = noif_statement.left
1105
1162
  new_noif.add_statement(no_statement)
1106
1163
  else
1107
1164
  new_noif.add_statement(smt.clone)
@@ -1118,10 +1175,10 @@ module HDLRuby::Low
1118
1175
  # Check the right side and the left side, and if they are variables, check the corresponding expressions and replace them.
1119
1176
  # If it is not a variable, it calls the method to be searched.
1120
1177
  if statement.right.left.is_a? (Ref) then
1121
- if (mode == :par && self.mode == :seq) && $fm.fm_seq.has_key?(statement.right.left.to_verilog) then
1122
- statement_left = $fm.fm_seq["#{statement.right.left.to_verilog}"]
1123
- elsif (mode == :seq && self.mode == :par) && $fm.fm_par.has_key?(statement.right.left.to_verilog) then
1124
- statement_left = $fm.fm_par["#{statement.right.left.to_verilog}"]
1178
+ if (mode == :par && self.mode == :seq) && FmI.fm_seq.has_key?(statement.right.left.to_verilog) then
1179
+ statement_left = FmI.fm_seq["#{statement.right.left.to_verilog}"]
1180
+ elsif (mode == :seq && self.mode == :par) && FmI.fm_par.has_key?(statement.right.left.to_verilog) then
1181
+ statement_left = FmI.fm_par["#{statement.right.left.to_verilog}"]
1125
1182
  else
1126
1183
  statement_left = statement.right.left.clone
1127
1184
  end
@@ -1132,10 +1189,10 @@ module HDLRuby::Low
1132
1189
  end
1133
1190
 
1134
1191
  if statement.right.right.is_a? (Ref) then
1135
- if (mode == :par && self.mode == :seq) && $fm.fm_seq.has_key?(statement.right.right.to_verilog) then
1136
- statement_right = $fm.fm_seq["#{statement.right.right.to_verilog}"]
1137
- elsif (mode == :seq && self.mode == :par) && $fm.fm_par.has_key?(statement.right.right.to_verilog) then
1138
- statement_right = $fm.fm_par["#{statement.right.right.to_verilog}"]
1192
+ if (mode == :par && self.mode == :seq) && FmI.fm_seq.has_key?(statement.right.right.to_verilog) then
1193
+ statement_right = FmI.fm_seq["#{statement.right.right.to_verilog}"]
1194
+ elsif (mode == :seq && self.mode == :par) && FmI.fm_par.has_key?(statement.right.right.to_verilog) then
1195
+ statement_right = FmI.fm_par["#{statement.right.right.to_verilog}"]
1139
1196
  else
1140
1197
  statement_right = statement.right.right.clone
1141
1198
  end
@@ -1147,10 +1204,10 @@ module HDLRuby::Low
1147
1204
  new_right = Binary.new(statement.right.type,statement.right.operator,statement_left.clone,statement_right.clone)
1148
1205
  # Confirm whether it is a variable.
1149
1206
  elsif statement.right.is_a?(Ref) then
1150
- if (mode == :par && self.mode == :seq) && $fm.fm_seq.has_key?(statement.right.to_verilog) then
1151
- new_right = $fm.fm_seq["#{statement.right.to_verilog}"].clone
1152
- elsif (mode == :seq && self.mode == :par) && $fm.fm_par.has_key?(statement.right.to_verilog) then
1153
- new_right = $fm.fm_par["#{statement.right.to_verilog}"].clone
1207
+ if (mode == :par && self.mode == :seq) && FmI.fm_seq.has_key?(statement.right.to_verilog) then
1208
+ new_right = FmI.fm_seq["#{statement.right.to_verilog}"].clone
1209
+ elsif (mode == :seq && self.mode == :par) && FmI.fm_par.has_key?(statement.right.to_verilog) then
1210
+ new_right = FmI.fm_par["#{statement.right.to_verilog}"].clone
1154
1211
  else
1155
1212
  new_right = statement.right.clone
1156
1213
  end
@@ -1163,7 +1220,7 @@ module HDLRuby::Low
1163
1220
  # Dock the existing left hand side and the replaced right hand side to create a new expression.
1164
1221
  # Record the expression after conversion to hash to continue seq-> par.
1165
1222
  new_statement = Transmit.new(statement.left.clone,new_right)
1166
- $fm.fm_seq["#{statement.left.to_verilog}"] = new_right
1223
+ FmI.fm_seq["#{statement.left.to_verilog}"] = new_right
1167
1224
  elsif (mode == :seq && self.mode == :par) && (rep) then
1168
1225
  unless (res_name(statement.left).name.to_s.include? "#")
1169
1226
  # Search the variable on the left side and give 'to the name.
@@ -1176,7 +1233,7 @@ module HDLRuby::Low
1176
1233
 
1177
1234
  new_statement = Transmit.new(search_refname(statement.left,"'"),new_right)
1178
1235
 
1179
- $fm.rep[statement.left] = new_statement
1236
+ FmI.rep[statement.left] = new_statement
1180
1237
  end
1181
1238
  else
1182
1239
  new_statement = Transmit.new(statement.left.clone,new_right)
@@ -1193,34 +1250,34 @@ module HDLRuby::Low
1193
1250
  end
1194
1251
 
1195
1252
  if (rep)
1196
- $fm.rep_sharp.each_key do |key|
1197
- new_smt = Transmit.new(key.clone,$fm.rep_sharp[key].clone)
1253
+ FmI.rep_sharp.each_key do |key|
1254
+ new_smt = Transmit.new(key.clone,FmI.rep_sharp[key].clone)
1198
1255
  flat.add_statement(new_smt.clone)
1199
1256
  end
1200
- $fm.rep_sharp.clear() # Deactivate rep that has become obsolete.
1257
+ FmI.rep_sharp.clear() # Deactivate rep that has become obsolete.
1201
1258
  end
1202
1259
  end
1203
1260
  # Add an expression after paragraph based on rep.
1204
1261
  # A complement expression like x = x '.
1205
- $fm.rep.each_key do |key|
1206
- new_statement = Transmit.new(key.clone,$fm.rep[key].left.clone)
1262
+ FmI.rep.each_key do |key|
1263
+ new_statement = Transmit.new(key.clone,FmI.rep[key].left.clone)
1207
1264
  flat.add_statement(new_statement.clone)
1208
1265
  end
1209
- $fm.rep.clear() # Deactivate rep that has become obsolete.
1266
+ FmI.rep.clear() # Deactivate rep that has become obsolete.
1210
1267
 
1211
1268
 
1212
1269
  # Since seq -> par is the end, fm_par is deleted.
1213
1270
  if (mode == :par && self.mode == :seq) then
1214
- $fm.fm_seq.clear()
1271
+ FmI.fm_seq.clear()
1215
1272
  end
1216
1273
 
1217
1274
  # In case of if statement (when rst == false) you can not convert no or else if you delete the contents of fm_seq.
1218
1275
  # Therefore, in this case restore the backup to restore.
1219
1276
  # This means that it is necessary to erase fm_seq once obtained in the if statement once.
1220
1277
  if(rst == false) then
1221
- $fm.fm_seq.clear()
1278
+ FmI.fm_seq.clear()
1222
1279
  fm_seq_backup.each_key do |key|
1223
- $fm.fm_seq[key] = fm_seq_backup[key]
1280
+ FmI.fm_seq[key] = fm_seq_backup[key]
1224
1281
  end
1225
1282
  end
1226
1283
 
@@ -1650,7 +1707,9 @@ module HDLRuby::Low
1650
1707
  "#{self.child.to_verilog}})"
1651
1708
  elsif (sw<cw) then
1652
1709
  # Need to truncate
1653
- return "$signed(#{self.child.to_verilog}[#{sw-1}:0])"
1710
+ # return "$signed(#{self.child.to_verilog}[#{sw-1}:0])"
1711
+ TruncersI.add((cw-1)..0,(sw-1)..0)
1712
+ return "$signed(#{TruncersI.truncer_name((cw-1)..0,(sw-1)..0)}(#{self.child.to_verilog}))"
1654
1713
  else
1655
1714
  # Only enforce signed.
1656
1715
  return "$signed(#{self.child.to_verilog})"
@@ -1661,7 +1720,9 @@ module HDLRuby::Low
1661
1720
  return "$unsigned({{#{sw-cw}{1'b0}},#{self.child.to_verilog}})"
1662
1721
  elsif (sw<cw) then
1663
1722
  # Need to truncate
1664
- return "$unsigned(#{self.child.to_verilog}[#{sw-1}:0])"
1723
+ # return "$unsigned(#{self.child.to_verilog}[#{sw-1}:0])"
1724
+ TruncersI.add((cw-1)..0,(sw-1)..0)
1725
+ return "$unsigned(#{TruncersI.truncer_name((cw-1)..0,(sw-1)..0)}(#{self.child.to_verilog}))"
1665
1726
  else
1666
1727
  # Only enforce signed.
1667
1728
  return "$unsigned(#{self.child.to_verilog})"
@@ -1940,62 +2001,65 @@ module HDLRuby::Low
1940
2001
  end
1941
2002
  end
1942
2003
 
2004
+ # Generate content code.
2005
+ codeC = ""
2006
+
1943
2007
  # Declare "inner".
1944
2008
  self.each_inner do |inner|
1945
2009
  if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
1946
- code << " reg"
2010
+ codeC << " reg"
1947
2011
  else
1948
- code << " wire"
2012
+ codeC << " wire"
1949
2013
  end
1950
2014
 
1951
2015
  if inner.type.base?
1952
2016
  if inner.type.base.base?
1953
- code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
2017
+ codeC << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
1954
2018
  else
1955
- code << "#{inner.type.to_verilog} #{inner.to_verilog}"
2019
+ codeC << "#{inner.type.to_verilog} #{inner.to_verilog}"
1956
2020
  end
1957
2021
  else
1958
- code << " #{inner.type.to_verilog}#{inner.to_verilog}"
2022
+ codeC << " #{inner.type.to_verilog}#{inner.to_verilog}"
1959
2023
  end
1960
2024
  if inner.value then
1961
2025
  # There is an initial value.
1962
- code << " = #{inner.value.to_verilog}"
2026
+ codeC << " = #{inner.value.to_verilog}"
1963
2027
  end
1964
- code << ";\n"
2028
+ codeC << ";\n"
1965
2029
  end
1966
2030
 
1967
2031
  # If there is scope in scope, translate it.
1968
2032
  self.each_scope do |scope|
1969
2033
  scope.each_inner do |inner|
1970
2034
  if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
1971
- code << " reg "
2035
+ codeC << " reg "
1972
2036
  else
1973
- code << " wire "
2037
+ codeC << " wire "
1974
2038
  end
1975
2039
 
1976
2040
  if inner.type.respond_to? (:base)
1977
2041
  if inner.type.base.base?
1978
- code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
2042
+ codeC << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
1979
2043
  else
1980
- code << "#{inner.type.to_verilog} #{inner.to_verilog}"
2044
+ codeC << "#{inner.type.to_verilog} #{inner.to_verilog}"
1981
2045
  end
1982
2046
  else
1983
- code << "inner #{inner.type.to_verilog} #{inner.to_verilog}"
2047
+ codeC << "inner #{inner.type.to_verilog} #{inner.to_verilog}"
1984
2048
  end
1985
2049
  if inner.value then
1986
2050
  # There is an initial value.
1987
- code << " = #{inner.value.to_verilog}"
2051
+ codeC << " = #{inner.value.to_verilog}"
1988
2052
  end
1989
- code << ";\n"
2053
+ codeC << ";\n"
1990
2054
  end
1991
2055
 
1992
2056
  scope.each_connection do |connection|
1993
- code << "\n"
1994
- code << "#{connection.to_verilog}"
2057
+ codeC << "\n"
2058
+ codeC << "#{connection.to_verilog}"
1995
2059
  end
1996
2060
  end
1997
2061
 
1998
- code << "\n"
2062
+ codeC << "\n"
1999
2063
 
2000
2064
  # puts "For system=#{self.name}"
2001
2065
  # transliation of the instantiation part.
@@ -2003,50 +2067,50 @@ module HDLRuby::Low
2003
2067
  self.each_systemI do |systemI|
2004
2068
  # puts "Processing systemI = #{systemI.name}"
2005
2069
  # Its Declaration.
2006
- code << " " * 3
2070
+ codeC << " " * 3
2007
2071
  systemT = systemI.systemT
2008
- code << name_to_verilog(systemT.name) << " "
2072
+ codeC << name_to_verilog(systemT.name) << " "
2009
2073
  vname = name_to_verilog(systemI.name)
2010
2074
  # systemI.properties[:verilog_name] = vname
2011
- code << vname << "("
2075
+ codeC << vname << "("
2012
2076
  # Its ports connections
2013
2077
  # Inputs
2014
2078
  systemT.each_input do |input|
2015
2079
  ref = self.extract_port_assign!(systemI,input)
2016
2080
  if ref then
2017
- code << "." << name_to_verilog(input.name) << "("
2018
- code << ref.to_verilog
2019
- code << "),"
2081
+ codeC << "." << name_to_verilog(input.name) << "("
2082
+ codeC << ref.to_verilog
2083
+ codeC << "),"
2020
2084
  end
2021
2085
  end
2022
2086
  # Outputs
2023
2087
  systemT.each_output do |output|
2024
2088
  ref = self.extract_port_assign!(systemI,output)
2025
2089
  if ref then
2026
- code << "." << name_to_verilog(output.name) << "("
2027
- code << ref.to_verilog
2028
- code << "),"
2090
+ codeC << "." << name_to_verilog(output.name) << "("
2091
+ codeC << ref.to_verilog
2092
+ codeC << "),"
2029
2093
  end
2030
2094
  end
2031
2095
  # Inouts
2032
2096
  systemT.each_inout do |inout|
2033
2097
  ref = self.extract_port_assign!(systemI,inout)
2034
2098
  if ref then
2035
- code << "." << name_to_verilog(inout.name) << "("
2036
- code << ref.to_verilog
2037
- code << "),"
2099
+ codeC << "." << name_to_verilog(inout.name) << "("
2100
+ codeC << ref.to_verilog
2101
+ codeC << "),"
2038
2102
  end
2039
2103
  end
2040
2104
  # Remove the last "," for conforming with Verilog syntax.
2041
2105
  # and close the port connection.
2042
- code[-1] = ");\n"
2106
+ codeC[-1] = ");\n"
2043
2107
  end
2044
2108
 
2045
2109
 
2046
2110
 
2047
2111
  # translation of the connection part (assigen).
2048
2112
  self.each_connection do |connection|
2049
- code << "#{connection.to_verilog}\n"
2113
+ codeC << "#{connection.to_verilog}\n"
2050
2114
  end
2051
2115
 
2052
2116
  # Translation of behavior part (always).
@@ -2054,43 +2118,48 @@ module HDLRuby::Low
2054
2118
  if behavior.block.is_a?(TimeBlock) then
2055
2119
  # Extract and translate the TimeRepeat separately.
2056
2120
  behavior.each_block_deep do |blk|
2057
- code << blk.repeat_to_verilog!
2121
+ codeC << blk.repeat_to_verilog!
2058
2122
  end
2059
2123
  # And generate an initial block.
2060
- code << " initial "
2124
+ codeC << " initial "
2061
2125
  else
2062
2126
  # Generate a standard process.
2063
- code << " always @( "
2127
+ codeC << " always @( "
2064
2128
  # If there is no "always" condition, it is always @("*").
2065
2129
  if behavior.each_event.to_a.empty? then
2066
- code << "*"
2130
+ codeC << "*"
2067
2131
  else
2068
2132
  event = behavior.each_event.to_a
2069
2133
  event[0..-2].each do |event|
2070
2134
  # If "posedge" or "negedge" does not exist, the variable is set to condition.
2071
2135
  if (event.type.to_s != "posedge" && event.type.to_s != "negedge") then
2072
- code << "#{event.ref.to_verilog}, "
2136
+ codeC << "#{event.ref.to_verilog}, "
2073
2137
  else
2074
2138
  # Otherwise, it outputs "psoedge" or "negedge" as a condition.
2075
- code << "#{event.type.to_s} #{event.ref.to_verilog}, "
2139
+ codeC << "#{event.type.to_s} #{event.ref.to_verilog}, "
2076
2140
  end
2077
2141
  end
2078
2142
  # Since no comma is necessary at the end, we try not to separate commas separately at the end.
2079
2143
  if (event.last.type.to_s != "posedge" && event.last.type.to_s != "negedge") then
2080
- code << "#{event.last.ref.to_verilog}"
2144
+ codeC << "#{event.last.ref.to_verilog}"
2081
2145
  else
2082
- code << "#{event.last.type.to_s} #{event.last.ref.to_verilog}"
2146
+ codeC << "#{event.last.type.to_s} #{event.last.ref.to_verilog}"
2083
2147
  end
2084
2148
  end
2085
- code << " ) "
2149
+ codeC << " ) "
2086
2150
  end
2087
2151
 
2088
- code << behavior.block.to_verilog
2152
+ codeC << behavior.block.to_verilog
2089
2153
 
2090
2154
  end
2091
2155
 
2092
2156
  # Conclusion.
2093
- code << "\nendmodule"
2157
+ codeC << "\nendmodule"
2158
+
2159
+ # Adds the truncing functions.
2160
+ code << TruncersI.dump
2161
+ # Adds the content code.
2162
+ code << codeC
2094
2163
  return code
2095
2164
  end
2096
2165
  end