HDLRuby 2.4.8 → 2.4.14

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Files changed (11) hide show
  1. checksums.yaml +4 -4
  2. data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb +25 -0
  3. data/lib/HDLRuby/hdr_samples/mei8_bench.rb +1 -1
  4. data/lib/HDLRuby/hdr_samples/with_connector.rb +207 -0
  5. data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +12 -0
  6. data/lib/HDLRuby/hdr_samples/with_memory_rom.rb +53 -0
  7. data/lib/HDLRuby/hdr_samples/with_multi_channels.rb +127 -112
  8. data/lib/HDLRuby/std/connector.rb +42 -0
  9. data/lib/HDLRuby/std/memory.rb +175 -29
  10. data/lib/HDLRuby/version.rb +1 -1
  11. metadata +6 -2
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data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb ADDED
@@ -0,0 +1,25 @@
1
+ #!/usr/bin/ruby
2
+ # Script for generating the vcd files.
3
+
4
+ # The configuration scenarii
5
+ $scenarii = [
6
+ [:_clk2_clk2, :register], # 0
7
+ [:_clk2_nclk2, :register], # 1
8
+ [:_clk2_clk3, :register], # 2
9
+ [:_clk3_clk2, :register], # 3
10
+ [:_clk2_clk2, :handshake], # 4
11
+ [:_clk2_nclk2, :handshake], # 5
12
+ [:_clk2_clk3, :handshake], # 6
13
+ [:_clk3_clk2, :handshake], # 7
14
+ [:clk2_clk2_clk2, :queue], # 8
15
+ [:clk2_clk2_nclk2, :queue], # 9
16
+ [:clk1_clk2_clk3, :queue], # 10
17
+ [:clk3_clk2_clk1, :queue], # 11
18
+ [:clk2_clk3_clk1, :queue], # 12
19
+ [:clk2_clk1_clk3, :queue], # 13
20
+ ]
21
+ $scenarii.each_with_index do |scenarii,i|
22
+ puts "scenario: [#{i}] #{scenarii}"
23
+ `bundle exec ../hdrcc.rb -S --vcd with_multi_channels.rb WithMultiChannelPaper #{i}`
24
+ `mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{scenarii[0]}_#{scenarii[1]}.vcd`
25
+ end
data/lib/HDLRuby/hdr_samples/mei8_bench.rb CHANGED
@@ -5,7 +5,7 @@ include HDLRuby::High::Std
5
5
  # A simple implementation of the MEI8 processor.
6
6
  #
7
7
  # In this implementation, the program is hard-coded in an internal ROM
8
- system :mei8 do |prog_file = "./prog_encrypt.obj"|
8
+ system :mei8 do |prog_file = "./prog.obj"|
9
9
  # Clock and reset.
10
10
  input :clk, :rst
11
11
  # Bus.
data/lib/HDLRuby/hdr_samples/with_connector.rb ADDED
@@ -0,0 +1,207 @@
1
+ require 'std/channel.rb'
2
+ require 'std/connector.rb'
3
+
4
+ include HDLRuby::High::Std
5
+
6
+ # Sample for testing the connectors of channels.
7
+
8
+ # Channel describing a buffered queue storing data of +typ+ type of +depth+,
9
+ # synchronized through clk and reset on +rst+.
10
+ channel(:queue) do |typ,depth,clk,rst|
11
+ # The inner buffer of the queue.
12
+ typ[-depth].inner :buffer
13
+ # The read and write pointers.
14
+ [depth.width].inner :rptr, :wptr
15
+ # The read and write command signals.
16
+ inner :rreq, :wreq
17
+ # The read and write ack signals.
18
+ inner :rack, :wack
19
+ # The read/write data registers.
20
+ typ.inner :rdata, :wdata
21
+
22
+ # The flags telling of the channel is synchronized
23
+ inner :rsync, :wsync
24
+
25
+ # The process handling the decoupled access to the buffer.
26
+ par(clk.posedge) do
27
+ hif(rst) { rptr <= 0; wptr <= 0 }
28
+ helse do
29
+ hif(~rsync) do
30
+ hif (~rreq) { rack <= 0 }
31
+ hif(rreq & (~rack) & (rptr != wptr)) do
32
+ rdata <= buffer[rptr]
33
+ rptr <= (rptr + 1) % depth
34
+ rack <= 1
35
+ end
36
+ end
37
+
38
+ hif(~wsync) do
39
+ hif (~wreq) { wack <= 0 }
40
+ hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
41
+ buffer[wptr] <= wdata
42
+ wptr <= (wptr + 1) % depth
43
+ wack <= 1
44
+ end
45
+ end
46
+ end
47
+ end
48
+
49
+ reader_output :rreq, :rptr, :rsync
50
+ reader_input :rdata, :rack, :wptr, :buffer
51
+
52
+ # The read primitive.
53
+ reader do |blk,target|
54
+ if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
55
+ # Same clk event, synchrone case: perform a direct access.
56
+ # Now perform the access.
57
+ top_block.unshift do
58
+ rsync <= 1
59
+ rreq <= 0
60
+ end
61
+ seq do
62
+ hif(rptr != wptr) do
63
+ # target <= rdata
64
+ target <= buffer[rptr]
65
+ rptr <= (rptr + 1) % depth
66
+ blk.call if blk
67
+ end
68
+ end
69
+ else
70
+ # Different clk event, perform a decoupled access.
71
+ top_block.unshift do
72
+ rsync <= 0
73
+ rreq <= 0
74
+ end
75
+ par do
76
+ hif (~rack) { rreq <= 1 }
77
+ helsif(rreq) do
78
+ rreq <= 0
79
+ target <= rdata
80
+ blk.call if blk
81
+ end
82
+ end
83
+ end
84
+ end
85
+
86
+ writer_output :wreq, :wdata, :wptr, :wsync, :buffer
87
+ writer_input :wack, :rptr
88
+
89
+ # The write primitive.
90
+ writer do |blk,target|
91
+ if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
92
+ # Same clk event, synchrone case: perform a direct access.
93
+ top_block.unshift do
94
+ wsync <= 1
95
+ wreq <= 0
96
+ end
97
+ hif(((wptr+1) % depth) != rptr) do
98
+ buffer[wptr] <= target
99
+ wptr <= (wptr + 1) % depth
100
+ blk.call if blk
101
+ end
102
+ else
103
+ # Different clk event, asynchrone case: perform a decoupled access.
104
+ top_block.unshift do
105
+ wsync <= 0
106
+ wreq <= 0
107
+ end
108
+ seq do
109
+ hif (~wack) do
110
+ wreq <= 1
111
+ wdata <= target
112
+ end
113
+ helsif(wreq) do
114
+ wreq <= 0
115
+ blk.call if blk
116
+ end
117
+ end
118
+ end
119
+ end
120
+ end
121
+
122
+
123
+
124
+
125
+ # Module for testing the connector.
126
+ system :with_connectors do
127
+ inner :clk, :rst
128
+ [4].inner :counter, :res_0,:res_1,:res_2,:res_3
129
+ inner :ack_in, :ack_out
130
+
131
+ # The input queue.
132
+ queue(bit[4],4,clk,rst).(:in_qu)
133
+
134
+ # The first output queue.
135
+ queue(bit[4],4,clk,rst).(:out_qu0)
136
+ queue(bit[4],4,clk,rst).(:out_qu1)
137
+ queue(bit[4],4,clk,rst).(:out_qu2)
138
+ queue(bit[4],4,clk,rst).(:out_qu3)
139
+
140
+ # Connect them
141
+ duplicator([4],clk.negedge,in_qu,[out_qu0,out_qu1,out_qu2,out_qu3])
142
+
143
+ # # Slow version, always work
144
+ # par(clk.posedge) do
145
+ # ack_in <= 0
146
+ # ack_out <= 1
147
+ # hif(rst) { counter <= 0 }
148
+ # helse do
149
+ # hif(ack_out) do
150
+ # ack_out <= 0
151
+ # in_qu.write(counter) do
152
+ # ack_in <= 1
153
+ # counter <= counter + 1
154
+ # end
155
+ # end
156
+ # hif(ack_in) do
157
+ # out_qu0.read(res_0)
158
+ # out_qu1.read(res_1)
159
+ # out_qu2.read(res_2)
160
+ # out_qu3.read(res_3) { ack_out <= 1 }
161
+ # end
162
+ # end
163
+ # end
164
+
165
+ # Fast version but assumes connected channels are blocking
166
+ par(clk.posedge) do
167
+ ack_in <= 0
168
+ hif(rst) { counter <= 0 }
169
+ helse do
170
+ in_qu.write(counter) do
171
+ ack_in <= 1
172
+ counter <= counter + 1
173
+ end
174
+ hif(ack_in) do
175
+ out_qu0.read(res_0)
176
+ out_qu1.read(res_1)
177
+ out_qu2.read(res_2)
178
+ out_qu3.read(res_3)
179
+ end
180
+ end
181
+ end
182
+
183
+ timed do
184
+ clk <= 0
185
+ rst <= 0
186
+ !10.ns
187
+ clk <= 1
188
+ !10.ns
189
+ clk <= 0
190
+ rst <= 1
191
+ !10.ns
192
+ clk <= 1
193
+ !10.ns
194
+ clk <= 0
195
+ !10.ns
196
+ clk <= 1
197
+ !10.ns
198
+ clk <= 0
199
+ rst <= 0
200
+ 16.times do
201
+ !10.ns
202
+ clk <= 1
203
+ !10.ns
204
+ clk <= 0
205
+ end
206
+ end
207
+ end
data/lib/HDLRuby/hdr_samples/with_fixpoint.rb CHANGED
@@ -32,6 +32,18 @@ system :fix_test do
32
32
  !10.ns
33
33
  d <= d + c
34
34
  !10.ns
35
+ d <= d / c
36
+ !10.ns
37
+ d <= d / 3.to_fix(4)
38
+ !10.ns
39
+ d <= 1.to_fix(4) - d
40
+ !10.ns
41
+ d <= -d
42
+ !10.ns
43
+ d <= d * 3.to_fix(4)
44
+ !10.ns
45
+ d <= -d
46
+ !10.ns
35
47
  a <= -0.375.to_fix(4)
36
48
  b <= 1.625.to_fix(4)
37
49
  !10.ns
data/lib/HDLRuby/hdr_samples/with_memory_rom.rb ADDED
@@ -0,0 +1,53 @@
1
+ require 'std/memory.rb'
2
+
3
+ include HDLRuby::High::Std
4
+
5
+
6
+
7
+
8
+
9
+ # A system testing the rom channel.
10
+ system :rorm_test do
11
+ inner :clk,:rst
12
+ [8].inner :value
13
+ inner :addr
14
+
15
+ # Declares a 8-bit-data and 1 element rom address synchronous memory
16
+ # on negative edge of clk.
17
+ # mem_rom([8],2,clk,rst,[_00000110,_00000111], rinc: :rst).(:romI)
18
+ mem_rom([8],1,clk,rst,[_00000110], rinc: :rst).(:romI)
19
+ rd = romI.branch(:rinc)
20
+
21
+ par(clk.posedge) do
22
+ hif(rst) { addr <= 0 }
23
+ helse do
24
+ rd.read(value)
25
+ end
26
+ end
27
+
28
+ timed do
29
+ clk <= 0
30
+ rst <= 0
31
+ !10.ns
32
+ clk <= 1
33
+ !10.ns
34
+ clk <= 0
35
+ rst <= 1
36
+ !10.ns
37
+ clk <= 1
38
+ !10.ns
39
+ clk <= 0
40
+ !10.ns
41
+ clk <= 1
42
+ !10.ns
43
+ clk <= 0
44
+ rst <= 0
45
+ !10.ns
46
+ 10.times do
47
+ clk <= 1
48
+ !10.ns
49
+ clk <= 0
50
+ !10.ns
51
+ end
52
+ end
53
+ end
data/lib/HDLRuby/hdr_samples/with_multi_channels.rb CHANGED
@@ -10,36 +10,51 @@ channel(:queue) do |typ,depth,clk,rst|
10
10
  # The read and write pointers.
11
11
  [depth.width].inner :rptr, :wptr
12
12
  # The read and write command signals.
13
- inner :rcmd, :wcmd
13
+ inner :rreq, :wreq
14
14
  # The read and write ack signals.
15
15
  inner :rack, :wack
16
- # The ack check deactivator (for synchron accesses).
17
- inner :hrack, :hwack
18
16
  # The read/write data registers.
19
17
  typ.inner :rdata, :wdata
20
18
 
19
+ # The flags telling of the channel is synchronized
20
+ inner :rsync, :wsync
21
+
21
22
  # The process handling the decoupled access to the buffer.
22
23
  par(clk.posedge) do
23
- # rack <= 0
24
- # wack <= 0
25
- hif (~rcmd) { rack <= 0 }
26
- hif (~wcmd) { wack <= 0 }
27
24
  hif(rst) { rptr <= 0; wptr <= 0 }
28
- hif(rcmd & (hrack|~rack) & (rptr != wptr)) do
29
- rptr <= (rptr + 1) % depth
30
- rack <= 1
31
- end
32
- hif(wcmd & (hwack|~wack) & (((wptr+1) % depth) != rptr)) do
33
- buffer[wptr] <= wdata
34
- # buffer[1] <= wdata
35
- wptr <= (wptr + 1) % depth
36
- wack <= 1
25
+ helse do
26
+ # hif(rsync) do
27
+ # hif(rptr != wptr) do
28
+ # rdata <= buffer[rptr]
29
+ # end
30
+ # end
31
+ # helse do
32
+ hif(~rsync) do
33
+ hif (~rreq) { rack <= 0 }
34
+ hif(rreq & (~rack) & (rptr != wptr)) do
35
+ rdata <= buffer[rptr]
36
+ rptr <= (rptr + 1) % depth
37
+ rack <= 1
38
+ end
39
+ end
40
+
41
+ # hif(wsync) do
42
+ # buffer[wptr] <= wdata
43
+ # end
44
+ # helse do
45
+ hif(~wsync) do
46
+ hif (~wreq) { wack <= 0 }
47
+ hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
48
+ buffer[wptr] <= wdata
49
+ wptr <= (wptr + 1) % depth
50
+ wack <= 1
51
+ end
52
+ end
37
53
  end
38
54
  end
39
- par { rdata <= buffer[rptr] }
40
55
 
41
- reader_output :rcmd, :rptr, :hrack
42
- reader_input :rdata, :rack
56
+ reader_output :rreq, :rptr, :rsync
57
+ reader_input :rdata, :rack, :wptr, :buffer
43
58
 
44
59
  # The read primitive.
45
60
  reader do |blk,target|
@@ -47,58 +62,66 @@ channel(:queue) do |typ,depth,clk,rst|
47
62
  # Same clk event, synchrone case: perform a direct access.
48
63
  # Now perform the access.
49
64
  top_block.unshift do
50
- rcmd <= 0
51
- hrack <= 1
65
+ rsync <= 1
66
+ rreq <= 0
52
67
  end
53
68
  seq do
54
- rptr <= (rptr + 1) % depth
55
- target <= rdata
56
- blk.call if blk
69
+ hif(rptr != wptr) do
70
+ # target <= rdata
71
+ target <= buffer[rptr]
72
+ rptr <= (rptr + 1) % depth
73
+ blk.call if blk
74
+ end
57
75
  end
58
76
  else
59
77
  # Different clk event, perform a decoupled access.
60
78
  top_block.unshift do
61
- rcmd <= 0
62
- hrack <= 0
79
+ rsync <= 0
80
+ rreq <= 0
63
81
  end
64
- seq do
65
- hif(rack) do
66
- blk.call if blk
67
- end
68
- helse do
69
- rcmd <= 1
82
+ par do
83
+ hif (~rack) { rreq <= 1 }
84
+ helsif(rreq) do
85
+ rreq <= 0
70
86
  target <= rdata
87
+ blk.call if blk
71
88
  end
72
89
  end
73
90
  end
74
91
  end
75
92
 
76
- writer_output :wcmd, :wdata, :hwack
77
- writer_input :wack
93
+ writer_output :wreq, :wdata, :wptr, :wsync, :buffer
94
+ writer_input :wack, :rptr
78
95
 
79
96
  # The write primitive.
80
97
  writer do |blk,target|
81
98
  if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
82
99
  # Same clk event, synchrone case: perform a direct access.
83
100
  top_block.unshift do
84
- wcmd <= 0
85
- hwack <= 1
101
+ wsync <= 1
102
+ wreq <= 0
103
+ end
104
+ hif(((wptr+1) % depth) != rptr) do
105
+ # wdata <= target
106
+ buffer[wptr] <= target
107
+ wptr <= (wptr + 1) % depth
108
+ blk.call if blk
86
109
  end
87
- wcmd <= 1
88
- wdata <= target
89
- blk.call if blk
90
110
  else
91
111
  # Different clk event, asynchrone case: perform a decoupled access.
92
112
  top_block.unshift do
93
- wcmd <= 0
94
- hwack <= 0
113
+ wsync <= 0
114
+ wreq <= 0
95
115
  end
96
116
  seq do
97
- hif(wack) do
117
+ hif (~wack) do
118
+ wreq <= 1
119
+ wdata <= target
120
+ end
121
+ helsif(wreq) do
122
+ wreq <= 0
98
123
  blk.call if blk
99
124
  end
100
- helse { wcmd <= 1 }
101
- wdata <= target
102
125
  end
103
126
  end
104
127
  end
@@ -135,7 +158,7 @@ channel(:handshake) do |typ|
135
158
  # The data signal.
136
159
  typ.inner :data
137
160
  # The request and acknowledge.
138
- typ.inner :req, :ack
161
+ inner :req, :ack
139
162
 
140
163
  reader_input :ack, :data
141
164
  reader_output :req
@@ -174,110 +197,102 @@ channel(:handshake) do |typ|
174
197
  end
175
198
 
176
199
 
177
- # $mode = :sync
178
- # $mode = :nsync
179
- # $mode = :async
180
- # $mode = :proco # Producter / Consummer
200
+ # $mode: channel clock, producer clock, consumer clock (n: not clock)
181
201
  # $channel = :register
182
202
  # $channel = :handshake
183
203
  # $channel = :queue
184
204
 
185
205
  # The configuration scenarii
186
- $scenarii = [ [:sync, :register], [:sync, :handshake], [:sync, :queue],
187
- [:nsync, :register], [:nsync, :handshake], [:nsync, :queue],
188
- [:async, :register], [:async, :handshake], [:async, :queue],
189
- [:proco, :register], [:proco, :handshake], [:proco, :queue] ]
206
+ $scenarii = [
207
+ [:_clk2_clk2, :register], # 0
208
+ [:_clk2_nclk2, :register], # 1
209
+ [:_clk2_clk3, :register], # 2
210
+ [:_clk3_clk2, :register], # 3
211
+ [:_clk2_clk2, :handshake], # 4
212
+ [:_clk2_nclk2, :handshake], # 5
213
+ [:_clk2_clk3, :handshake], # 6
214
+ [:_clk3_clk2, :handshake], # 7
215
+ [:clk2_clk2_clk2, :queue], # 8
216
+ [:clk2_clk2_nclk2, :queue], # 9
217
+ [:clk1_clk2_clk3, :queue], # 10
218
+ [:clk3_clk2_clk1, :queue], # 11
219
+ [:clk2_clk3_clk1, :queue], # 12
220
+ [:clk2_clk1_clk3, :queue], # 13
221
+ ]
190
222
 
191
223
  # The configuration
192
- $mode, $channel = $scenarii[11]
224
+ # $mode, $channel = $scenarii[11]
225
+ $mode, $channel = $scenarii[ARGV[-1].to_i]
226
+ puts "scenario: #{$scenarii[ARGV[-1].to_i]}"
193
227
 
194
228
  # Testing the queue channel.
195
229
  system :test_queue do
196
- inner :clk, :rst, :clk2, :clk3
197
- [8].inner :idata, :odata
230
+ inner :rst, :clk1, :clk2, :clk3
231
+ [8].inner :idata, :odata, :odata2
198
232
  [4].inner :counter
199
233
 
234
+
235
+ # Assign the clocks
236
+ mode = $mode.to_s.split("_")
237
+ if ($channel == :queue) then
238
+ clk_que = send(mode[0])
239
+ end
240
+ ev_pro = mode[1][0] == "n" ?
241
+ send(mode[1][1..-1]).negedge : send(mode[1]).posedge
242
+ ev_con = mode[2][0] == "n" ?
243
+ send(mode[2][1..-1]).negedge : send(mode[2]).posedge
244
+
245
+ # Set up the channel
200
246
  if $channel == :register then
201
247
  register(bit[8]).(:my_ch)
202
248
  elsif $channel == :handshake then
203
249
  handshake(bit[8],rst).(:my_ch)
204
250
  elsif $channel == :queue then
205
- queue(bit[8],5,clk,rst).(:my_ch)
251
+ queue(bit[8],3,clk_que,rst).(:my_ch)
206
252
  end
207
253
 
208
- ev = $mode == :sync ? clk.posedge :
209
- $mode == :nsync ? clk.negedge : clk2.posedge
210
-
211
- if $mode != :proco then
212
- # Sync/Neg sync and async tests mode
213
- par(ev) do
214
- hif(rst) do
215
- counter <= 0
216
- idata <= 0
217
- odata <= 0
218
- end
219
- helse do
220
- hif (counter < 4) do
221
- my_ch.write(idata) do
222
- idata <= idata + 1
223
- counter <= counter + 1
224
- end
225
- end
226
- helsif ((counter > 10) & (counter < 15)) do
227
- my_ch.read(odata) do
228
- idata <= idata - odata
229
- counter <= counter + 1
230
- end
231
- end
232
- helse do
233
- counter <= counter + 1
234
- end
235
- end
254
+ # Producter/consumer mode
255
+ # Producer
256
+ par(ev_pro) do
257
+ hif(rst) do
258
+ idata <= 0
236
259
  end
237
- else
238
- # Producter/consumer mode
239
- # Producer
240
- par(clk2.posedge) do
241
- hif(rst) do
242
- idata <= 0
243
- end
244
- helse do
245
- my_ch.write(idata) do
246
- idata <= idata + 1
247
- end
260
+ helse do
261
+ my_ch.write(idata) do
262
+ idata <= idata + 1
248
263
  end
249
264
  end
250
- # Consumer
251
- par(clk3.posedge) do
252
- hif(rst) do
253
- counter <= 0
254
- end
255
- helse do
256
- my_ch.read(odata) do
257
- counter <= counter + 1
258
- end
265
+ end
266
+ # Consumer
267
+ par(ev_con) do
268
+ hif(rst) do
269
+ counter <= 0
270
+ end
271
+ helse do
272
+ my_ch.read(odata) do
273
+ counter <= counter + 1
259
274
  end
260
275
  end
261
276
  end
262
277
 
263
278
  timed do
264
- clk <= 0
279
+ clk1 <= 0
265
280
  clk2 <= 0
266
281
  clk3 <= 0
267
282
  rst <= 0
268
283
  !10.ns
269
- clk <= 1
284
+ clk1 <= 1
270
285
  !10.ns
271
- clk <= 0
286
+ clk1 <= 0
272
287
  rst <= 1
273
288
  !3.ns
274
289
  clk2 <= 1
275
290
  !3.ns
276
291
  clk3 <= 0
277
292
  !4.ns
278
- clk <= 1
293
+ clk1 <= 1
279
294
  !10.ns
280
- clk <= 0
295
+ clk1 <= 0
281
296
  !3.ns
282
297
  clk2 <= 0
283
298
  !3.ns
@@ -286,9 +301,9 @@ system :test_queue do
286
301
  rst <= 0
287
302
  !2.ns
288
303
  64.times do
289
- clk <= 1
304
+ clk1 <= 1
290
305
  !10.ns
291
- clk <= 0
306
+ clk1 <= 0
292
307
  !3.ns
293
308
  clk2 <= ~clk2
294
309
  !3.ns
data/lib/HDLRuby/std/connector.rb ADDED
@@ -0,0 +1,42 @@
1
+ module HDLRuby::High::Std
2
+
3
+ ##
4
+ # Standard HDLRuby::High library: connectors between channels
5
+ #
6
+ ########################################################################
7
+
8
+ # Function for generating a connector that duplicates the output of
9
+ # channel +inch+ and connect it to channels +outchs+ with data of
10
+ # +typ+.
11
+ # The duplication is done according to event +ev+.
12
+ function :duplicator do |typ, ev, inch, outchs|
13
+ ev = ev.poswedge unless ev.is_a?(Event)
14
+ inner :in_ack, :in_req
15
+ out_chacks = outchs.map.with_index do |ch,i|
16
+ [ ch, inner(:"out_ack#{i}") ]
17
+ end
18
+ typ.inner :data
19
+ par(ev) do
20
+ in_req <= 1
21
+ out_chacks.each { |ch,ack| ack <= 0 }
22
+ out_chacks.each do |ch,ack|
23
+ hif(ack == 1) { in_req <= 0 }
24
+ end
25
+ hif(in_req) do
26
+ in_ack <= 0
27
+ inch.read(data) { in_ack <= 1 }
28
+ end
29
+ hif(in_ack) do
30
+ out_chacks.each do |ch,ack|
31
+ hif(ack == 0) { ch.write(data) { ack <= 1 } }
32
+ end
33
+ hif (out_chacks.reduce(_1) { |sum,(ch,ack)| ack & sum }) do
34
+ out_chacks.each { |ch,ack| ack <= 0 }
35
+ end
36
+ end
37
+ end
38
+ end
39
+
40
+
41
+
42
+ end
data/lib/HDLRuby/std/memory.rb CHANGED
@@ -34,6 +34,7 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
34
34
  size = size.to_i
35
35
  # Compute the address bus width from the size.
36
36
  awidth = (size-1).width
37
+ awidth = 1 if awidth == 0
37
38
  # Ensure clk_e is an event, if not set it to a positive edge.
38
39
  clk_e = clk_e.posedge unless clk_e.is_a?(Event)
39
40
 
@@ -209,6 +210,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
209
210
  size = size.to_i
210
211
  # Compute the address bus width from the size.
211
212
  awidth = (size-1).width
213
+ awidth = 1 if awidth == 0
212
214
  # Process the table of reset mapping for the branches.
213
215
  # Ensures br_srts is a hash.
214
216
  br_rsts = br_rsts.to_hash
@@ -292,17 +294,43 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
292
294
  trig_r <= 0
293
295
  end
294
296
  # The read procedure.
297
+ # par do
298
+ # hif(rst == 0) do
299
+ # # No reset, so can perform the read.
300
+ # hif(trig_r == 1) do
301
+ # # The trigger was previously set, read ok.
302
+ # target <= dbus_r
303
+ # blk.call if blk
304
+ # end
305
+ # # Prepare the read.
306
+ # abus_r <= abus_r + 1
307
+ # trig_r <= 1
308
+ # end
309
+ # end
310
+ # The read procedure.
295
311
  par do
296
312
  hif(rst == 0) do
297
313
  # No reset, so can perform the read.
298
314
  hif(trig_r == 1) do
299
315
  # The trigger was previously set, read ok.
300
- target <= dbus_r
301
- blk.call if blk
316
+ # target <= dbus_r
317
+ # blk.call if blk
318
+ seq do
319
+ # abus_r <= abus_r + 1
320
+ target <= dbus_r
321
+ blk.call if blk
322
+ end
323
+ end
324
+ helse do
325
+ # Prepare the read.
326
+ # abus_r <= abus_r + 1
327
+ if 2**size.width != size then
328
+ abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
329
+ else
330
+ abus_r <= abus_r + 1
331
+ end
332
+ trig_r <= 1
302
333
  end
303
- # Prepare the read.
304
- abus_r <= abus_r + 1
305
- trig_r <= 1
306
334
  end
307
335
  end
308
336
  end
@@ -331,18 +359,44 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
331
359
  # Reset so switch of the access trigger.
332
360
  trig_r <= 0
333
361
  end
362
+ # # The read procedure.
363
+ # par do
364
+ # hif(rst == 0) do
365
+ # # No reset, so can perform the read.
366
+ # hif(trig_r == 1) do
367
+ # # The trigger was previously set, read ok.
368
+ # target <= dbus_r
369
+ # blk.call if blk
370
+ # end
371
+ # # Prepare the read.
372
+ # abus_r <= abus_r - 1
373
+ # trig_r <= 1
374
+ # end
375
+ # end
334
376
  # The read procedure.
335
377
  par do
336
378
  hif(rst == 0) do
337
379
  # No reset, so can perform the read.
338
380
  hif(trig_r == 1) do
339
381
  # The trigger was previously set, read ok.
340
- target <= dbus_r
341
- blk.call if blk
382
+ # target <= dbus_r
383
+ # blk.call if blk
384
+ seq do
385
+ # abus_r <= abus_r - 1
386
+ target <= dbus_r
387
+ blk.call if blk
388
+ end
389
+ end
390
+ helse do
391
+ # Prepare the read.
392
+ # abus_r <= abus_r - 1
393
+ if 2**size.width != size then
394
+ abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
395
+ else
396
+ abus_r <= abus_r - 1
397
+ end
398
+ trig_r <= 1
342
399
  end
343
- # Prepare the read.
344
- abus_r <= abus_r - 1
345
- trig_r <= 1
346
400
  end
347
401
  end
348
402
  end
@@ -392,6 +446,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
392
446
  size = size.to_i
393
447
  # Compute the address bus width from the size.
394
448
  awidth = (size-1).width
449
+ awidth = 1 if awidth == 0
395
450
  # Process the table of reset mapping for the branches.
396
451
  # puts "first br_rsts=#{br_rsts}"
397
452
  # if br_rsts.is_a?(Array) then
@@ -551,7 +606,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
551
606
  end
552
607
  helse do
553
608
  # Prepare the read.
554
- abus_r <= abus_r + 1
609
+ # abus_r <= abus_r + 1
610
+ if 2**size.width != size then
611
+ abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
612
+ else
613
+ abus_r <= abus_r + 1
614
+ end
555
615
  trig_r <= 1
556
616
  end
557
617
  end
@@ -588,7 +648,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
588
648
  # No reset, so can perform the write.
589
649
  blk.call if blk
590
650
  # Prepare the write.
591
- abus_w <= abus_w + 1
651
+ # abus_w <= abus_w + 1
652
+ if 2**size.width != size then
653
+ abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
654
+ else
655
+ abus_w <= abus_w + 1
656
+ end
592
657
  trig_w <= 1
593
658
  dbus_w <= target
594
659
  end
@@ -620,18 +685,44 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
620
685
  # Reset so switch of the access trigger.
621
686
  trig_r <= 0
622
687
  end
688
+ # # The read procedure.
689
+ # par do
690
+ # hif(rst == 0) do
691
+ # # No reset, so can perform the read.
692
+ # hif(trig_r == 1) do
693
+ # # The trigger was previously set, read ok.
694
+ # target <= dbus_r
695
+ # blk.call if blk
696
+ # end
697
+ # # Prepare the read.
698
+ # abus_r <= abus_r - 1
699
+ # trig_r <= 1
700
+ # end
701
+ # end
623
702
  # The read procedure.
624
703
  par do
625
704
  hif(rst == 0) do
626
705
  # No reset, so can perform the read.
627
706
  hif(trig_r == 1) do
628
707
  # The trigger was previously set, read ok.
629
- target <= dbus_r
630
- blk.call if blk
708
+ # target <= dbus_r
709
+ # blk.call if blk
710
+ seq do
711
+ # abus_r <= abus_r - 1
712
+ target <= dbus_r
713
+ blk.call if blk
714
+ end
715
+ end
716
+ helse do
717
+ # Prepare the read.
718
+ # abus_r <= abus_r - 1
719
+ if 2**size.width != size then
720
+ abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
721
+ else
722
+ abus_r <= abus_r - 1
723
+ end
724
+ trig_r <= 1
631
725
  end
632
- # Prepare the read.
633
- abus_r <= abus_r - 1
634
- trig_r <= 1
635
726
  end
636
727
  end
637
728
  end
@@ -666,7 +757,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
666
757
  # No reset, so can perform the write.
667
758
  blk.call if blk
668
759
  # Prepare the write.
669
- abus_w <= abus_w - 1
760
+ # abus_w <= abus_w - 1
761
+ if 2**size.width != size then
762
+ abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
763
+ else
764
+ abus_w <= abus_w - 1
765
+ end
670
766
  trig_w <= 1
671
767
  dbus_w <= target
672
768
  end
@@ -860,7 +956,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
860
956
  reader_input rst_name
861
957
  end
862
958
  # Declares the address counter.
863
- [size.width-1].inner :abus_r
959
+ awidth = (size-1).width
960
+ awidth = 1 if awidth == 0
961
+ [awidth].inner :abus_r
864
962
  reader_inout :abus_r
865
963
 
866
964
  # Defines the read procedure at address +addr+
@@ -883,7 +981,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
883
981
  end
884
982
  blk.call if blk
885
983
  # Prepare the next read.
886
- abus_r <= abus_r + 1
984
+ # abus_r <= abus_r + 1
985
+ if 2**size.width != size then
986
+ abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
987
+ else
988
+ abus_r <= abus_r + 1
989
+ end
887
990
  end
888
991
  end
889
992
  end
@@ -899,7 +1002,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
899
1002
  writer_input rst_name
900
1003
  end
901
1004
  # Declares the address counter.
902
- [size.width-1].inner :abus_w
1005
+ awidth = (size-1).width
1006
+ awidth = 1 if awidth == 0
1007
+ [awidth].inner :abus_w
903
1008
  writer_inout :abus_w
904
1009
 
905
1010
  # Defines the write procedure at address +addr+
@@ -922,7 +1027,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
922
1027
  end
923
1028
  blk.call if blk
924
1029
  # Prepare the next write.
925
- abus_w <= abus_w + 1
1030
+ # abus_w <= abus_w + 1
1031
+ if 2**size.width != size then
1032
+ abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
1033
+ else
1034
+ abus_w <= abus_w + 1
1035
+ end
926
1036
  end
927
1037
  end
928
1038
  end
@@ -940,7 +1050,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
940
1050
  reader_input rst_name
941
1051
  end
942
1052
  # Declares the address counter.
943
- [size.width-1].inner :abus_r
1053
+ awidth = (size-1).width
1054
+ awidth = 1 if awidth == 0
1055
+ [awidth].inner :abus_r
944
1056
  reader_inout :abus_r
945
1057
 
946
1058
  # Defines the read procedure at address +addr+
@@ -963,7 +1075,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
963
1075
  end
964
1076
  blk.call if blk
965
1077
  # Prepare the next read.
966
- abus_r <= abus_r - 1
1078
+ # abus_r <= abus_r - 1
1079
+ if 2**size.width != size then
1080
+ abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
1081
+ else
1082
+ abus_r <= abus_r - 1
1083
+ end
967
1084
  end
968
1085
  end
969
1086
  end
@@ -979,7 +1096,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
979
1096
  reader_input rst_name
980
1097
  end
981
1098
  # Declares the address counter.
982
- [size.width-1].inner :abus_w
1099
+ awidth = (size-1).width
1100
+ awidth = 1 if awidth == 0
1101
+ [awidth].inner :abus_w
983
1102
  reader_inout :abus_w
984
1103
 
985
1104
  # Defines the write procedure at address +addr+
@@ -1002,7 +1121,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
1002
1121
  end
1003
1122
  blk.call if blk
1004
1123
  # Prepare the next write.
1005
- abus_w <= abus_w - 1
1124
+ # abus_w <= abus_w - 1
1125
+ if 2**size.width != size then
1126
+ abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
1127
+ else
1128
+ abus_w <= abus_w - 1
1129
+ end
1006
1130
  end
1007
1131
  end
1008
1132
  end
@@ -1050,7 +1174,9 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1050
1174
  size = size.to_i
1051
1175
  # Compute the address bus width from the size.
1052
1176
  awidth = (size*nbanks-1).width
1177
+ awidth = 1 if awidth == 0
1053
1178
  awidth_b = (size-1).width # Bank width
1179
+ awidth_b = 1 if awidth_b == 0
1054
1180
  # Ensures br_srts is a hash.
1055
1181
  br_rsts = br_rsts.to_hash
1056
1182
 
@@ -1211,7 +1337,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1211
1337
  blk.call if blk
1212
1338
  end
1213
1339
  # Prepare the read.
1214
- abus_r <= abus_r + 1
1340
+ # abus_r <= abus_r + 1
1341
+ if 2**size.width != size then
1342
+ abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
1343
+ else
1344
+ abus_r <= abus_r + 1
1345
+ end
1215
1346
  trig_r <= 1
1216
1347
  end
1217
1348
  end
@@ -1247,7 +1378,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1247
1378
  # No reset, so can perform the write.
1248
1379
  blk.call if blk
1249
1380
  # Prepare the write.
1250
- abus_w <= abus_w + 1
1381
+ # abus_w <= abus_w + 1
1382
+ if 2**size.width != size then
1383
+ abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
1384
+ else
1385
+ abus_w <= abus_w + 1
1386
+ end
1251
1387
  trig_w <= 1
1252
1388
  dbus_w <= target
1253
1389
  end
@@ -1288,7 +1424,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1288
1424
  blk.call if blk
1289
1425
  end
1290
1426
  # Prepare the read.
1291
- abus_r <= abus_r - 1
1427
+ # abus_r <= abus_r - 1
1428
+ if 2**size.width != size then
1429
+ abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
1430
+ else
1431
+ abus_r <= abus_r - 1
1432
+ end
1292
1433
  trig_r <= 1
1293
1434
  end
1294
1435
  end
@@ -1325,6 +1466,11 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1325
1466
  blk.call if blk
1326
1467
  # Prepare the write.
1327
1468
  abus_w <= abus_w - 1
1469
+ if 2**size.width != size then
1470
+ abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
1471
+ else
1472
+ abus_w <= abus_w - 1
1473
+ end
1328
1474
  trig_w <= 1
1329
1475
  dbus_w <= target
1330
1476
  end
data/lib/HDLRuby/version.rb CHANGED
@@ -1,3 +1,3 @@
1
1
  module HDLRuby
2
- VERSION = "2.4.8"
2
+ VERSION = "2.4.14"
3
3
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: HDLRuby
3
3
  version: !ruby/object:Gem::Version
4
- version: 2.4.8
4
+ version: 2.4.14
5
5
  platform: ruby
6
6
  authors:
7
7
  - Lovic Gauthier
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2020-10-11 00:00:00.000000000 Z
11
+ date: 2020-11-16 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler
@@ -84,6 +84,7 @@ files:
84
84
  - lib/HDLRuby/hdr_samples/include.rb
85
85
  - lib/HDLRuby/hdr_samples/instance_open.rb
86
86
  - lib/HDLRuby/hdr_samples/linear_test.rb
87
+ - lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb
87
88
  - lib/HDLRuby/hdr_samples/mei8.rb
88
89
  - lib/HDLRuby/hdr_samples/mei8_bench.rb
89
90
  - lib/HDLRuby/hdr_samples/memory_test.rb
@@ -119,12 +120,14 @@ files:
119
120
  - lib/HDLRuby/hdr_samples/tuple.rb
120
121
  - lib/HDLRuby/hdr_samples/with_channel.rb
121
122
  - lib/HDLRuby/hdr_samples/with_class.rb
123
+ - lib/HDLRuby/hdr_samples/with_connector.rb
122
124
  - lib/HDLRuby/hdr_samples/with_decoder.rb
123
125
  - lib/HDLRuby/hdr_samples/with_fixpoint.rb
124
126
  - lib/HDLRuby/hdr_samples/with_fsm.rb
125
127
  - lib/HDLRuby/hdr_samples/with_linear.rb
126
128
  - lib/HDLRuby/hdr_samples/with_loop.rb
127
129
  - lib/HDLRuby/hdr_samples/with_memory.rb
130
+ - lib/HDLRuby/hdr_samples/with_memory_rom.rb
128
131
  - lib/HDLRuby/hdr_samples/with_multi_channels.rb
129
132
  - lib/HDLRuby/hdr_samples/with_reconf.rb
130
133
  - lib/HDLRuby/hdrcc.rb
@@ -270,6 +273,7 @@ files:
270
273
  - lib/HDLRuby/sim/hruby_value_pool.c
271
274
  - lib/HDLRuby/std/channel.rb
272
275
  - lib/HDLRuby/std/clocks.rb
276
+ - lib/HDLRuby/std/connector.rb
273
277
  - lib/HDLRuby/std/counters.rb
274
278
  - lib/HDLRuby/std/decoder.rb
275
279
  - lib/HDLRuby/std/fixpoint.rb