HDLRuby 2.4.8 → 2.4.14

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 7d844be165420dfe1bd108956e57c726b8e630e39d332112627f560a48817f8e
-  data.tar.gz: ef9603d21b10f7d455ff74033b7df816712b0b48c73a2834a46241934db38e5a
+  metadata.gz: 624b9738e43e9de0207b36e50f26dfc0885d260f004cec10d4bf27c5dc9a3c33
+  data.tar.gz: 6599a6daacaf1699d39b14bcb51fe3c93367b57fb29e0dbac089d609b63673b5
 SHA512:
-  metadata.gz: aabff1989668735d6cee243a12d3e0c58fd62baebb76e3fccb700045e0ba793907deabea47afc5fed59d3af63ca063c1a0cb64603dd6e91da3b068dd2a9f9cc3
-  data.tar.gz: 9e5e8968fcec50f75f293e93048ca930e2525a10943f1c4976027010ac60c41a844ae0c3a1aa8f7e18b4ce3c5814fa3178420ee2c500a0ab62ee4a93627a88ff
+  metadata.gz: b134540ea1182bf20b0c38e771161b3882c3d27128c8343bf6a0cf487f1f0e631ff6491d6abf9df9e6e89a09e6005af6ceb95f24ce54e0043c2195872e875197
+  data.tar.gz: edc4a191153cf71fe399b2756a50fb2b447c4571e0596b740de4c138d7bcf1314bc243614eb66e0a18d65e5642d27ab72bae0f60753bf223dfaea1a71935d211

data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb

@@ -0,0 +1,25 @@
+#!/usr/bin/ruby
+# Script for generating the vcd files.
+
+# The configuration scenarii
+$scenarii = [
+              [:_clk2_clk2,      :register],    #  0
+              [:_clk2_nclk2,     :register],    #  1
+              [:_clk2_clk3,      :register],    #  2
+              [:_clk3_clk2,      :register],    #  3
+              [:_clk2_clk2,      :handshake],   #  4
+              [:_clk2_nclk2,     :handshake],   #  5
+              [:_clk2_clk3,      :handshake],   #  6
+              [:_clk3_clk2,      :handshake],   #  7
+              [:clk2_clk2_clk2,  :queue],       #  8
+              [:clk2_clk2_nclk2, :queue],       #  9
+              [:clk1_clk2_clk3,  :queue],       # 10
+              [:clk3_clk2_clk1,  :queue],       # 11
+              [:clk2_clk3_clk1,  :queue],       # 12
+              [:clk2_clk1_clk3,  :queue],       # 13
+            ]
+$scenarii.each_with_index do |scenarii,i|
+    puts "scenario: [#{i}] #{scenarii}"
+    `bundle exec ../hdrcc.rb -S --vcd with_multi_channels.rb WithMultiChannelPaper #{i}`
+    `mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{scenarii[0]}_#{scenarii[1]}.vcd`
+end

data/lib/HDLRuby/hdr_samples/mei8_bench.rb

@@ -5,7 +5,7 @@ include HDLRuby::High::Std
 # A simple implementation of the MEI8 processor.
 #
 # In this implementation, the program is hard-coded in an internal ROM
-system :mei8 do |prog_file = "./prog_encrypt.obj"|
+system :mei8 do |prog_file = "./prog.obj"|
     # Clock and reset.
     input :clk, :rst
     # Bus.

data/lib/HDLRuby/hdr_samples/with_connector.rb

@@ -0,0 +1,207 @@
+require 'std/channel.rb'
+require 'std/connector.rb'
+
+include HDLRuby::High::Std
+
+# Sample for testing the connectors of channels.
+
+# Channel describing a buffered queue storing data of +typ+ type of +depth+,
+# synchronized through clk and reset on +rst+.
+channel(:queue) do |typ,depth,clk,rst|
+    # The inner buffer of the queue.
+    typ[-depth].inner :buffer
+    # The read and write pointers.
+    [depth.width].inner :rptr, :wptr
+    # The read and write command signals.
+    inner :rreq, :wreq
+    # The read and write ack signals.
+    inner :rack, :wack
+    # The read/write data registers.
+    typ.inner :rdata, :wdata
+
+    # The flags telling of the channel is synchronized
+    inner :rsync, :wsync
+
+    # The process handling the decoupled access to the buffer.
+    par(clk.posedge) do
+        hif(rst) { rptr <= 0; wptr <= 0 }
+        helse do
+            hif(~rsync) do
+                hif (~rreq) { rack <= 0 }
+                hif(rreq & (~rack) & (rptr != wptr)) do
+                    rdata <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    rack <= 1
+                end
+            end
+
+            hif(~wsync) do
+                hif (~wreq) { wack <= 0 }
+                hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
+                    buffer[wptr] <= wdata
+                    wptr <= (wptr + 1) % depth
+                    wack <= 1
+                end
+            end
+        end
+    end
+
+    reader_output :rreq, :rptr, :rsync
+    reader_input :rdata, :rack, :wptr, :buffer
+
+    # The read primitive.
+    reader do |blk,target|
+        if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
+            # Same clk event, synchrone case: perform a direct access.
+            # Now perform the access.
+            top_block.unshift do
+                rsync <= 1
+                rreq <= 0
+            end
+            seq do
+                hif(rptr != wptr) do
+                    # target <= rdata
+                    target <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    blk.call if blk
+                end
+            end
+        else
+            # Different clk event, perform a decoupled access.
+            top_block.unshift do
+                rsync <= 0
+                rreq <= 0
+            end
+            par do
+                hif (~rack) { rreq <= 1 }
+                helsif(rreq) do
+                    rreq <= 0
+                    target <= rdata
+                    blk.call if blk
+                end
+            end
+        end
+    end
+
+    writer_output :wreq, :wdata, :wptr, :wsync, :buffer
+    writer_input :wack, :rptr
+
+    # The write primitive.
+    writer do |blk,target|
+        if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
+            # Same clk event, synchrone case: perform a direct access.
+            top_block.unshift do
+                wsync <= 1
+                wreq <= 0
+            end
+            hif(((wptr+1) % depth) != rptr) do
+                buffer[wptr] <= target
+                wptr <= (wptr + 1) % depth
+                blk.call if blk
+            end
+        else
+            # Different clk event, asynchrone case: perform a decoupled access.
+            top_block.unshift do
+                wsync <= 0
+                wreq <= 0
+            end
+            seq do
+                hif (~wack) do
+                    wreq <= 1
+                    wdata <= target
+                end
+                helsif(wreq) do
+                    wreq <= 0
+                    blk.call if blk
+                end
+            end
+        end
+    end
+end
+
+
+
+
+# Module for testing the connector.
+system :with_connectors do
+    inner :clk, :rst
+    [4].inner :counter, :res_0,:res_1,:res_2,:res_3
+    inner :ack_in, :ack_out
+
+    # The input queue.
+    queue(bit[4],4,clk,rst).(:in_qu)
+
+    # The first output queue.
+    queue(bit[4],4,clk,rst).(:out_qu0)
+    queue(bit[4],4,clk,rst).(:out_qu1)
+    queue(bit[4],4,clk,rst).(:out_qu2)
+    queue(bit[4],4,clk,rst).(:out_qu3)
+
+    # Connect them
+    duplicator([4],clk.negedge,in_qu,[out_qu0,out_qu1,out_qu2,out_qu3])
+
+    # # Slow version, always work
+    # par(clk.posedge) do
+    #     ack_in <= 0
+    #     ack_out <= 1
+    #     hif(rst) { counter <= 0 }
+    #     helse do
+    #         hif(ack_out) do
+    #             ack_out <= 0
+    #             in_qu.write(counter)  do
+    #                 ack_in <= 1
+    #                 counter <= counter + 1
+    #             end
+    #         end
+    #         hif(ack_in) do
+    #             out_qu0.read(res_0)
+    #             out_qu1.read(res_1)
+    #             out_qu2.read(res_2)
+    #             out_qu3.read(res_3) { ack_out <= 1 }
+    #         end
+    #     end
+    # end
+
+    # Fast version but assumes connected channels are blocking
+    par(clk.posedge) do
+        ack_in <= 0
+        hif(rst) { counter <= 0 }
+        helse do
+            in_qu.write(counter)  do
+                ack_in <= 1
+                counter <= counter + 1
+            end
+            hif(ack_in) do
+                out_qu0.read(res_0)
+                out_qu1.read(res_1)
+                out_qu2.read(res_2)
+                out_qu3.read(res_3)
+            end
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        16.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -32,6 +32,18 @@ system :fix_test do
         !10.ns
         d <= d + c 
         !10.ns
+        d <= d / c
+        !10.ns
+        d <= d / 3.to_fix(4)
+        !10.ns
+        d <= 1.to_fix(4) - d
+        !10.ns
+        d <= -d
+        !10.ns
+        d <= d * 3.to_fix(4)
+        !10.ns
+        d <= -d
+        !10.ns
         a <= -0.375.to_fix(4)
         b <= 1.625.to_fix(4)
         !10.ns

data/lib/HDLRuby/hdr_samples/with_memory_rom.rb

@@ -0,0 +1,53 @@
+require 'std/memory.rb'
+
+include HDLRuby::High::Std
+
+
+
+
+
+# A system testing the rom channel.
+system :rorm_test do
+    inner :clk,:rst
+    [8].inner :value
+    inner :addr
+
+    # Declares a 8-bit-data and 1 element rom address synchronous memory
+    # on negative edge of clk.
+    # mem_rom([8],2,clk,rst,[_00000110,_00000111], rinc: :rst).(:romI)
+    mem_rom([8],1,clk,rst,[_00000110], rinc: :rst).(:romI)
+    rd = romI.branch(:rinc)
+
+    par(clk.posedge) do
+        hif(rst) { addr <= 0 }
+        helse do
+            rd.read(value)
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        10.times do
+            clk <= 1
+            !10.ns
+            clk <= 0
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_multi_channels.rb

@@ -10,36 +10,51 @@ channel(:queue) do |typ,depth,clk,rst|
     # The read and write pointers.
     [depth.width].inner :rptr, :wptr
     # The read and write command signals.
-    inner :rcmd, :wcmd
+    inner :rreq, :wreq
     # The read and write ack signals.
     inner :rack, :wack
-    # The ack check deactivator (for synchron accesses).
-    inner :hrack, :hwack
     # The read/write data registers.
     typ.inner :rdata, :wdata
 
+    # The flags telling of the channel is synchronized
+    inner :rsync, :wsync
+
     # The process handling the decoupled access to the buffer.
     par(clk.posedge) do
-        # rack <= 0
-        # wack <= 0
-        hif (~rcmd) { rack <= 0 }
-        hif (~wcmd) { wack <= 0 }
         hif(rst) { rptr <= 0; wptr <= 0 }
-        hif(rcmd & (hrack|~rack) & (rptr != wptr)) do
-            rptr <= (rptr + 1) % depth
-            rack <= 1
-        end
-        hif(wcmd & (hwack|~wack) & (((wptr+1) % depth) != rptr)) do
-            buffer[wptr] <= wdata
-            # buffer[1] <= wdata
-            wptr <= (wptr + 1) % depth
-            wack <= 1
+        helse do
+            # hif(rsync) do
+            #     hif(rptr != wptr) do
+            #         rdata <= buffer[rptr]
+            #     end
+            # end
+            # helse do
+            hif(~rsync) do
+                hif (~rreq) { rack <= 0 }
+                hif(rreq & (~rack) & (rptr != wptr)) do
+                    rdata <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    rack <= 1
+                end
+            end
+
+            # hif(wsync) do
+            #     buffer[wptr] <= wdata
+            # end
+            # helse do
+            hif(~wsync) do
+                hif (~wreq) { wack <= 0 }
+                hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
+                    buffer[wptr] <= wdata
+                    wptr <= (wptr + 1) % depth
+                    wack <= 1
+                end
+            end
         end
     end
-    par { rdata <= buffer[rptr] }
 
-    reader_output :rcmd, :rptr, :hrack
-    reader_input :rdata, :rack
+    reader_output :rreq, :rptr, :rsync
+    reader_input :rdata, :rack, :wptr, :buffer
 
     # The read primitive.
     reader do |blk,target|
@@ -47,58 +62,66 @@ channel(:queue) do |typ,depth,clk,rst|
             # Same clk event, synchrone case: perform a direct access.
             # Now perform the access.
             top_block.unshift do
-                rcmd <= 0
-                hrack <= 1
+                rsync <= 1
+                rreq <= 0
             end
             seq do
-                rptr <= (rptr + 1) % depth
-                target <= rdata
-                blk.call if blk
+                hif(rptr != wptr) do
+                    # target <= rdata
+                    target <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    blk.call if blk
+                end
             end
         else
             # Different clk event, perform a decoupled access.
             top_block.unshift do
-                rcmd <= 0
-                hrack <= 0
+                rsync <= 0
+                rreq <= 0
             end
-            seq do
-                hif(rack) do
-                    blk.call if blk
-                end
-                helse do
-                    rcmd <= 1 
+            par do
+                hif (~rack) { rreq <= 1 }
+                helsif(rreq) do
+                    rreq <= 0
                     target <= rdata
+                    blk.call if blk
                 end
             end
         end
     end
 
-    writer_output :wcmd, :wdata, :hwack
-    writer_input :wack
+    writer_output :wreq, :wdata, :wptr, :wsync, :buffer
+    writer_input :wack, :rptr
 
     # The write primitive.
     writer do |blk,target|
         if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
             # Same clk event, synchrone case: perform a direct access.
             top_block.unshift do
-                wcmd <= 0
-                hwack <= 1
+                wsync <= 1
+                wreq <= 0
+            end
+            hif(((wptr+1) % depth) != rptr) do
+                # wdata <= target
+                buffer[wptr] <= target
+                wptr <= (wptr + 1) % depth
+                blk.call if blk
             end
-            wcmd <= 1
-            wdata <= target
-            blk.call if blk
         else
             # Different clk event, asynchrone case: perform a decoupled access.
             top_block.unshift do
-                wcmd <= 0
-                hwack <= 0
+                wsync <= 0
+                wreq <= 0
             end
             seq do
-                hif(wack) do
+                hif (~wack) do
+                    wreq <= 1
+                    wdata <= target
+                end
+                helsif(wreq) do
+                    wreq <= 0
                     blk.call if blk
                 end
-                helse { wcmd <= 1 }
-                wdata <= target
             end
         end
     end
@@ -135,7 +158,7 @@ channel(:handshake) do |typ|
     # The data signal.
     typ.inner :data
     # The request and acknowledge.
-    typ.inner :req, :ack
+    inner :req, :ack
 
     reader_input :ack, :data
     reader_output :req
@@ -174,110 +197,102 @@ channel(:handshake) do |typ|
 end
 
 
-# $mode = :sync
-# $mode = :nsync
-# $mode = :async
-# $mode = :proco  # Producter / Consummer
+# $mode: channel clock, producer clock, consumer clock (n: not clock)
 # $channel = :register
 # $channel = :handshake
 # $channel = :queue
 
 # The configuration scenarii
-$scenarii = [ [:sync,  :register], [:sync,  :handshake], [:sync,  :queue],
-              [:nsync, :register], [:nsync, :handshake], [:nsync, :queue],
-              [:async, :register], [:async, :handshake], [:async, :queue],
-              [:proco, :register], [:proco, :handshake], [:proco, :queue] ]
+$scenarii = [
+              [:_clk2_clk2,      :register],    #  0
+              [:_clk2_nclk2,     :register],    #  1
+              [:_clk2_clk3,      :register],    #  2
+              [:_clk3_clk2,      :register],    #  3
+              [:_clk2_clk2,      :handshake],   #  4
+              [:_clk2_nclk2,     :handshake],   #  5
+              [:_clk2_clk3,      :handshake],   #  6
+              [:_clk3_clk2,      :handshake],   #  7
+              [:clk2_clk2_clk2,  :queue],       #  8
+              [:clk2_clk2_nclk2, :queue],       #  9
+              [:clk1_clk2_clk3,  :queue],       # 10
+              [:clk3_clk2_clk1,  :queue],       # 11
+              [:clk2_clk3_clk1,  :queue],       # 12
+              [:clk2_clk1_clk3,  :queue],       # 13
+            ]
 
 # The configuration
-$mode, $channel = $scenarii[11]
+# $mode, $channel = $scenarii[11]
+$mode, $channel = $scenarii[ARGV[-1].to_i]
+puts "scenario: #{$scenarii[ARGV[-1].to_i]}"
 
 # Testing the queue channel.
 system :test_queue do
-    inner :clk, :rst, :clk2, :clk3
-    [8].inner :idata, :odata
+    inner :rst, :clk1, :clk2, :clk3
+    [8].inner :idata, :odata, :odata2
     [4].inner :counter
 
+
+    # Assign the clocks
+    mode = $mode.to_s.split("_")
+    if ($channel == :queue) then
+        clk_que = send(mode[0])
+    end
+    ev_pro = mode[1][0] == "n" ? 
+        send(mode[1][1..-1]).negedge : send(mode[1]).posedge
+    ev_con = mode[2][0] == "n" ? 
+        send(mode[2][1..-1]).negedge : send(mode[2]).posedge
+
+    # Set up the channel
     if $channel == :register then
         register(bit[8]).(:my_ch)
     elsif $channel == :handshake then
         handshake(bit[8],rst).(:my_ch)
     elsif $channel == :queue then
-        queue(bit[8],5,clk,rst).(:my_ch)
+        queue(bit[8],3,clk_que,rst).(:my_ch)
     end
 
-    ev = $mode == :sync ? clk.posedge : 
-         $mode == :nsync ? clk.negedge : clk2.posedge
-
-    if $mode != :proco then
-        # Sync/Neg sync and async tests mode
-        par(ev) do
-            hif(rst) do
-                counter <= 0
-                idata <= 0
-                odata <= 0
-            end
-            helse do
-                hif (counter < 4) do
-                    my_ch.write(idata) do
-                        idata <= idata + 1
-                        counter <= counter + 1
-                    end
-                end
-                helsif ((counter > 10) & (counter < 15)) do
-                    my_ch.read(odata) do
-                        idata <= idata - odata
-                        counter <= counter + 1
-                    end
-                end
-                helse do
-                    counter <= counter + 1
-                end
-            end
+    # Producter/consumer mode
+    # Producer
+    par(ev_pro) do
+        hif(rst) do
+            idata <= 0
         end
-    else
-        # Producter/consumer mode
-        # Producer
-        par(clk2.posedge) do
-            hif(rst) do
-                idata <= 0
-            end
-            helse do
-                my_ch.write(idata) do
-                    idata <= idata + 1
-                end
+        helse do
+            my_ch.write(idata) do
+                idata <= idata + 1
             end
         end
-        # Consumer
-        par(clk3.posedge) do
-            hif(rst) do
-                counter <= 0
-            end
-            helse do
-                my_ch.read(odata) do
-                    counter <= counter + 1
-                end
+    end
+    # Consumer
+    par(ev_con) do
+        hif(rst) do
+            counter <= 0
+        end
+        helse do
+            my_ch.read(odata) do
+                counter <= counter + 1
             end
         end
     end
 
     timed do
-        clk <= 0
+        clk1 <= 0
         clk2 <= 0
         clk3 <= 0
         rst <= 0
         !10.ns
-        clk <= 1
+        clk1 <= 1
         !10.ns
-        clk <= 0
+        clk1 <= 0
         rst <= 1
         !3.ns
         clk2 <= 1
         !3.ns
         clk3 <= 0
         !4.ns
-        clk <= 1
+        clk1 <= 1
         !10.ns
-        clk <= 0
+        clk1 <= 0
         !3.ns
         clk2 <= 0
         !3.ns
@@ -286,9 +301,9 @@ system :test_queue do
         rst <= 0
         !2.ns
         64.times do
-            clk <= 1
+            clk1 <= 1
             !10.ns
-            clk <= 0
+            clk1 <= 0
             !3.ns
             clk2 <= ~clk2
             !3.ns

data/lib/HDLRuby/std/connector.rb

@@ -0,0 +1,42 @@
+module HDLRuby::High::Std
+
+##
+# Standard HDLRuby::High library: connectors between channels
+# 
+########################################################################
+
+    # Function for generating a connector that duplicates the output of
+    # channel +inch+ and connect it to channels +outchs+ with data of
+    # +typ+.
+    # The duplication is done according to event +ev+.
+    function :duplicator do |typ, ev, inch, outchs|
+        ev = ev.poswedge unless ev.is_a?(Event)
+        inner :in_ack, :in_req
+        out_chacks = outchs.map.with_index do |ch,i|
+            [ ch, inner(:"out_ack#{i}") ]
+        end
+        typ.inner :data
+        par(ev) do
+            in_req <= 1
+            out_chacks.each { |ch,ack| ack <= 0 }
+            out_chacks.each do |ch,ack| 
+                hif(ack == 1) { in_req <= 0 }
+            end
+            hif(in_req) do
+                in_ack <= 0
+                inch.read(data) { in_ack <= 1 }
+            end
+            hif(in_ack) do
+                out_chacks.each do |ch,ack|
+                    hif(ack == 0) { ch.write(data) { ack <= 1 } }
+                end
+                hif (out_chacks.reduce(_1) { |sum,(ch,ack)| ack & sum }) do
+                    out_chacks.each { |ch,ack| ack <= 0 }
+                end
+            end
+        end
+    end
+
+
+
+end 

data/lib/HDLRuby/std/memory.rb

@@ -34,6 +34,7 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Ensure clk_e is an event, if not set it to a positive edge.
     clk_e = clk_e.posedge unless clk_e.is_a?(Event)
 
@@ -209,6 +210,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Process the table of reset mapping for the branches.
     # Ensures br_srts is a hash.
     br_rsts = br_rsts.to_hash
@@ -292,17 +294,43 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                 trig_r <= 0
             end
             # The read procedure.
+        #     par do
+        #         hif(rst == 0) do
+        #             # No reset, so can perform the read.
+        #             hif(trig_r == 1) do
+        #                 # The trigger was previously set, read ok.
+        #                 target <= dbus_r
+        #                 blk.call if blk
+        #             end
+        #             # Prepare the read.
+        #             abus_r <= abus_r + 1
+        #             trig_r <= 1
+        #         end
+        #     end
+            # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r + 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r + 1
+                        if 2**size.width != size then
+                            abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                        else
+                            abus_r <= abus_r + 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r + 1
-                    trig_r <= 1
                 end
             end
         end
@@ -331,18 +359,44 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                 # Reset so switch of the access trigger.
                 trig_r <= 0
             end
+            # # The read procedure.
+            # par do
+            #     hif(rst == 0) do
+            #         # No reset, so can perform the read.
+            #         hif(trig_r == 1) do
+            #             # The trigger was previously set, read ok.
+            #             target <= dbus_r
+            #             blk.call if blk
+            #         end
+            #         # Prepare the read.
+            #         abus_r <= abus_r - 1
+            #         trig_r <= 1
+            #     end
+            # end
             # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r - 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r - 1
+                        if 2**size.width != size then
+                            abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                        else
+                            abus_r <= abus_r - 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r - 1
-                    trig_r <= 1
                 end
             end
         end
@@ -392,6 +446,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Process the table of reset mapping for the branches.
     # puts "first br_rsts=#{br_rsts}"
     # if br_rsts.is_a?(Array) then
@@ -551,7 +606,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     helse do
                         # Prepare the read.
-                        abus_r <= abus_r + 1
+                        # abus_r <= abus_r + 1
+                        if 2**size.width != size then
+                            abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                        else
+                            abus_r <= abus_r + 1
+                        end
                         trig_r <= 1
                     end
                 end
@@ -588,7 +648,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -620,18 +685,44 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                 # Reset so switch of the access trigger.
                 trig_r <= 0
             end
+            # # The read procedure.
+            # par do
+            #     hif(rst == 0) do
+            #         # No reset, so can perform the read.
+            #         hif(trig_r == 1) do
+            #             # The trigger was previously set, read ok.
+            #             target <= dbus_r
+            #             blk.call if blk
+            #         end
+            #         # Prepare the read.
+            #         abus_r <= abus_r - 1
+            #         trig_r <= 1
+            #     end
+            # end
             # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r - 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r - 1
+                        if 2**size.width != size then
+                            abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                        else
+                            abus_r <= abus_r - 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r - 1
-                    trig_r <= 1
                 end
             end
         end
@@ -666,7 +757,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w - 1
+                    # abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -860,7 +956,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_r
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_r
         reader_inout :abus_r
 
         # Defines the read procedure at address +addr+
@@ -883,7 +981,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next read.
-                    abus_r <= abus_r + 1
+                    # abus_r <= abus_r + 1
+                    if 2**size.width != size then
+                        abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                    else
+                        abus_r <= abus_r + 1
+                    end
                 end
             end
         end
@@ -899,7 +1002,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             writer_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_w
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_w
         writer_inout :abus_w
 
         # Defines the write procedure at address +addr+
@@ -922,7 +1027,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                 end
             end
         end
@@ -940,7 +1050,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_r
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_r
         reader_inout :abus_r
 
         # Defines the read procedure at address +addr+
@@ -963,7 +1075,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next read.
-                    abus_r <= abus_r - 1
+                    # abus_r <= abus_r - 1
+                    if 2**size.width != size then
+                        abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                    else
+                        abus_r <= abus_r - 1
+                    end
                 end
             end
         end
@@ -979,7 +1096,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_w
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_w
         reader_inout :abus_w
 
         # Defines the write procedure at address +addr+
@@ -1002,7 +1121,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next write.
-                    abus_w <= abus_w - 1
+                    # abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                 end
             end
         end
@@ -1050,7 +1174,9 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size*nbanks-1).width
+    awidth = 1 if awidth == 0
     awidth_b = (size-1).width # Bank width
+    awidth_b = 1 if awidth_b == 0
     # Ensures br_srts is a hash.
     br_rsts = br_rsts.to_hash
 
@@ -1211,7 +1337,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                         blk.call if blk
                     end
                     # Prepare the read.
-                    abus_r <= abus_r + 1
+                    # abus_r <= abus_r + 1
+                    if 2**size.width != size then
+                        abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                    else
+                        abus_r <= abus_r + 1
+                    end
                     trig_r <= 1
                 end
             end
@@ -1247,7 +1378,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -1288,7 +1424,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                         blk.call if blk
                     end
                     # Prepare the read.
-                    abus_r <= abus_r - 1
+                    # abus_r <= abus_r - 1
+                    if 2**size.width != size then
+                        abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                    else
+                        abus_r <= abus_r - 1
+                    end
                     trig_r <= 1
                 end
             end
@@ -1325,6 +1466,11 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the write.
                     abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.8"
+  VERSION = "2.4.14"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.8
+  version: 2.4.14
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-10-11 00:00:00.000000000 Z
+date: 2020-11-16 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -84,6 +84,7 @@ files:
 - lib/HDLRuby/hdr_samples/include.rb
 - lib/HDLRuby/hdr_samples/instance_open.rb
 - lib/HDLRuby/hdr_samples/linear_test.rb
+- lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb
 - lib/HDLRuby/hdr_samples/mei8.rb
 - lib/HDLRuby/hdr_samples/mei8_bench.rb
 - lib/HDLRuby/hdr_samples/memory_test.rb
@@ -119,12 +120,14 @@ files:
 - lib/HDLRuby/hdr_samples/tuple.rb
 - lib/HDLRuby/hdr_samples/with_channel.rb
 - lib/HDLRuby/hdr_samples/with_class.rb
+- lib/HDLRuby/hdr_samples/with_connector.rb
 - lib/HDLRuby/hdr_samples/with_decoder.rb
 - lib/HDLRuby/hdr_samples/with_fixpoint.rb
 - lib/HDLRuby/hdr_samples/with_fsm.rb
 - lib/HDLRuby/hdr_samples/with_linear.rb
 - lib/HDLRuby/hdr_samples/with_loop.rb
 - lib/HDLRuby/hdr_samples/with_memory.rb
+- lib/HDLRuby/hdr_samples/with_memory_rom.rb
 - lib/HDLRuby/hdr_samples/with_multi_channels.rb
 - lib/HDLRuby/hdr_samples/with_reconf.rb
 - lib/HDLRuby/hdrcc.rb
@@ -270,6 +273,7 @@ files:
 - lib/HDLRuby/sim/hruby_value_pool.c
 - lib/HDLRuby/std/channel.rb
 - lib/HDLRuby/std/clocks.rb
+- lib/HDLRuby/std/connector.rb
 - lib/HDLRuby/std/counters.rb
 - lib/HDLRuby/std/decoder.rb
 - lib/HDLRuby/std/fixpoint.rb