HDLRuby 2.4.6 → 2.4.12

checksums.yaml

@@ -1,7 +1,7 @@
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data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb

@@ -0,0 +1,25 @@
+#!/usr/bin/ruby
+# Script for generating the vcd files.
+
+# The configuration scenarii
+$scenarii = [
+              [:sync,  :register],     # 00
+              [:sync,  :handshake],    # 01
+              [:sync,  :queue],        # 02
+              [:nsync, :register],     # 03
+              [:nsync, :handshake],    # 04
+              [:nsync, :queue],        # 05
+              [:async, :register],     # 06
+              [:async, :handshake],    # 07
+              [:async, :queue],        # 08
+              [:proco, :register],     # 09
+              [:proco, :handshake],    # 10
+              [:proco, :queue],        # 11
+              [:double,:register],     # 12
+              [:double,:handshake],    # 13 
+              [:double,:queue]         # 14
+            ]
+(0..11).each do |i|
+    `bundle exec ../hdrcc.rb -S --vcd with_multi_channels.rb WithMultiChannelPaper #{i}`
+    `mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{$scenarii[i][0]}_#{$scenarii[i][1]}.vcd`
+end

data/lib/HDLRuby/hdr_samples/mei8_bench.rb

@@ -5,7 +5,7 @@ include HDLRuby::High::Std
 # A simple implementation of the MEI8 processor.
 #
 # In this implementation, the program is hard-coded in an internal ROM
-system :mei8 do |prog_file = "./prog_encrypt.obj"|
+system :mei8 do |prog_file = "./prog.obj"|
     # Clock and reset.
     input :clk, :rst
     # Bus.

data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb

@@ -0,0 +1,49 @@
+
+# A benchmark for testing the arithmetic with signed values.
+system :neg_arith_bench do
+    signed[11..0].inner :x,:y,:z
+
+    timed do
+        x <= 10
+        y <= 10
+        z <= 0
+        !10.ns
+        z <= 10 * 10
+        !10.ns
+        z <= x * y
+        !10.ns
+        x <= 10
+        y <= -10
+        !10.ns
+        z <= 10 * (-10)
+        !10.ns
+        z <= x * y
+        !10.ns
+        x <= -10
+        y <= 10
+        !10.ns
+        z <= (-10) * 10
+        !10.ns
+        z <= x * y
+        !10.ns
+        x <= -10
+        y <= -10
+        !10.ns
+        z <= (-10) * (-10)
+        !10.ns
+        z <= x * y
+        !10.ns
+        x <= _000000011010
+        y <= _000011111010
+        z <= 0
+        !10.ns
+        z <= x * y
+        !10.ns
+        x <= _000000011010
+        y <= _111111111010
+        z <= 0
+        !10.ns
+        z <= x * y
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -31,5 +31,35 @@ system :fix_test do
         d <= 0
         !10.ns
         d <= d + c 
+        !10.ns
+        d <= d / c
+        !10.ns
+        d <= d / 3.to_fix(4)
+        !10.ns
+        d <= 1.to_fix(4) - d
+        !10.ns
+        d <= -d
+        !10.ns
+        d <= d * 3.to_fix(4)
+        !10.ns
+        d <= -d
+        !10.ns
+        a <= -0.375.to_fix(4)
+        b <= 1.625.to_fix(4)
+        !10.ns
+        c <= a * b
+        !10.ns
+        # a <= _00010000
+        # b <= _00010101
+        a <= _0000111x
+        b <= _1110011x
+        !10.ns
+        # a <= a & _11111110
+        # b <= b | _00000001
+        a <= a | _00000001
+        b <= b | _00000001
+        !10.ns
+        c <= a * b
+        !10.ns
     end
 end

data/lib/HDLRuby/hdr_samples/with_memory_rom.rb

@@ -0,0 +1,53 @@
+require 'std/memory.rb'
+
+include HDLRuby::High::Std
+
+
+
+
+
+# A system testing the rom channel.
+system :rorm_test do
+    inner :clk,:rst
+    [8].inner :value
+    inner :addr
+
+    # Declares a 8-bit-data and 1 element rom address synchronous memory
+    # on negative edge of clk.
+    # mem_rom([8],2,clk,rst,[_00000110,_00000111], rinc: :rst).(:romI)
+    mem_rom([8],1,clk,rst,[_00000110], rinc: :rst).(:romI)
+    rd = romI.branch(:rinc)
+
+    par(clk.posedge) do
+        hif(rst) { addr <= 0 }
+        helse do
+            rd.read(value)
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        10.times do
+            clk <= 1
+            !10.ns
+            clk <= 0
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_multi_channels.rb

@@ -60,12 +60,16 @@ channel(:queue) do |typ,depth,clk,rst|
             top_block.unshift do
                 rcmd <= 0
                 hrack <= 0
-            end
-            seq do
                 hif(rack) do
                     blk.call if blk
                 end
-                helse do
+            end
+            seq do
+                # hif(rack) do
+                #     blk.call if blk
+                # end
+                # helse do
+                hif(rack==0) do
                     rcmd <= 1 
                     target <= rdata
                 end
@@ -92,12 +96,16 @@ channel(:queue) do |typ,depth,clk,rst|
             top_block.unshift do
                 wcmd <= 0
                 hwack <= 0
-            end
-            seq do
                 hif(wack) do
                     blk.call if blk
                 end
-                helse { wcmd <= 1 }
+            end
+            seq do
+                # hif(wack) do
+                #     blk.call if blk
+                # end
+                # helse 
+                hif(wack==0) { wcmd <= 1 }
                 wdata <= target
             end
         end
@@ -135,7 +143,7 @@ channel(:handshake) do |typ|
     # The data signal.
     typ.inner :data
     # The request and acknowledge.
-    typ.inner :req, :ack
+    inner :req, :ack
 
     reader_input :ack, :data
     reader_output :req
@@ -173,48 +181,116 @@ channel(:handshake) do |typ|
     end
 end
 
+# Channel describing a handshake for transmitting data of +typ+ type, reset
+# by +rst+
+channel(:handshake2) do |typ|
+    # The data signal.
+    typ.inner :data
+    # The request and acknowledge.
+    inner :req, :ack
+    # The write flag
+    inner :wf
+
+    reader_input :ack, :data
+    reader_output :req
+
+    # The read primitive.
+    reader do |blk,target|
+        top_block.unshift do
+            req <= 0
+            hif(ack & req == 1) do
+                target <= data
+                req <= 0
+                blk.call if blk
+            end
+        end
+        hif(ack == 0) do
+            req <= 1
+        end
+    end
+
+    writer_input :req
+    writer_output :ack, :data
+    writer_inout :wf
+
+    # The read primitive.
+    writer do |blk,target|
+        top_block.unshift do
+            ack <= 0
+            hif(wf & req & ~ack == 1) do
+                data <= target
+                ack <= 1
+                blk.call if blk
+            end
+            hif(~req) { wf <= 0 }
+        end
+        hif(~ack) do
+            wf <= 1
+        end
+    end
+end
+
 
 # $mode = :sync
 # $mode = :nsync
 # $mode = :async
-# $mode = :proco  # Producter / Consummer
+# $mode = :proco  # Producer / Consummer
+# $mode = :double # Producer and Consummer with double channels.
 # $channel = :register
 # $channel = :handshake
 # $channel = :queue
 
 # The configuration scenarii
-$scenarii = [ [:sync,  :register], [:sync,  :handshake], [:sync,  :queue],
-              [:nsync, :register], [:nsync, :handshake], [:nsync, :queue],
-              [:async, :register], [:async, :handshake], [:async, :queue],
-              [:proco, :register], [:proco, :handshake], [:proco, :queue] ]
+$scenarii = [
+              [:sync,  :register],     #  0
+              [:sync,  :handshake],    #  1
+              [:sync,  :queue],        #  3
+              [:nsync, :register],     #  4
+              [:nsync, :handshake],    #  5
+              [:nsync, :queue],        #  6
+              [:async, :register],     #  7
+              [:async, :handshake],    #  8
+              [:async, :queue],        #  9
+              [:proco, :register],     # 10
+              [:proco, :handshake],    # 11
+              [:proco, :queue],        # 12
+              [:double,:register],     # 13
+              [:double,:handshake],    # 14
+              [:double,:queue]         # 15
+            ]
 
 # The configuration
-$mode, $channel = $scenarii[11]
+# $mode, $channel = $scenarii[11]
+$mode, $channel = $scenarii[ARGV[-1].to_i]
+puts "scenario: #{$scenarii[ARGV[-1].to_i]}"
 
 # Testing the queue channel.
 system :test_queue do
     inner :clk, :rst, :clk2, :clk3
-    [8].inner :idata, :odata
+    [8].inner :idata, :odata, :odata2
     [4].inner :counter
 
     if $channel == :register then
         register(bit[8]).(:my_ch)
+        register(bit[8]).(:my_ch2)
     elsif $channel == :handshake then
         handshake(bit[8],rst).(:my_ch)
+        handshake(bit[8],rst).(:my_ch2)
     elsif $channel == :queue then
         queue(bit[8],5,clk,rst).(:my_ch)
+        queue(bit[8],5,clk,rst).(:my_ch2)
     end
 
     ev = $mode == :sync ? clk.posedge : 
          $mode == :nsync ? clk.negedge : clk2.posedge
 
-    if $mode != :proco then
+    if $mode != :proco && $mode != :double then
         # Sync/Neg sync and async tests mode
         par(ev) do
             hif(rst) do
                 counter <= 0
                 idata <= 0
-                odata <= 0
+                # odata <= 0
             end
             helse do
                 hif (counter < 4) do
@@ -225,7 +301,7 @@ system :test_queue do
                 end
                 helsif ((counter > 10) & (counter < 15)) do
                     my_ch.read(odata) do
-                        idata <= idata - odata
+                        # idata <= idata - odata
                         counter <= counter + 1
                     end
                 end
@@ -234,7 +310,7 @@ system :test_queue do
                 end
             end
         end
-    else
+    elsif $mode == :proco then
         # Producter/consumer mode
         # Producer
         par(clk2.posedge) do
@@ -258,6 +334,25 @@ system :test_queue do
                 end
             end
         end
+    else
+        # Producer and consumer are commicating through two layers of channels
+        par(ev) do
+            hif(rst) do
+                counter <= 0
+                idata <= 0
+            end
+            helse do
+                my_ch.write(idata) do
+                    idata <= idata + 1
+                end
+                my_ch.read(odata) do
+                    my_ch2.write(odata)
+                end
+                my_ch2.read(odata2) do
+                    counter <= counter + 1
+                end
+            end
+        end
     end
 
     timed do

data/lib/HDLRuby/hruby_bstr.rb

@@ -32,6 +32,7 @@ module HDLRuby
         #   and negative when "1".
         # * when not present it is assumed to be within str.
         def initialize(str,sign = nil)
+            # puts "str=#{str}"
             # Maybe str is an numeric.
             if str.is_a?(Numeric) then
                 # Yes, convert it to a binary string.
@@ -74,6 +75,7 @@ module HDLRuby
                 end.reverse.join
             end
             @str += str.to_s.downcase
+            # puts "@str=#{@str}"
             unless @str.match(/^[0-1zx]+$/) then
                 raise "Invalid value for creating a bit string: #{str}"
             end

data/lib/HDLRuby/hruby_low2c.rb

@@ -1450,7 +1450,11 @@ module HDLRuby::Low
                 if self.content >= 0 then
                     str = self.content.to_s(2).rjust(width,"0").upcase
                 else
-                    str = (2**width+self.content).to_s(2).upcase
+                    # Compute the extension to the next multiple
+                    # of int_width
+                    ext_width = (((width-1) / Low2C.int_width)+1)*Low2C.int_width
+                    # Convert the string.
+                    str = (2**ext_width+self.content).to_s(2).upcase
                 end
                 # puts "content=#{self.content} str=#{str}"
             end
@@ -1465,13 +1469,14 @@ module HDLRuby::Low
                 res << " };\n"
                 # Create the value.
                 res << " " * (level+1)*3
-                # puts "str=#{str} type width=#{self.type.width}"
+                # puts "str=#{str} type width=#{self.type.width} signed? #{type.signed?}"
                 res << "return make_set_value(#{self.type.to_c(level+1)},1," +
                        "data);\n" 
             else
                 # No, generate a bit string value.
                 res << " " * (level+1)*3
-                res << "static unsigned char data[] = \"#{str}\";\n"
+                # res << "static unsigned char data[] = \"#{str}\";\n"
+                res << "static unsigned char data[] = \"#{str.reverse}\";\n"
                 # Create the value.
                 res << " " * (level+1)*3
                 res << "return make_set_value(#{self.type.to_c(level+1)},0," +

data/lib/HDLRuby/sim/hruby_sim.h

@@ -50,8 +50,9 @@ typedef enum {
 
 /* The interface to the type engine. */
 typedef struct FlagsS_ {
-    unsigned int all;
-    unsigned int sign : 1; /* Tells if the type is signed or not. */
+    // unsigned int all;
+    // unsigned int sign : 1; /* Tells if the type is signed or not. */
+    unsigned int sign; /* Tells if the type is signed or not. */
 } FlagsS;
 
 /** The type structure. */

data/lib/HDLRuby/sim/hruby_sim_calc.c

@@ -70,7 +70,8 @@ static List hash_type[HASH_TYPE_SIZE] = {};
  *  @return the resulting type. */
 static int hash_value(unsigned long long base, unsigned long long number,
                       FlagsS flags) {
-    return ((base+flags.all)^(number)) & 1023;
+    // return ((base+flags.all)^(number)) & 1023;
+    return ((base+flags.sign)^(number)) & 1023;
 }
 
 /** Adds a type to the hash of types.
@@ -109,7 +110,8 @@ static Type get_hash_type(Type base, unsigned long long number) {
         while(elem) {
             Type type = elem->data;
             if ((type->base == bw) && (type->number == number) &&
-                (type->flags.all == flags.all)) {
+                // (type->flags.all == flags.all)) {
+                (type->flags.sign == flags.sign)) {
                 /* The type is found. */
                 return type;
             }
@@ -243,8 +245,10 @@ void resize_value(Value value, int size) {
 void set_value(Value value, int numeric, void* data) {
     value->numeric = numeric;
     if (numeric) {
+    // printf("set_value with data=%llx\n",*(unsigned long long*)data);
         value->data_int = *((unsigned long long*)data);
     } else  {
+        // printf("data=%s\n",(char*)data);
         memcpy(value->data_str,data,type_width(value->type)*sizeof(char));
     }
 }
@@ -254,6 +258,7 @@ void set_value(Value value, int numeric, void* data) {
  *  @param numeric tell if the value is in numeric form or in bitstring form
  *  @param data the source data */
 Value make_set_value(Type type, int numeric, void* data) {
+    // printf("make_set_value with type->flags.sign=%x\n",type->flags.sign);
     Value value = make_value(type,numeric);
     set_value(value,numeric,data);
     return value;
@@ -307,6 +312,7 @@ Value copy_value(Value src, Value dst) {
         /* Numeric copy. */
         dst->data_int = fix_numeric_type(dst->type,src->data_int);
     } else {
+        // printf("copy_value with bit string: %s\n",src->data_str);
         /* Resize the destination if required. */
         resize_value(dst,type_width(dst->type));
         /* Bitstring copy up to the end of dst or src. */
@@ -603,12 +609,14 @@ static Value sub_value_bitstring(Value src0, Value src1, Value dst) {
  *  @param dst the destination value
  *  @return dst */
 static Value mul_value_defined_bitstring(Value src0, Value src1, Value dst) {
+    // printf("mul_value_defined_bitstring with src0=%llx src1=%llx\n",value2integer(src0),value2integer(src1));
     /* Sets state of the destination using the first source. */
     dst->type = src0->type;
     dst->numeric = 1;
 
     /* Perform the multiplication. */
     dst->data_int = value2integer(src0) * value2integer(src1);
+    // printf("dst->data_int=%llx\n",dst->data_int);
     return dst;
 }
 
@@ -1172,7 +1180,7 @@ static Value equal_value_bitstring(Value src0, Value src1, Value dst) {
 static Value select_value_bitstring(Value cond, Value dst, unsigned int num,
         va_list args) 
 {
-    printf("select_value_bitstring with cond=%s\n",cond->data_str);
+    // printf("select_value_bitstring with cond=%s\n",cond->data_str);
     /* Get the first alternative for sizing the result. */
     Value src = va_arg(args,Value);
     /* Compute the width of the result in bits. */
@@ -1556,6 +1564,7 @@ static Value sub_value_numeric(Value src0, Value src1, Value dst) {
  *  @param dst the destination value
  *  @return dst */
 static Value mul_value_numeric(Value src0, Value src1, Value dst) {
+    // printf("mul_value_numeric with src0->data_int=%llx src1->data_int=%llx\n",src0->data_int, src1->data_int);
     /* Sets state of the destination using the first source. */
     dst->type = src0->type;
     dst->numeric = 1;
@@ -1823,7 +1832,7 @@ static Value concat_value_numeric_array(int num, int dir,
  *  @param dst the destination value
  *  @return dst */
 static Value cast_value_numeric(Value src, Type type, Value dst) {
-    // printf("cast_value_numeric with src=%llx",src->data_int);
+    // printf("cast_value_numeric with src=%llx\n",src->data_int);
     /* Copy the source to the destination. */
     dst->data_int = src->data_int;
     /* Update the destination type to the cast. */
@@ -2665,6 +2674,7 @@ unsigned long long value2integer(Value value) {
     char bit;
     /* Access the bitstring data. */
     char* data_str = value->data_str;
+    // printf("value2integer with data_str=%s\n",data_str);
     /* Copy the bits. */
     for (i=0; i<width && i<LONG_LONG_BIT; ++i) {
         /* Get the bit. */
@@ -2676,12 +2686,17 @@ unsigned long long value2integer(Value value) {
         /* Write the bit. */
         res = (res << 1) | bit;
     }
+    // printf("first res=%llx\n",res);
+    unsigned long long bit0 = (data_str[width-1]-'0') << i;
     /* Perform the sign extension if required. */
     if (i>=width && value->type->flags.sign) {
         for(; i<LONG_LONG_BIT; ++i) {
-            res = (res << 1) | bit;
+            // res = (res << 1) | bit;
+            res |= bit0;
+            bit0 <<= 1;
         }
     }
+    // printf("then res=%llx\n",res);
     return res;
 }
 

data/lib/HDLRuby/std/fixpoint.rb

@@ -52,10 +52,18 @@ module HDLRuby::High::Std
                         end
                         # Redefine the multiplication and division for fixed point.
                         typ.define_operator(:*) do |left,right|
-                            (left.as([isize+fsize*2])*right) >> fsize
+                            if (typ.signed?) then
+                                (left.as(signed[isize+fsize*2])*right) >> fsize
+                            else
+                                (left.as([isize+fsize*2])*right) >> fsize
+                            end
                         end
                         typ.define_operator(:/) do |left,right|
-                            (left.as([isize+fsize*2]) << fsize) / right
+                            if (typ.signed?) then
+                                (left.as(signed[isize+fsize*2]) << fsize) / right
+                            else
+                                (left.as([isize+fsize*2]) << fsize) / right
+                            end
                         end
                         typ
                     end

data/lib/HDLRuby/std/linear.rb

@@ -209,6 +209,7 @@ module HDLRuby::High::Std
         # lv and rv are valid.
         lvoks = lefts.each_with_index.map { |left,i| inner :"lvok#{i}" }
         inner :rvok
+        woks = lefts.each_with_index.map { |left,i| inner :"wok#{i}" }
         # Run flag
         inner :run
         par(ev) do
@@ -218,28 +219,39 @@ module HDLRuby::High::Std
                 rvok <= 0
                 lefts.each_with_index do |left,i|
                     lvoks[i] <= 0
-                    # accs[i].write(0)
-                    avs[i] <= 0
+                    # avs[i] <= 0
+                    woks[i] <= 0
                 end
             end
             hif(req | run) do
                 run <= 1
                 # Computation request.
-                right.read(rv) { rvok <= 1 }
+                hif(~rvok) { right.read(rv) { rvok <= 1 } }
                 lefts.each_with_index do |left,i|
-                    left.read(lvs[i])  { lvoks[i] <= 1 }
+                    hif(~lvoks[i]) { left.read(lvs[i])  { lvoks[i] <= 1 } }
                     # accs[i].read(avs[i])
-                    hif(lvoks[i] & rvok) do
+                    hif(lvoks[i] & rvok & ~woks[i]) do
                         ack <= 1
                         run <= 0
-                        # accs[i].write(add.(avs[i],mul.(lvs[i],rv)))
                         seq do
                             avs[i] <= add.(avs[i],mul.(lvs[i],rv))
-                            accs[i].write(avs[i])
+                            accs[i].write(avs[i]) do
+                                woks[i] <= 1
+                                # seq do
+                                #     lvoks[i] <= 0
+                                #     rvok <= lvoks.reduce(:|)
+                                # end
+                            end
                         end
                     end
+                    hif (woks.reduce(:&)) do
+                        woks.each { |wok| wok <= 0 }
+                        lvoks.each { | lvok| lvok <=0 }
+                        rvok <= 0
+                    end
                 end
             end
+            helse { avs.each {|av| av <= 0 } }
             # helse do
             #     rvok <= 0
             #     lefts.each_with_index do |left,i|

data/lib/HDLRuby/std/memory.rb

@@ -34,6 +34,7 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Ensure clk_e is an event, if not set it to a positive edge.
     clk_e = clk_e.posedge unless clk_e.is_a?(Event)
 
@@ -209,6 +210,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Process the table of reset mapping for the branches.
     # Ensures br_srts is a hash.
     br_rsts = br_rsts.to_hash
@@ -292,17 +294,43 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                 trig_r <= 0
             end
             # The read procedure.
+        #     par do
+        #         hif(rst == 0) do
+        #             # No reset, so can perform the read.
+        #             hif(trig_r == 1) do
+        #                 # The trigger was previously set, read ok.
+        #                 target <= dbus_r
+        #                 blk.call if blk
+        #             end
+        #             # Prepare the read.
+        #             abus_r <= abus_r + 1
+        #             trig_r <= 1
+        #         end
+        #     end
+            # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r + 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r + 1
+                        if 2**size.width != size then
+                            abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                        else
+                            abus_r <= abus_r + 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r + 1
-                    trig_r <= 1
                 end
             end
         end
@@ -331,18 +359,44 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                 # Reset so switch of the access trigger.
                 trig_r <= 0
             end
+            # # The read procedure.
+            # par do
+            #     hif(rst == 0) do
+            #         # No reset, so can perform the read.
+            #         hif(trig_r == 1) do
+            #             # The trigger was previously set, read ok.
+            #             target <= dbus_r
+            #             blk.call if blk
+            #         end
+            #         # Prepare the read.
+            #         abus_r <= abus_r - 1
+            #         trig_r <= 1
+            #     end
+            # end
             # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r - 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r - 1
+                        if 2**size.width != size then
+                            abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                        else
+                            abus_r <= abus_r - 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r - 1
-                    trig_r <= 1
                 end
             end
         end
@@ -392,6 +446,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Process the table of reset mapping for the branches.
     # puts "first br_rsts=#{br_rsts}"
     # if br_rsts.is_a?(Array) then
@@ -541,12 +596,24 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r + 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r + 1
+                        if 2**size.width != size then
+                            abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                        else
+                            abus_r <= abus_r + 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r + 1
-                    trig_r <= 1
                 end
             end
         end
@@ -581,7 +648,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -613,18 +685,44 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                 # Reset so switch of the access trigger.
                 trig_r <= 0
             end
+            # # The read procedure.
+            # par do
+            #     hif(rst == 0) do
+            #         # No reset, so can perform the read.
+            #         hif(trig_r == 1) do
+            #             # The trigger was previously set, read ok.
+            #             target <= dbus_r
+            #             blk.call if blk
+            #         end
+            #         # Prepare the read.
+            #         abus_r <= abus_r - 1
+            #         trig_r <= 1
+            #     end
+            # end
             # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r - 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r - 1
+                        if 2**size.width != size then
+                            abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                        else
+                            abus_r <= abus_r - 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r - 1
-                    trig_r <= 1
                 end
             end
         end
@@ -659,7 +757,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w - 1
+                    # abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -853,7 +956,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_r
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_r
         reader_inout :abus_r
 
         # Defines the read procedure at address +addr+
@@ -876,7 +981,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next read.
-                    abus_r <= abus_r + 1
+                    # abus_r <= abus_r + 1
+                    if 2**size.width != size then
+                        abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                    else
+                        abus_r <= abus_r + 1
+                    end
                 end
             end
         end
@@ -892,7 +1002,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             writer_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_w
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_w
         writer_inout :abus_w
 
         # Defines the write procedure at address +addr+
@@ -915,7 +1027,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                 end
             end
         end
@@ -933,7 +1050,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_r
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_r
         reader_inout :abus_r
 
         # Defines the read procedure at address +addr+
@@ -956,7 +1075,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next read.
-                    abus_r <= abus_r - 1
+                    # abus_r <= abus_r - 1
+                    if 2**size.width != size then
+                        abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                    else
+                        abus_r <= abus_r - 1
+                    end
                 end
             end
         end
@@ -972,7 +1096,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_w
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_w
         reader_inout :abus_w
 
         # Defines the write procedure at address +addr+
@@ -995,7 +1121,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next write.
-                    abus_w <= abus_w - 1
+                    # abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                 end
             end
         end
@@ -1043,7 +1174,9 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size*nbanks-1).width
+    awidth = 1 if awidth == 0
     awidth_b = (size-1).width # Bank width
+    awidth_b = 1 if awidth_b == 0
     # Ensures br_srts is a hash.
     br_rsts = br_rsts.to_hash
 
@@ -1204,7 +1337,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                         blk.call if blk
                     end
                     # Prepare the read.
-                    abus_r <= abus_r + 1
+                    # abus_r <= abus_r + 1
+                    if 2**size.width != size then
+                        abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                    else
+                        abus_r <= abus_r + 1
+                    end
                     trig_r <= 1
                 end
             end
@@ -1240,7 +1378,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -1281,7 +1424,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                         blk.call if blk
                     end
                     # Prepare the read.
-                    abus_r <= abus_r - 1
+                    # abus_r <= abus_r - 1
+                    if 2**size.width != size then
+                        abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                    else
+                        abus_r <= abus_r - 1
+                    end
                     trig_r <= 1
                 end
             end
@@ -1318,6 +1466,11 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the write.
                     abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.6"
+  VERSION = "2.4.12"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.6
+  version: 2.4.12
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-10-07 00:00:00.000000000 Z
+date: 2020-10-30 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -84,11 +84,13 @@ files:
 - lib/HDLRuby/hdr_samples/include.rb
 - lib/HDLRuby/hdr_samples/instance_open.rb
 - lib/HDLRuby/hdr_samples/linear_test.rb
+- lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb
 - lib/HDLRuby/hdr_samples/mei8.rb
 - lib/HDLRuby/hdr_samples/mei8_bench.rb
 - lib/HDLRuby/hdr_samples/memory_test.rb
 - lib/HDLRuby/hdr_samples/multer_gen.rb
 - lib/HDLRuby/hdr_samples/multer_seq.rb
+- lib/HDLRuby/hdr_samples/neg_arith_bench.rb
 - lib/HDLRuby/hdr_samples/neural/a.rb
 - lib/HDLRuby/hdr_samples/neural/a_sub.rb
 - lib/HDLRuby/hdr_samples/neural/bw.rb
@@ -124,6 +126,7 @@ files:
 - lib/HDLRuby/hdr_samples/with_linear.rb
 - lib/HDLRuby/hdr_samples/with_loop.rb
 - lib/HDLRuby/hdr_samples/with_memory.rb
+- lib/HDLRuby/hdr_samples/with_memory_rom.rb
 - lib/HDLRuby/hdr_samples/with_multi_channels.rb
 - lib/HDLRuby/hdr_samples/with_reconf.rb
 - lib/HDLRuby/hdrcc.rb