HDLRuby 2.4.29 → 2.5.0

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@@ -126,7 +126,12 @@ class Block
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  # of each line.
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  def to_verilog(spc = 3)
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  code = "begin"
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- code << " : #{name_to_verilog(self.name)}" if self.name && !self.name.empty?
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+ # code << " : #{name_to_verilog(self.name)}" if self.name && !self.name.empty?
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+ if self.name && !self.name.empty? then
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+ vname = name_to_verilog(self.name)
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+ code << " : #{vname}"
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+ self.properties[:verilog_name] = vname
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+ end
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  code << "\n" if block.each_inner.any?
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  # Declaration of "inner" part within "always".
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  block.each_inner do |inner|
@@ -1384,8 +1389,10 @@ end
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  class RefName
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  # Converts the system to Verilog code using +renamer+ for producing Verilog-compatible names.
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  def to_verilog
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- # return "#{self.name.to_s}"
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- return "#{name_to_verilog(self.name)}"
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+ # return "#{name_to_verilog(self.name)}"
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+ vname = name_to_verilog(self.name)
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+ self.properties[:verilog_name] = vname
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+ return "#{vname}"
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  end
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  # Used for instantiation (emergency procedure).
@@ -1750,7 +1757,10 @@ class SignalI
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  # Converts the system to Verilog code.
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  def to_verilog
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  # Convert unusable characters and return them.
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- return "#{name_to_verilog(self.name)}"
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+ # return "#{name_to_verilog(self.name)}"
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+ vname = name_to_verilog(self.name)
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+ self.properties[:verilog_name] = vname
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+ return "#{vname}"
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  end
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  end
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@@ -1932,8 +1942,14 @@ class SystemT
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  # Spelling necessary for simulation.
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  code = "`timescale 1ps/1ps\n\n"
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+
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+ # # Output the module name.
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+ # code << "module #{name_to_verilog(self.name)}("
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+
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+ vname = name_to_verilog(self.name)
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+ self.properties[:verilog_name] = vname
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  # Output the module name.
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- code << "module #{name_to_verilog(self.name)}("
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+ code << "module #{vname}("
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  # Output the last two to the input.
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  inputs[0..-2].each do |input|
@@ -2110,7 +2126,10 @@ class SystemT
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  code << " " * 3
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  systemT = systemI.systemT
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  code << name_to_verilog(systemT.name) << " "
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- code << name_to_verilog(systemI.name) << "("
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+ # code << name_to_verilog(systemI.name) << "("
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+ vname = name_to_verilog(systemI.name)
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+ systemI.properties[:verilog_name] = vname
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+ code << vname << "("
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  # Its ports connections
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  # Inputs
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  systemT.each_input do |input|
@@ -0,0 +1,61 @@
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+ require 'strscan'
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+
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+ ##
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+ # Tool for expanding template files.
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+ #
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+ # Used for generating files like confugaration file for given HW target
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+ #
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+ ########################################################################
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+
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+
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+ class TemplateExpander
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+
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+ ## Describes an expansion rule.
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+ Rule = Struct.new(:match,:action)
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+
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+ # Creates a new template expander with potential list of +rules+.
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+ def initialize(rules= [])
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+ # Setup the rules.
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+ @rules = rules.map do |match,action|
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+ # Ensures action is a proc.
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+ action = proc { |str| action.to_s } unless action.is_a?(Proc)
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+ # Create the rule.
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+ Rule.new(Regexp.new(match), action)
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+ end
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+ # The skip regexp is empty, it has to be built with finalize.
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+ @skip = nil
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+ end
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+
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+ # Adds a +rule+.
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+ def add_rule(*rule)
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+ @rules << Rule.new(Regexp.new(rule[0]), rule[1])
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+ end
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+
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+ # Finalize the expander by building the default rule.
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+ def finalize
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+ # @skip = Regexp.union(*@rules.map { |rule| rule.match })
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+ @skip = /(?=#{Regexp.union(*@rules.map { |rule| rule.match }).source})|\z/
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+ end
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+
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+ # Apply the expander to +str+ and put the result in +res+.
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+ def expand(str,res = "")
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+ # Ensure the default rule is properly set up.
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+ self.finalize
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+ # Scan the string with each rule.
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+ scanner = StringScanner.new(str)
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+ until scanner.eos? do
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+ @rules.find do |rule|
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+ scanned = scanner.scan(rule.match)
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+ if scanned then
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+ res << rule.action.call(scanned)
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+ else
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+ false
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+ end
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+ end
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+ res << scanner.scan_until(@skip)
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+ end
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+ return res
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+ end
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+
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+
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+ end
@@ -1,3 +1,3 @@
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  module HDLRuby
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- VERSION = "2.4.29"
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+ VERSION = "2.5.0"
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  end
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: HDLRuby
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  version: !ruby/object:Gem::Version
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- version: 2.4.29
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+ version: 2.5.0
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  platform: ruby
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  authors:
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  - Lovic Gauthier
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  autorequire:
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  bindir: exe
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  cert_chain: []
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- date: 2021-02-06 00:00:00.000000000 Z
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+ date: 2021-03-15 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: bundler
@@ -66,6 +66,8 @@ files:
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  - lib/HDLRuby/alcc.rb
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  - lib/HDLRuby/backend/hruby_allocator.rb
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  - lib/HDLRuby/backend/hruby_c_allocator.rb
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+ - lib/HDLRuby/drivers/xcd.rb
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+ - lib/HDLRuby/drivers/xcd/dummy.xcd
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  - lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v
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  - lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_213.v
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  - lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v
@@ -85,6 +87,7 @@ files:
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  - lib/HDLRuby/hdr_samples/dff.rb
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  - lib/HDLRuby/hdr_samples/dff_bench.rb
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  - lib/HDLRuby/hdr_samples/dff_counter.rb
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+ - lib/HDLRuby/hdr_samples/dff_properties.rb
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  - lib/HDLRuby/hdr_samples/include.rb
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  - lib/HDLRuby/hdr_samples/instance_open.rb
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  - lib/HDLRuby/hdr_samples/linear_test.rb
@@ -199,6 +202,7 @@ files:
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  - lib/HDLRuby/hruby_bstr.rb
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  - lib/HDLRuby/hruby_check.rb
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  - lib/HDLRuby/hruby_db.rb
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+ - lib/HDLRuby/hruby_decorator.rb
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  - lib/HDLRuby/hruby_error.rb
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  - lib/HDLRuby/hruby_high.rb
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  - lib/HDLRuby/hruby_low.rb
@@ -293,6 +297,7 @@ files:
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  - lib/HDLRuby/std/pipeline.rb
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  - lib/HDLRuby/std/reconf.rb
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  - lib/HDLRuby/std/task.rb
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+ - lib/HDLRuby/template_expander.rb
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  - lib/HDLRuby/test_hruby_bstr.rb
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  - lib/HDLRuby/test_hruby_high.rb
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  - lib/HDLRuby/test_hruby_high_low.rb