HDLRuby 2.4.29 → 2.5.0
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- checksums.yaml +4 -4
- data/lib/HDLRuby/drivers/xcd.rb +79 -0
- data/lib/HDLRuby/drivers/xcd/dummy.xcd +4 -0
- data/lib/HDLRuby/hdr_samples/dff_properties.rb +19 -0
- data/lib/HDLRuby/hdrcc.rb +31 -3
- data/lib/HDLRuby/hruby_decorator.rb +248 -0
- data/lib/HDLRuby/hruby_high.rb +255 -66
- data/lib/HDLRuby/hruby_low.rb +511 -0
- data/lib/HDLRuby/hruby_verilog.rb +25 -6
- data/lib/HDLRuby/template_expander.rb +61 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +7 -2
@@ -126,7 +126,12 @@ class Block
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126
126
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# of each line.
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127
127
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def to_verilog(spc = 3)
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128
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code = "begin"
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129
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-
code << " : #{name_to_verilog(self.name)}" if self.name && !self.name.empty?
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129
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+
# code << " : #{name_to_verilog(self.name)}" if self.name && !self.name.empty?
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130
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+
if self.name && !self.name.empty? then
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131
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vname = name_to_verilog(self.name)
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code << " : #{vname}"
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133
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self.properties[:verilog_name] = vname
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end
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code << "\n" if block.each_inner.any?
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136
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# Declaration of "inner" part within "always".
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block.each_inner do |inner|
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@@ -1384,8 +1389,10 @@ end
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1384
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class RefName
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1385
1390
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# Converts the system to Verilog code using +renamer+ for producing Verilog-compatible names.
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def to_verilog
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1387
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-
# return "#{self.name
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1388
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-
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1392
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+
# return "#{name_to_verilog(self.name)}"
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1393
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vname = name_to_verilog(self.name)
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1394
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self.properties[:verilog_name] = vname
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1395
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return "#{vname}"
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end
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# Used for instantiation (emergency procedure).
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@@ -1750,7 +1757,10 @@ class SignalI
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1750
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# Converts the system to Verilog code.
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1751
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def to_verilog
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1752
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# Convert unusable characters and return them.
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1753
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-
return "#{name_to_verilog(self.name)}"
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1760
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+
# return "#{name_to_verilog(self.name)}"
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1761
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+
vname = name_to_verilog(self.name)
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1762
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self.properties[:verilog_name] = vname
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1763
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return "#{vname}"
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1754
1764
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end
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end
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@@ -1932,8 +1942,14 @@ class SystemT
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1932
1942
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1933
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# Spelling necessary for simulation.
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1934
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code = "`timescale 1ps/1ps\n\n"
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1945
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+
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1946
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+
# # Output the module name.
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1947
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+
# code << "module #{name_to_verilog(self.name)}("
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1948
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+
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1949
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vname = name_to_verilog(self.name)
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1950
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+
self.properties[:verilog_name] = vname
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# Output the module name.
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1936
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-
code << "module #{
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1952
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+
code << "module #{vname}("
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1937
1953
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# Output the last two to the input.
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inputs[0..-2].each do |input|
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@@ -2110,7 +2126,10 @@ class SystemT
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2110
2126
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code << " " * 3
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2127
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systemT = systemI.systemT
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2112
2128
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code << name_to_verilog(systemT.name) << " "
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2113
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-
code << name_to_verilog(systemI.name) << "("
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2129
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+
# code << name_to_verilog(systemI.name) << "("
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2130
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+
vname = name_to_verilog(systemI.name)
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2131
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+
systemI.properties[:verilog_name] = vname
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2132
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code << vname << "("
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2114
2133
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# Its ports connections
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2115
2134
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# Inputs
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2116
2135
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systemT.each_input do |input|
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@@ -0,0 +1,61 @@
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1
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+
require 'strscan'
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2
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+
|
3
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+
##
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4
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# Tool for expanding template files.
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5
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#
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6
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# Used for generating files like confugaration file for given HW target
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7
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#
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8
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########################################################################
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9
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+
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10
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+
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11
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+
class TemplateExpander
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12
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+
|
13
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## Describes an expansion rule.
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14
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+
Rule = Struct.new(:match,:action)
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15
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+
|
16
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+
# Creates a new template expander with potential list of +rules+.
|
17
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+
def initialize(rules= [])
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18
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# Setup the rules.
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19
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@rules = rules.map do |match,action|
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20
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# Ensures action is a proc.
|
21
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action = proc { |str| action.to_s } unless action.is_a?(Proc)
|
22
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# Create the rule.
|
23
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Rule.new(Regexp.new(match), action)
|
24
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end
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25
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# The skip regexp is empty, it has to be built with finalize.
|
26
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@skip = nil
|
27
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+
end
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28
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+
|
29
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# Adds a +rule+.
|
30
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+
def add_rule(*rule)
|
31
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@rules << Rule.new(Regexp.new(rule[0]), rule[1])
|
32
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+
end
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33
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+
|
34
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+
# Finalize the expander by building the default rule.
|
35
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+
def finalize
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36
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# @skip = Regexp.union(*@rules.map { |rule| rule.match })
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37
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+
@skip = /(?=#{Regexp.union(*@rules.map { |rule| rule.match }).source})|\z/
|
38
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+
end
|
39
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+
|
40
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+
# Apply the expander to +str+ and put the result in +res+.
|
41
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def expand(str,res = "")
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42
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+
# Ensure the default rule is properly set up.
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43
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self.finalize
|
44
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# Scan the string with each rule.
|
45
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+
scanner = StringScanner.new(str)
|
46
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+
until scanner.eos? do
|
47
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@rules.find do |rule|
|
48
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scanned = scanner.scan(rule.match)
|
49
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+
if scanned then
|
50
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res << rule.action.call(scanned)
|
51
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else
|
52
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false
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53
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end
|
54
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end
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55
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res << scanner.scan_until(@skip)
|
56
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end
|
57
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return res
|
58
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end
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59
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+
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60
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+
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61
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end
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data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
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2
2
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name: HDLRuby
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3
3
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version: !ruby/object:Gem::Version
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4
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-
version: 2.
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4
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+
version: 2.5.0
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5
5
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platform: ruby
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6
6
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authors:
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7
7
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- Lovic Gauthier
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8
8
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autorequire:
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9
9
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bindir: exe
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10
10
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cert_chain: []
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11
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-
date: 2021-
|
11
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+
date: 2021-03-15 00:00:00.000000000 Z
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12
12
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dependencies:
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13
13
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- !ruby/object:Gem::Dependency
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14
14
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name: bundler
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@@ -66,6 +66,8 @@ files:
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66
66
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- lib/HDLRuby/alcc.rb
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67
67
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- lib/HDLRuby/backend/hruby_allocator.rb
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68
68
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- lib/HDLRuby/backend/hruby_c_allocator.rb
|
69
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+
- lib/HDLRuby/drivers/xcd.rb
|
70
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+
- lib/HDLRuby/drivers/xcd/dummy.xcd
|
69
71
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- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v
|
70
72
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- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_213.v
|
71
73
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- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v
|
@@ -85,6 +87,7 @@ files:
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85
87
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- lib/HDLRuby/hdr_samples/dff.rb
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86
88
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- lib/HDLRuby/hdr_samples/dff_bench.rb
|
87
89
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- lib/HDLRuby/hdr_samples/dff_counter.rb
|
90
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+
- lib/HDLRuby/hdr_samples/dff_properties.rb
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88
91
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- lib/HDLRuby/hdr_samples/include.rb
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89
92
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- lib/HDLRuby/hdr_samples/instance_open.rb
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90
93
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- lib/HDLRuby/hdr_samples/linear_test.rb
|
@@ -199,6 +202,7 @@ files:
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199
202
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- lib/HDLRuby/hruby_bstr.rb
|
200
203
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- lib/HDLRuby/hruby_check.rb
|
201
204
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- lib/HDLRuby/hruby_db.rb
|
205
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+
- lib/HDLRuby/hruby_decorator.rb
|
202
206
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- lib/HDLRuby/hruby_error.rb
|
203
207
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- lib/HDLRuby/hruby_high.rb
|
204
208
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- lib/HDLRuby/hruby_low.rb
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@@ -293,6 +297,7 @@ files:
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293
297
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- lib/HDLRuby/std/pipeline.rb
|
294
298
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- lib/HDLRuby/std/reconf.rb
|
295
299
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- lib/HDLRuby/std/task.rb
|
300
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+
- lib/HDLRuby/template_expander.rb
|
296
301
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- lib/HDLRuby/test_hruby_bstr.rb
|
297
302
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- lib/HDLRuby/test_hruby_high.rb
|
298
303
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- lib/HDLRuby/test_hruby_high_low.rb
|