HDLRuby 2.4.29 → 2.5.0

Sign up to get free protection for your applications and to get access to all the features.
@@ -126,7 +126,12 @@ class Block
126
126
  # of each line.
127
127
  def to_verilog(spc = 3)
128
128
  code = "begin"
129
- code << " : #{name_to_verilog(self.name)}" if self.name && !self.name.empty?
129
+ # code << " : #{name_to_verilog(self.name)}" if self.name && !self.name.empty?
130
+ if self.name && !self.name.empty? then
131
+ vname = name_to_verilog(self.name)
132
+ code << " : #{vname}"
133
+ self.properties[:verilog_name] = vname
134
+ end
130
135
  code << "\n" if block.each_inner.any?
131
136
  # Declaration of "inner" part within "always".
132
137
  block.each_inner do |inner|
@@ -1384,8 +1389,10 @@ end
1384
1389
  class RefName
1385
1390
  # Converts the system to Verilog code using +renamer+ for producing Verilog-compatible names.
1386
1391
  def to_verilog
1387
- # return "#{self.name.to_s}"
1388
- return "#{name_to_verilog(self.name)}"
1392
+ # return "#{name_to_verilog(self.name)}"
1393
+ vname = name_to_verilog(self.name)
1394
+ self.properties[:verilog_name] = vname
1395
+ return "#{vname}"
1389
1396
  end
1390
1397
 
1391
1398
  # Used for instantiation (emergency procedure).
@@ -1750,7 +1757,10 @@ class SignalI
1750
1757
  # Converts the system to Verilog code.
1751
1758
  def to_verilog
1752
1759
  # Convert unusable characters and return them.
1753
- return "#{name_to_verilog(self.name)}"
1760
+ # return "#{name_to_verilog(self.name)}"
1761
+ vname = name_to_verilog(self.name)
1762
+ self.properties[:verilog_name] = vname
1763
+ return "#{vname}"
1754
1764
  end
1755
1765
  end
1756
1766
 
@@ -1932,8 +1942,14 @@ class SystemT
1932
1942
 
1933
1943
  # Spelling necessary for simulation.
1934
1944
  code = "`timescale 1ps/1ps\n\n"
1945
+
1946
+ # # Output the module name.
1947
+ # code << "module #{name_to_verilog(self.name)}("
1948
+
1949
+ vname = name_to_verilog(self.name)
1950
+ self.properties[:verilog_name] = vname
1935
1951
  # Output the module name.
1936
- code << "module #{name_to_verilog(self.name)}("
1952
+ code << "module #{vname}("
1937
1953
 
1938
1954
  # Output the last two to the input.
1939
1955
  inputs[0..-2].each do |input|
@@ -2110,7 +2126,10 @@ class SystemT
2110
2126
  code << " " * 3
2111
2127
  systemT = systemI.systemT
2112
2128
  code << name_to_verilog(systemT.name) << " "
2113
- code << name_to_verilog(systemI.name) << "("
2129
+ # code << name_to_verilog(systemI.name) << "("
2130
+ vname = name_to_verilog(systemI.name)
2131
+ systemI.properties[:verilog_name] = vname
2132
+ code << vname << "("
2114
2133
  # Its ports connections
2115
2134
  # Inputs
2116
2135
  systemT.each_input do |input|
@@ -0,0 +1,61 @@
1
+ require 'strscan'
2
+
3
+ ##
4
+ # Tool for expanding template files.
5
+ #
6
+ # Used for generating files like confugaration file for given HW target
7
+ #
8
+ ########################################################################
9
+
10
+
11
+ class TemplateExpander
12
+
13
+ ## Describes an expansion rule.
14
+ Rule = Struct.new(:match,:action)
15
+
16
+ # Creates a new template expander with potential list of +rules+.
17
+ def initialize(rules= [])
18
+ # Setup the rules.
19
+ @rules = rules.map do |match,action|
20
+ # Ensures action is a proc.
21
+ action = proc { |str| action.to_s } unless action.is_a?(Proc)
22
+ # Create the rule.
23
+ Rule.new(Regexp.new(match), action)
24
+ end
25
+ # The skip regexp is empty, it has to be built with finalize.
26
+ @skip = nil
27
+ end
28
+
29
+ # Adds a +rule+.
30
+ def add_rule(*rule)
31
+ @rules << Rule.new(Regexp.new(rule[0]), rule[1])
32
+ end
33
+
34
+ # Finalize the expander by building the default rule.
35
+ def finalize
36
+ # @skip = Regexp.union(*@rules.map { |rule| rule.match })
37
+ @skip = /(?=#{Regexp.union(*@rules.map { |rule| rule.match }).source})|\z/
38
+ end
39
+
40
+ # Apply the expander to +str+ and put the result in +res+.
41
+ def expand(str,res = "")
42
+ # Ensure the default rule is properly set up.
43
+ self.finalize
44
+ # Scan the string with each rule.
45
+ scanner = StringScanner.new(str)
46
+ until scanner.eos? do
47
+ @rules.find do |rule|
48
+ scanned = scanner.scan(rule.match)
49
+ if scanned then
50
+ res << rule.action.call(scanned)
51
+ else
52
+ false
53
+ end
54
+ end
55
+ res << scanner.scan_until(@skip)
56
+ end
57
+ return res
58
+ end
59
+
60
+
61
+ end
@@ -1,3 +1,3 @@
1
1
  module HDLRuby
2
- VERSION = "2.4.29"
2
+ VERSION = "2.5.0"
3
3
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: HDLRuby
3
3
  version: !ruby/object:Gem::Version
4
- version: 2.4.29
4
+ version: 2.5.0
5
5
  platform: ruby
6
6
  authors:
7
7
  - Lovic Gauthier
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2021-02-06 00:00:00.000000000 Z
11
+ date: 2021-03-15 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler
@@ -66,6 +66,8 @@ files:
66
66
  - lib/HDLRuby/alcc.rb
67
67
  - lib/HDLRuby/backend/hruby_allocator.rb
68
68
  - lib/HDLRuby/backend/hruby_c_allocator.rb
69
+ - lib/HDLRuby/drivers/xcd.rb
70
+ - lib/HDLRuby/drivers/xcd/dummy.xcd
69
71
  - lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v
70
72
  - lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_213.v
71
73
  - lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v
@@ -85,6 +87,7 @@ files:
85
87
  - lib/HDLRuby/hdr_samples/dff.rb
86
88
  - lib/HDLRuby/hdr_samples/dff_bench.rb
87
89
  - lib/HDLRuby/hdr_samples/dff_counter.rb
90
+ - lib/HDLRuby/hdr_samples/dff_properties.rb
88
91
  - lib/HDLRuby/hdr_samples/include.rb
89
92
  - lib/HDLRuby/hdr_samples/instance_open.rb
90
93
  - lib/HDLRuby/hdr_samples/linear_test.rb
@@ -199,6 +202,7 @@ files:
199
202
  - lib/HDLRuby/hruby_bstr.rb
200
203
  - lib/HDLRuby/hruby_check.rb
201
204
  - lib/HDLRuby/hruby_db.rb
205
+ - lib/HDLRuby/hruby_decorator.rb
202
206
  - lib/HDLRuby/hruby_error.rb
203
207
  - lib/HDLRuby/hruby_high.rb
204
208
  - lib/HDLRuby/hruby_low.rb
@@ -293,6 +297,7 @@ files:
293
297
  - lib/HDLRuby/std/pipeline.rb
294
298
  - lib/HDLRuby/std/reconf.rb
295
299
  - lib/HDLRuby/std/task.rb
300
+ - lib/HDLRuby/template_expander.rb
296
301
  - lib/HDLRuby/test_hruby_bstr.rb
297
302
  - lib/HDLRuby/test_hruby_high.rb
298
303
  - lib/HDLRuby/test_hruby_high_low.rb