HDLRuby 2.4.21 → 2.4.22

checksums.yaml

@@ -1,7 +1,7 @@
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data/lib/HDLRuby/hdr_samples/rom.rb

@@ -1,12 +1,14 @@
 
+signed[7..0].typedef(:typ)
+
 # Describes an 8-bit data 4-bit address ROM.
 system :rom4_8 do
     [2..0].input :addr
     [7..0].output :data0,:data1,:data2
 
     bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
-    bit[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
-    bit[7..0][-8].constant content2: (8).times.to_a
+    signed[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
+    typ[-8].constant content2: (8).times.to_a
 
     data0 <= content0[addr]
     data1 <= content1[addr]

data/lib/HDLRuby/hruby_low.rb

@@ -1183,6 +1183,11 @@ module HDLRuby::Low
             return false
         end
 
+        # Tells if the type of of vector kind.
+        def vector?
+            return false
+        end
+
         # Gets the bitwidth of the type, by default 0.
         # Bit, signed, unsigned and Float base have a width of 1.
         def width
@@ -1410,7 +1415,7 @@ module HDLRuby::Low
 
             # Sets the delegations
             self.extend Forwardable
-            [ :signed?, :unsigned?, :fixed?, :float?, :leaf?,
+            [ :signed?, :unsigned?, :fixed?, :float?, :leaf?, :vector?,
               :width, :range?, :range, :base?, :base, :types?,
               :get_all_types, :get_type, :each, :each_type, 
               :regular?,
@@ -1466,6 +1471,11 @@ module HDLRuby::Low
         # The base type of the vector
         attr_reader :base
 
+        # Tells if the type of of vector kind.
+        def vector?
+            return true
+        end
+
         # Tells if the type has a base.
         def base?
             return true

data/lib/HDLRuby/hruby_verilog.rb

@@ -11,6 +11,10 @@ include HDLRuby::Verilog
 module HDLRuby::Low
 
 
+    # The list of base types used both in verilog and HDLRuby
+    VERILOG_BASE_TYPES = ["signed"]
+
+
 # Sample of very handy for programming.
 # puts "class=#{self.yes.class}"       # Confirm class of self.yes.
 # puts "methods=#{self.right.methods}" # Confirm method of self.right.
@@ -1349,7 +1353,8 @@ end
 class TypeVector
     # Converts the system to Verilog code.
     def to_verilog
-        if self.base.name.to_s != "bit"
+        # if self.base.name.to_s != "bit"
+        if VERILOG_BASE_TYPES.include?(self.base.name.to_s)
             return " #{self.base.name.to_s}[#{self.range.first}:#{self.range.last}]"
         end
         return " [#{self.range.first}:#{self.range.last}]"
@@ -1750,10 +1755,12 @@ class SystemT
         end
         # And the array types signals.
         self.each_signal do |sig|
-            regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
         end
         self.each_inner do |sig|
-            regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
         end
 
         # Code generation

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.21"
+  VERSION = "2.4.22"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.21
+  version: 2.4.22
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-12-10 00:00:00.000000000 Z
+date: 2021-01-01 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler