HDLRuby 2.4.20 → 2.4.27
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- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/rom.rb +4 -2
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +8 -4
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +1 -0
- data/lib/HDLRuby/hdrcc.rb +2 -0
- data/lib/HDLRuby/hruby_low.rb +11 -1
- data/lib/HDLRuby/hruby_low_casts_without_expression.rb +326 -0
- data/lib/HDLRuby/hruby_verilog.rb +82 -12
- data/lib/HDLRuby/std/channel.rb +59 -18
- data/lib/HDLRuby/std/connector.rb +1 -1
- data/lib/HDLRuby/std/linear.rb +0 -5
- data/lib/HDLRuby/std/memory.rb +73 -20
- data/lib/HDLRuby/version.rb +1 -1
- metadata +3 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 68d4b96d98a37f1398d44249498d5bb82e977776d5f3e28a930de98ed8ab5ece
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4
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data.tar.gz: 6a7c8b57cf47d42f541b04c34765c5b05e08d93a64eaa66e1ca2048b461682a5
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SHA512:
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metadata.gz:
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data.tar.gz:
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6
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metadata.gz: 8c5fd477685906abd21772655ccd1e9c40efdb4069bae0ffbadc9206dc0ea2df2110e983ae08875feec18c1d8e26937e8574aa596c07b946ec9e6ed1ed83714e
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7
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+
data.tar.gz: 6a7fd8f88a307d13d100a63fc774ac70452dae9fc444642ceb038dd3b50ad98eb0318b422412dc4efc77ae858d29ff58c0e66b0c5179806cb0b16854b9ff1cef
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@@ -1,12 +1,14 @@
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2
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+
signed[7..0].typedef(:typ)
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3
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+
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4
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# Describes an 8-bit data 4-bit address ROM.
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3
5
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system :rom4_8 do
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4
6
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[2..0].input :addr
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5
7
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[7..0].output :data0,:data1,:data2
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6
8
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7
9
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bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
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8
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-
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9
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-
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10
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+
signed[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
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11
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+
typ[-8].constant content2: (8).times.to_a
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10
12
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|
11
13
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data0 <= content0[addr]
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12
14
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data1 <= content1[addr]
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@@ -40,10 +40,14 @@ system :channel_connector do
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40
40
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41
41
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serializer(typ,clk.negedge,[reader_inputs_x,reader_inputs_h],writer_inputs_serializer)
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42
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43
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-
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-
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-
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-
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+
mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_r) # 入力値を格納するrom(x)
|
44
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+
mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_duplicator0) #
|
45
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+
mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_duplicator1) #
|
46
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+
reader_inputs_r = rom_inputs_r.branch(:rinc)
|
47
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+
writer_duplicator0 = ram_duplicator0.branch(:winc)
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48
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+
writer_duplicator1 = ram_duplicator1.branch(:winc)
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49
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+
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50
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+
duplicator(typ,clk.posedge,reader_inputs_r,[writer_duplicator0, writer_duplicator1])
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timed do
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# リセット
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data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -19,6 +19,7 @@ require 'HDLRuby/hruby_low_with_port'
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19
19
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require 'HDLRuby/hruby_low_with_var'
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20
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require 'HDLRuby/hruby_low_without_concat'
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21
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require 'HDLRuby/hruby_low_without_connection'
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22
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+
require 'HDLRuby/hruby_low_casts_without_expression'
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require 'HDLRuby/hruby_low_cleanup'
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24
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25
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require 'HDLRuby/hruby_verilog.rb'
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@@ -577,6 +578,7 @@ elsif $options[:verilog] then
|
|
577
578
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# top_system = $top_system
|
578
579
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# Make description compatible with verilog generation.
|
579
580
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$top_system.each_systemT_deep do |systemT|
|
581
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+
systemT.casts_without_expression!
|
580
582
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systemT.to_upper_space!
|
581
583
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systemT.to_global_systemTs!
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582
584
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# systemT.break_types!
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data/lib/HDLRuby/hruby_low.rb
CHANGED
@@ -1183,6 +1183,11 @@ module HDLRuby::Low
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1183
1183
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return false
|
1184
1184
|
end
|
1185
1185
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|
1186
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+
# Tells if the type of of vector kind.
|
1187
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+
def vector?
|
1188
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+
return false
|
1189
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+
end
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1190
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+
|
1186
1191
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# Gets the bitwidth of the type, by default 0.
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1187
1192
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# Bit, signed, unsigned and Float base have a width of 1.
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1188
1193
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def width
|
@@ -1410,7 +1415,7 @@ module HDLRuby::Low
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1410
1415
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|
1411
1416
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# Sets the delegations
|
1412
1417
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self.extend Forwardable
|
1413
|
-
[ :signed?, :unsigned?, :fixed?, :float?, :leaf?,
|
1418
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+
[ :signed?, :unsigned?, :fixed?, :float?, :leaf?, :vector?,
|
1414
1419
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:width, :range?, :range, :base?, :base, :types?,
|
1415
1420
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:get_all_types, :get_type, :each, :each_type,
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1416
1421
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:regular?,
|
@@ -1466,6 +1471,11 @@ module HDLRuby::Low
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|
1466
1471
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# The base type of the vector
|
1467
1472
|
attr_reader :base
|
1468
1473
|
|
1474
|
+
# Tells if the type of of vector kind.
|
1475
|
+
def vector?
|
1476
|
+
return true
|
1477
|
+
end
|
1478
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+
|
1469
1479
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# Tells if the type has a base.
|
1470
1480
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def base?
|
1471
1481
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return true
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@@ -0,0 +1,326 @@
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1
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+
require 'HDLRuby'
|
2
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+
require 'HDLRuby/hruby_tools'
|
3
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require 'HDLRuby/hruby_low_mutable'
|
4
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require 'HDLRuby/hruby_low_with_bool'
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5
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+
|
6
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+
|
7
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module HDLRuby::Low
|
8
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+
|
9
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|
10
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##
|
11
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# Replace expressions in cast operators with variables.
|
12
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+
# Use for generating Verilog code generation since bit extension cannot
|
13
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+
# be performed on expression but only on signals.
|
14
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+
#
|
15
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+
########################################################################
|
16
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+
|
17
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+
|
18
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## Extends the SystemT class with functionality for extracting
|
19
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+
# expressions from cast.
|
20
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+
class SystemT
|
21
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+
|
22
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+
# Extracts the expressions from the casts.
|
23
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+
def casts_without_expression!
|
24
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+
self.scope.casts_without_expression!
|
25
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+
return self
|
26
|
+
end
|
27
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+
|
28
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+
end
|
29
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+
|
30
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+
|
31
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+
## Extends the Scope class with functionality for extracting
|
32
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+
# expressions from cast.
|
33
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+
class Scope
|
34
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+
|
35
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+
# Extracts the expressions from the casts.
|
36
|
+
def casts_without_expression!
|
37
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+
# Recurse on the sub scopes.
|
38
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+
self.each_scope(&:casts_without_expression!)
|
39
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+
|
40
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+
# Apply on the connections.
|
41
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+
self.each_connection(&:casts_without_expression!)
|
42
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+
|
43
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+
# Apply on the behaviors.
|
44
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+
self.each_behavior do |behavior|
|
45
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+
behavior.block.casts_without_expression!
|
46
|
+
end
|
47
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+
return self
|
48
|
+
end
|
49
|
+
end
|
50
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+
|
51
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+
|
52
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+
## Extends the Transmit class with functionality for extracting
|
53
|
+
# expressions from cast.
|
54
|
+
class Transmit
|
55
|
+
|
56
|
+
# Extracts the expressions from the casts.
|
57
|
+
def casts_without_expression!
|
58
|
+
# Apply on the left value.
|
59
|
+
self.set_left!(self.left.casts_without_expression)
|
60
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+
# Apply on the right value.
|
61
|
+
self.set_right!(self.right.casts_without_expression)
|
62
|
+
return self
|
63
|
+
end
|
64
|
+
end
|
65
|
+
|
66
|
+
## Extends the If class with functionality for extracting
|
67
|
+
# expressions from cast.
|
68
|
+
class If
|
69
|
+
|
70
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+
# Extracts the expressions from the casts.
|
71
|
+
def casts_without_expression!
|
72
|
+
# Apply on the condition.
|
73
|
+
self.set_condition!(self.condition.casts_without_expression)
|
74
|
+
# Apply on the yes.
|
75
|
+
self.yes.casts_without_expression!
|
76
|
+
# Apply on the noifs.
|
77
|
+
@noifs.map! do |cond,stmnt|
|
78
|
+
[cond.casts_without_expression,stmnt.casts_without_expression!]
|
79
|
+
end
|
80
|
+
# Apply on the no if any.
|
81
|
+
self.no.casts_without_expression! if self.no
|
82
|
+
return self
|
83
|
+
end
|
84
|
+
end
|
85
|
+
|
86
|
+
## Extends the When class with functionality for extracting
|
87
|
+
# expressions from cast.
|
88
|
+
class When
|
89
|
+
|
90
|
+
# Extracts the expressions from the casts.
|
91
|
+
def casts_without_expression!
|
92
|
+
# Apply on the match.
|
93
|
+
self.set_match!(self.match.casts_without_expression)
|
94
|
+
# Apply on the statement.
|
95
|
+
self.statement.casts_without_expression!
|
96
|
+
return self
|
97
|
+
end
|
98
|
+
end
|
99
|
+
|
100
|
+
|
101
|
+
## Extends the Case class with functionality for extracting
|
102
|
+
# expressions from cast.
|
103
|
+
class Case
|
104
|
+
|
105
|
+
# Extracts the expressions from the casts.
|
106
|
+
def casts_without_expression!
|
107
|
+
# No need to apply on the value!
|
108
|
+
# Apply on the value.
|
109
|
+
self.set_value!(self.value.casts_without_expression)
|
110
|
+
# Apply on the whens.
|
111
|
+
self.each_when(&:casts_without_expression!)
|
112
|
+
# Apply on the default if any.
|
113
|
+
self.default.casts_without_expression! if self.default
|
114
|
+
return self
|
115
|
+
end
|
116
|
+
end
|
117
|
+
|
118
|
+
|
119
|
+
## Extends the TimeWait class with functionality for extracting
|
120
|
+
# expressions from cast.
|
121
|
+
class TimeWait
|
122
|
+
# Extracts the expressions from the casts.
|
123
|
+
def casts_without_expression!
|
124
|
+
# Nothing to do.
|
125
|
+
return self
|
126
|
+
end
|
127
|
+
end
|
128
|
+
|
129
|
+
## Extends the TimeRepeat class with functionality for extracting
|
130
|
+
# expressions from cast.
|
131
|
+
class TimeRepeat
|
132
|
+
# Extracts the expressions from the casts.
|
133
|
+
def casts_without_expression!
|
134
|
+
# Simply recurse on the stamtement.
|
135
|
+
self.statement.casts_without_expression!
|
136
|
+
return self
|
137
|
+
end
|
138
|
+
end
|
139
|
+
|
140
|
+
|
141
|
+
## Extends the Block class with functionality for extracting
|
142
|
+
# expressions from cast.
|
143
|
+
class Block
|
144
|
+
|
145
|
+
# Extracts the expressions from the casts.
|
146
|
+
def casts_without_expression!
|
147
|
+
# Apply on each statement.
|
148
|
+
self.each_statement(&:casts_without_expression!)
|
149
|
+
return self
|
150
|
+
end
|
151
|
+
end
|
152
|
+
|
153
|
+
|
154
|
+
## Extends the Value class with functionality for extracting
|
155
|
+
# expressions from cast.
|
156
|
+
class Value
|
157
|
+
# Extracts the expressions from the casts.
|
158
|
+
def casts_without_expression
|
159
|
+
# Simple clones.
|
160
|
+
return self.clone
|
161
|
+
end
|
162
|
+
end
|
163
|
+
|
164
|
+
|
165
|
+
## Extends the Cast class with functionality for extracting
|
166
|
+
# expressions from cast.
|
167
|
+
class Cast
|
168
|
+
# Extracts the expressions from the casts.
|
169
|
+
def casts_without_expression
|
170
|
+
# Recurse on the child.
|
171
|
+
nchild = self.child.casts_without_expression
|
172
|
+
# Process the cast.
|
173
|
+
unless (nchild.is_a?(Ref)) then
|
174
|
+
# Need to extract the child.
|
175
|
+
# Create signal holding the child.
|
176
|
+
stmnt = self.statement
|
177
|
+
if (stmnt.is_a?(Connection)) then
|
178
|
+
# Specific case of connections: need to build
|
179
|
+
# a new block.
|
180
|
+
scop = stmnt.parent
|
181
|
+
scop.delete_connection!(stmnt)
|
182
|
+
stmnt = Transmit.new(stmnt.left.clone, stmnt.right.clone)
|
183
|
+
blk = Block.new(:seq)
|
184
|
+
scop.add_behavior(Behavior.new(blk))
|
185
|
+
blk.add_statement(stmnt)
|
186
|
+
else
|
187
|
+
blk = stmnt.block
|
188
|
+
end
|
189
|
+
name = HDLRuby.uniq_name
|
190
|
+
typ = nchild.type
|
191
|
+
sig = blk.add_inner(SignalI.new(name,typ))
|
192
|
+
# Add a statement assigning the child to the new signal.
|
193
|
+
nref = RefName.new(typ,RefThis.new,name)
|
194
|
+
nstmnt = Transmit.new(nref,nchild)
|
195
|
+
idx = blk.each_statement.find_index(stmnt)
|
196
|
+
blk.insert_statement!(idx,nstmnt)
|
197
|
+
# Replace the child by a reference to the created
|
198
|
+
# signal.
|
199
|
+
nchild = nref.clone
|
200
|
+
end
|
201
|
+
return Cast.new(self.type,nchild)
|
202
|
+
end
|
203
|
+
end
|
204
|
+
|
205
|
+
## Extends the Unary class with functionality for extracting
|
206
|
+
# expressions from cast.
|
207
|
+
class Unary
|
208
|
+
|
209
|
+
# Extracts the expressions from the casts.
|
210
|
+
def casts_without_expression
|
211
|
+
# Recurse on the sub node.
|
212
|
+
return Unary.new(self.type,self.operator,
|
213
|
+
self.child.casts_without_expression)
|
214
|
+
return self
|
215
|
+
end
|
216
|
+
end
|
217
|
+
|
218
|
+
|
219
|
+
## Extends the Binary class with functionality for extracting
|
220
|
+
# expressions from cast.
|
221
|
+
class Binary
|
222
|
+
|
223
|
+
# Extracts the expressions from the casts.
|
224
|
+
def casts_without_expression
|
225
|
+
# Recurse on the sub nodes.
|
226
|
+
return Binary.new(self.type,self.operator,
|
227
|
+
self.left.casts_without_expression,
|
228
|
+
self.right.casts_without_expression)
|
229
|
+
end
|
230
|
+
end
|
231
|
+
|
232
|
+
|
233
|
+
|
234
|
+
## Extends the Select class with functionality for extracting
|
235
|
+
# expressions from cast.
|
236
|
+
class Select
|
237
|
+
|
238
|
+
# Extracts the expressions from the casts.
|
239
|
+
def casts_without_expression
|
240
|
+
# Recurse on the sub node.
|
241
|
+
return Select.new(self.type,"?",
|
242
|
+
self.select.casts_without_expression,
|
243
|
+
*self.each_choice.map do |choice|
|
244
|
+
choice.casts_without_expression
|
245
|
+
end )
|
246
|
+
return self
|
247
|
+
end
|
248
|
+
end
|
249
|
+
|
250
|
+
|
251
|
+
## Extends the Concat class with functionality for converting booleans
|
252
|
+
# in assignments to select operators.
|
253
|
+
class Concat
|
254
|
+
# Extracts the expressions from the casts.
|
255
|
+
def casts_without_expression
|
256
|
+
# Recurse on the sub expressions.
|
257
|
+
return Concat.new(self.type,self.each_expression.map do |expr|
|
258
|
+
expr.casts_without_expression
|
259
|
+
end )
|
260
|
+
end
|
261
|
+
end
|
262
|
+
|
263
|
+
|
264
|
+
## Extends the RefConcat class with functionality for converting booleans
|
265
|
+
# in assignments to select operators.
|
266
|
+
class RefConcat
|
267
|
+
# Extracts the expressions from the casts.
|
268
|
+
def casts_without_expression
|
269
|
+
# Recurse on the sub references.
|
270
|
+
return RefConcat.new(self.type,self.each_expression.map do |expr|
|
271
|
+
expr.casts_without_expression
|
272
|
+
end )
|
273
|
+
end
|
274
|
+
end
|
275
|
+
|
276
|
+
|
277
|
+
## Extends the RefIndex class with functionality for converting booleans
|
278
|
+
# in assignments to select operators.
|
279
|
+
class RefIndex
|
280
|
+
# Extracts the expressions from the casts.
|
281
|
+
def casts_without_expression
|
282
|
+
# Recurse on the sub references.
|
283
|
+
return RefIndex.new(self.type,
|
284
|
+
self.ref.casts_without_expression,
|
285
|
+
self.index.casts_without_expression)
|
286
|
+
end
|
287
|
+
end
|
288
|
+
|
289
|
+
|
290
|
+
## Extends the RefRange class with functionality for converting booleans
|
291
|
+
# in assignments to select operators.
|
292
|
+
class RefRange
|
293
|
+
# Extracts the expressions from the casts.
|
294
|
+
def casts_without_expression
|
295
|
+
# Recurse on the sub references.
|
296
|
+
return RefRange.new(self.type,
|
297
|
+
self.ref.casts_without_expression,
|
298
|
+
self.range.first.casts_without_expression ..
|
299
|
+
self.range.last.casts_without_expression)
|
300
|
+
end
|
301
|
+
end
|
302
|
+
|
303
|
+
|
304
|
+
## Extends the RefName class with functionality for converting booleans
|
305
|
+
# in assignments to select operators.
|
306
|
+
class RefName
|
307
|
+
# Extracts the expressions from the casts.
|
308
|
+
def casts_without_expression
|
309
|
+
# Recurse on the sub references.
|
310
|
+
return RefName.new(self.type,
|
311
|
+
self.ref.casts_without_expression,
|
312
|
+
self.name)
|
313
|
+
end
|
314
|
+
end
|
315
|
+
|
316
|
+
|
317
|
+
## Extends the RefThis class with functionality for converting booleans
|
318
|
+
# in assignments to select operators.
|
319
|
+
class RefThis
|
320
|
+
# Extracts the expressions from the casts.
|
321
|
+
def casts_without_expression
|
322
|
+
# Simply clone.
|
323
|
+
return self.clone
|
324
|
+
end
|
325
|
+
end
|
326
|
+
end
|
@@ -11,6 +11,10 @@ include HDLRuby::Verilog
|
|
11
11
|
module HDLRuby::Low
|
12
12
|
|
13
13
|
|
14
|
+
# The list of base types used both in verilog and HDLRuby
|
15
|
+
VERILOG_BASE_TYPES = ["signed"]
|
16
|
+
|
17
|
+
|
14
18
|
# Sample of very handy for programming.
|
15
19
|
# puts "class=#{self.yes.class}" # Confirm class of self.yes.
|
16
20
|
# puts "methods=#{self.right.methods}" # Confirm method of self.right.
|
@@ -456,7 +460,10 @@ class Block
|
|
456
460
|
$fm.fm_par["#{tmt.left.to_verilog}"] = tmt.right
|
457
461
|
end
|
458
462
|
new_block.add_statement(tmt.clone)
|
459
|
-
end
|
463
|
+
end
|
464
|
+
else
|
465
|
+
# Other statements are simply added as is.
|
466
|
+
new_block.add_statement(statement.clone)
|
460
467
|
end
|
461
468
|
end
|
462
469
|
|
@@ -1349,7 +1356,8 @@ end
|
|
1349
1356
|
class TypeVector
|
1350
1357
|
# Converts the system to Verilog code.
|
1351
1358
|
def to_verilog
|
1352
|
-
if self.base.name.to_s != "bit"
|
1359
|
+
# if self.base.name.to_s != "bit"
|
1360
|
+
if VERILOG_BASE_TYPES.include?(self.base.name.to_s)
|
1353
1361
|
return " #{self.base.name.to_s}[#{self.range.first}:#{self.range.last}]"
|
1354
1362
|
end
|
1355
1363
|
return " [#{self.range.first}:#{self.range.last}]"
|
@@ -1598,7 +1606,7 @@ end
|
|
1598
1606
|
class Unary
|
1599
1607
|
# Converts the system to Verilog code.
|
1600
1608
|
def to_verilog
|
1601
|
-
return "#{self.operator}#{self.child.to_verilog}"
|
1609
|
+
return "#{self.operator[0]}#{self.child.to_verilog}"
|
1602
1610
|
end
|
1603
1611
|
end
|
1604
1612
|
|
@@ -1609,10 +1617,37 @@ class Cast
|
|
1609
1617
|
# by traditional verilog.
|
1610
1618
|
def to_verilog
|
1611
1619
|
# return "#{self.type.to_verilog}'(#{self.child.to_verilog})"
|
1620
|
+
if self.child.is_a?(Value) then
|
1621
|
+
return self.child.to_verilog
|
1622
|
+
end
|
1623
|
+
# Get the type widths, used for computing extensions or truncations.
|
1624
|
+
cw = self.child.type.width
|
1625
|
+
sw = self.type.width
|
1612
1626
|
if self.type.signed? then
|
1613
|
-
return "$signed(#{self.child.to_verilog})"
|
1627
|
+
# return "$signed(#{self.child.to_verilog})"
|
1628
|
+
if (sw>cw) then
|
1629
|
+
# Need to sign extend.
|
1630
|
+
return "$signed({{#{sw-cw}{#{self.child.to_verilog}[#{cw-1}]}}," +
|
1631
|
+
"#{self.child.to_verilog}})"
|
1632
|
+
elsif (sw<cw) then
|
1633
|
+
# Need to truncate
|
1634
|
+
return "$signed(#{self.child.to_verilog}[#{sw-1}:0])"
|
1635
|
+
else
|
1636
|
+
# Only enforce signed.
|
1637
|
+
return "$signed(#{self.child.to_verilog})"
|
1638
|
+
end
|
1614
1639
|
else
|
1615
|
-
return "$unsigned(#{self.child.to_verilog})"
|
1640
|
+
# return "$unsigned(#{self.child.to_verilog})"
|
1641
|
+
if (sw>cw) then
|
1642
|
+
# Need to extend.
|
1643
|
+
return "$unsigned({{#{sw-cw}{1'b0}},#{self.child.to_verilog}})"
|
1644
|
+
elsif (sw<cw) then
|
1645
|
+
# Need to truncate
|
1646
|
+
return "$unsigned(#{self.child.to_verilog}[#{sw-1}:0])"
|
1647
|
+
else
|
1648
|
+
# Only enforce signed.
|
1649
|
+
return "$unsigned(#{self.child.to_verilog})"
|
1650
|
+
end
|
1616
1651
|
end
|
1617
1652
|
end
|
1618
1653
|
end
|
@@ -1670,15 +1705,15 @@ class Delay
|
|
1670
1705
|
def to_verilog
|
1671
1706
|
time = self.value.to_s
|
1672
1707
|
if(self.unit.to_s == "ps") then
|
1673
|
-
return "##{time}"
|
1708
|
+
return "##{time};"
|
1674
1709
|
elsif(self.unit.to_s == "ns")
|
1675
|
-
return "##{time}000"
|
1710
|
+
return "##{time}000;"
|
1676
1711
|
elsif(self.unit.to_s == "us")
|
1677
|
-
return "##{time}000000"
|
1712
|
+
return "##{time}000000;"
|
1678
1713
|
elsif(self.unit.to_s == "ms")
|
1679
|
-
return "##{time}000000000"
|
1714
|
+
return "##{time}000000000;"
|
1680
1715
|
elsif(self.unit.to_s == "s")
|
1681
|
-
return "##{time}000000000000"
|
1716
|
+
return "##{time}000000000000;"
|
1682
1717
|
end
|
1683
1718
|
end
|
1684
1719
|
end
|
@@ -1690,6 +1725,20 @@ end
|
|
1690
1725
|
|
1691
1726
|
# Enhance SystemT with generation of verilog code.
|
1692
1727
|
class SystemT
|
1728
|
+
|
1729
|
+
## Tells if a connection is actually a port connection.
|
1730
|
+
def port_output_connection?(connection)
|
1731
|
+
return self.each_systemI.find do |systemI|
|
1732
|
+
if connection.right.is_a?(RefName) &&
|
1733
|
+
connection.right.ref.is_a?(RefName) &&
|
1734
|
+
systemI.name == connection.right.ref.name
|
1735
|
+
puts "port_connection for right=#{connection.right.name} and systemI=#{systemI.name}"
|
1736
|
+
true
|
1737
|
+
else
|
1738
|
+
false
|
1739
|
+
end
|
1740
|
+
end
|
1741
|
+
end
|
1693
1742
|
|
1694
1743
|
## Tells if an expression is a reference to port +systemI.signal+.
|
1695
1744
|
def port_assign?(expr, systemI, signal)
|
@@ -1728,6 +1777,12 @@ class SystemT
|
|
1728
1777
|
# Converts the system to Verilog code.
|
1729
1778
|
def to_verilog
|
1730
1779
|
# Preprocessing
|
1780
|
+
# Force seq block to par: ULTRA TEMPORARY! ICIICI
|
1781
|
+
self.each_behavior do |behavior|
|
1782
|
+
behavior.each_block_deep do |block|
|
1783
|
+
block.set_mode!(:par) unless block.is_a?(TimeBlock)
|
1784
|
+
end
|
1785
|
+
end
|
1731
1786
|
# Detect the registers
|
1732
1787
|
regs = []
|
1733
1788
|
# The left values.
|
@@ -1741,6 +1796,17 @@ class SystemT
|
|
1741
1796
|
end
|
1742
1797
|
end
|
1743
1798
|
end
|
1799
|
+
# # puts "regs has clk?: #{regs.include?("clk")}"
|
1800
|
+
# # puts "for system #{self.name}"
|
1801
|
+
# # Remove the left values of connection, they do not count.
|
1802
|
+
# self.scope.each_connection do |connection|
|
1803
|
+
# # Skip port connections.
|
1804
|
+
# next if !self.port_output_connection?(connection)
|
1805
|
+
# # puts "Not counting left in connection: #{connection.to_verilog}"
|
1806
|
+
# # puts "i.e.: #{connection.left.to_verilog}"
|
1807
|
+
# regs.delete(connection.left.to_verilog)
|
1808
|
+
# end
|
1809
|
+
# # puts "Now regs has clk?: #{regs.include?("clk")}"
|
1744
1810
|
# And the initialized signals.
|
1745
1811
|
self.each_output do |output|
|
1746
1812
|
regs << output.to_verilog if output.value
|
@@ -1750,10 +1816,12 @@ class SystemT
|
|
1750
1816
|
end
|
1751
1817
|
# And the array types signals.
|
1752
1818
|
self.each_signal do |sig|
|
1753
|
-
regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
|
1819
|
+
# regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
|
1820
|
+
regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
|
1754
1821
|
end
|
1755
1822
|
self.each_inner do |sig|
|
1756
|
-
regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
|
1823
|
+
# regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
|
1824
|
+
regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
|
1757
1825
|
end
|
1758
1826
|
|
1759
1827
|
# Code generation
|
@@ -1932,9 +2000,11 @@ class SystemT
|
|
1932
2000
|
|
1933
2001
|
code << "\n"
|
1934
2002
|
|
2003
|
+
# puts "For system=#{self.name}"
|
1935
2004
|
# transliation of the instantiation part.
|
1936
2005
|
# Generate the instances connections.
|
1937
2006
|
self.each_systemI do |systemI|
|
2007
|
+
# puts "Processing systemI = #{systemI.name}"
|
1938
2008
|
# Its Declaration.
|
1939
2009
|
code << " " * 3
|
1940
2010
|
systemT = systemI.systemT
|
data/lib/HDLRuby/std/channel.rb
CHANGED
@@ -778,15 +778,30 @@ module HDLRuby::High::Std
|
|
778
778
|
# Port in same system as the channel case.
|
779
779
|
# Add them to the current system.
|
780
780
|
HDLRuby::High.cur_system.open do
|
781
|
-
locs.each do |name,sig|
|
782
|
-
|
781
|
+
# locs.each do |name,sig|
|
782
|
+
# port_pairs << [sig, sig.type.inner(name)]
|
783
|
+
# end
|
784
|
+
loc_inputs.each do |name,sig|
|
785
|
+
port_pairs << [sig, sig.type.inner(name),:input]
|
786
|
+
end
|
787
|
+
loc_outputs.each do |name,sig|
|
788
|
+
port_pairs << [sig, sig.type.inner(name),:output]
|
789
|
+
end
|
790
|
+
loc_inouts.each do |name,sig|
|
791
|
+
port_pairs << [sig, sig.type.inner(name),:inout]
|
783
792
|
end
|
784
793
|
end
|
785
794
|
obj = self
|
786
795
|
# Make the inner connection
|
787
|
-
port_pairs.each do |sig, port|
|
796
|
+
# port_pairs.each do |sig, port|
|
797
|
+
port_pairs.each do |sig, port, dir|
|
788
798
|
sig.parent.open do
|
789
|
-
port.to_ref <= sig
|
799
|
+
# port.to_ref <= sig
|
800
|
+
if dir == :input then
|
801
|
+
port.to_ref <= sig
|
802
|
+
else
|
803
|
+
sig <= port.to_ref
|
804
|
+
end
|
790
805
|
end
|
791
806
|
end
|
792
807
|
else
|
@@ -796,23 +811,28 @@ module HDLRuby::High::Std
|
|
796
811
|
# The inputs
|
797
812
|
loc_inputs.each do |name,sig|
|
798
813
|
# puts "name=#{name} sig.name=#{sig.name}"
|
799
|
-
port_pairs << [sig, sig.type.input(name)]
|
814
|
+
port_pairs << [sig, sig.type.input(name),:input]
|
800
815
|
end
|
801
816
|
# The outputs
|
802
817
|
loc_outputs.each do |name,sig|
|
803
|
-
port_pairs << [sig, sig.type.output(name)]
|
818
|
+
port_pairs << [sig, sig.type.output(name),:output]
|
804
819
|
end
|
805
820
|
# The inouts
|
806
821
|
loc_inouts.each do |name,sig|
|
807
|
-
port_pairs << [sig, sig.type.inout(name)]
|
822
|
+
port_pairs << [sig, sig.type.inout(name),:inout]
|
808
823
|
end
|
809
824
|
end
|
810
825
|
obj = self
|
811
826
|
# Make the connection of the instance.
|
812
827
|
HDLRuby::High.cur_system.on_instance do |inst|
|
813
828
|
obj.scope.open do
|
814
|
-
port_pairs.each do |sig, port|
|
815
|
-
RefObject.new(inst,port.to_ref) <= sig
|
829
|
+
port_pairs.each do |sig, port, dir|
|
830
|
+
# RefObject.new(inst,port.to_ref) <= sig
|
831
|
+
if dir == :input then
|
832
|
+
RefObject.new(inst,port.to_ref) <= sig
|
833
|
+
else
|
834
|
+
sig <= RefObject.new(inst,port.to_ref)
|
835
|
+
end
|
816
836
|
end
|
817
837
|
end
|
818
838
|
end
|
@@ -870,15 +890,30 @@ module HDLRuby::High::Std
|
|
870
890
|
# Port in same system as the channel case.
|
871
891
|
# Add them to the current system.
|
872
892
|
HDLRuby::High.cur_system.open do
|
873
|
-
locs.each do |name,sig|
|
874
|
-
|
893
|
+
# locs.each do |name,sig|
|
894
|
+
# port_pairs << [sig, sig.type.inner(name)]
|
895
|
+
# end
|
896
|
+
loc_inputs.each do |name,sig|
|
897
|
+
port_pairs << [sig, sig.type.inner(name),:input]
|
898
|
+
end
|
899
|
+
loc_outputs.each do |name,sig|
|
900
|
+
port_pairs << [sig, sig.type.inner(name),:output]
|
901
|
+
end
|
902
|
+
loc_inouts.each do |name,sig|
|
903
|
+
port_pairs << [sig, sig.type.inner(name),:inout]
|
875
904
|
end
|
876
905
|
end
|
877
906
|
obj = self
|
878
907
|
# Make the inner connection
|
879
|
-
port_pairs.each do |sig, port|
|
908
|
+
# port_pairs.each do |sig, port|
|
909
|
+
port_pairs.each do |sig, port, dir|
|
880
910
|
sig.parent.open do
|
881
|
-
port.to_ref <= sig
|
911
|
+
# port.to_ref <= sig
|
912
|
+
if dir == :input then
|
913
|
+
port.to_ref <= sig
|
914
|
+
else
|
915
|
+
sig <= port.to_ref
|
916
|
+
end
|
882
917
|
end
|
883
918
|
end
|
884
919
|
else
|
@@ -887,23 +922,29 @@ module HDLRuby::High::Std
|
|
887
922
|
HDLRuby::High.cur_system.open do
|
888
923
|
# The inputs
|
889
924
|
loc_inputs.each do |name,sig|
|
890
|
-
port_pairs << [sig, sig.type.input(name)]
|
925
|
+
port_pairs << [sig, sig.type.input(name),:input]
|
891
926
|
end
|
892
927
|
# The outputs
|
893
928
|
loc_outputs.each do |name,sig|
|
894
|
-
port_pairs << [sig, sig.type.output(name)]
|
929
|
+
port_pairs << [sig, sig.type.output(name),:output]
|
895
930
|
end
|
896
931
|
# The inouts
|
897
932
|
loc_inouts.each do |name,sig|
|
898
|
-
port_pairs << [sig, sig.type.inout(name)]
|
933
|
+
port_pairs << [sig, sig.type.inout(name),:inout]
|
899
934
|
end
|
900
935
|
end
|
901
936
|
obj = self
|
902
937
|
# Make the connection of the instance.
|
903
938
|
HDLRuby::High.cur_system.on_instance do |inst|
|
904
939
|
obj.scope.open do
|
905
|
-
port_pairs.each do |sig, port|
|
906
|
-
RefObject.new(inst,port.to_ref) <= sig
|
940
|
+
port_pairs.each do |sig, port, dir|
|
941
|
+
# RefObject.new(inst,port.to_ref) <= sig
|
942
|
+
# RefObject.new(inst,port.to_ref) <= sig
|
943
|
+
if dir == :input then
|
944
|
+
RefObject.new(inst,port.to_ref) <= sig
|
945
|
+
else
|
946
|
+
sig <= RefObject.new(inst,port.to_ref)
|
947
|
+
end
|
907
948
|
end
|
908
949
|
end
|
909
950
|
end
|
@@ -13,7 +13,7 @@ module HDLRuby::High::Std
|
|
13
13
|
# duplicator using a handshake protocol. If set to nil, the duplicator
|
14
14
|
# runs automatically.
|
15
15
|
function :duplicator do |typ, ev, in_ch, out_chs, req = nil, ack = nil|
|
16
|
-
ev = ev.
|
16
|
+
ev = ev.posedge unless ev.is_a?(Event)
|
17
17
|
inner :in_ack
|
18
18
|
inner :in_req
|
19
19
|
out_acks = out_chs.size.times.map { |i| inner(:"out_ack#{i}") }
|
data/lib/HDLRuby/std/linear.rb
CHANGED
@@ -229,7 +229,6 @@ module HDLRuby::High::Std
|
|
229
229
|
hif(~rvok) { right.read(rv) { rvok <= 1 } }
|
230
230
|
lefts.each_with_index do |left,i|
|
231
231
|
hif(~lvoks[i]) { left.read(lvs[i]) { lvoks[i] <= 1 } }
|
232
|
-
# accs[i].read(avs[i])
|
233
232
|
hif(lvoks[i] & rvok & ~woks[i]) do
|
234
233
|
ack <= 1
|
235
234
|
run <= 0
|
@@ -237,10 +236,6 @@ module HDLRuby::High::Std
|
|
237
236
|
avs[i] <= add.(avs[i],mul.(lvs[i],rv))
|
238
237
|
accs[i].write(avs[i]) do
|
239
238
|
woks[i] <= 1
|
240
|
-
# seq do
|
241
|
-
# lvoks[i] <= 0
|
242
|
-
# rvok <= lvoks.reduce(:|)
|
243
|
-
# end
|
244
239
|
end
|
245
240
|
end
|
246
241
|
end
|
data/lib/HDLRuby/std/memory.rb
CHANGED
@@ -289,9 +289,10 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
289
289
|
rst = send(rst_name)
|
290
290
|
top_block.unshift do
|
291
291
|
# Initialize the address so that the next access is at address 0.
|
292
|
-
hif(rst==1) { abus_r <= -1 }
|
293
|
-
# Reset so switch of the access trigger.
|
294
|
-
trig_r <= 0
|
292
|
+
# hif(rst==1) { abus_r <= -1 }
|
293
|
+
# # Reset so switch of the access trigger.
|
294
|
+
# trig_r <= 0
|
295
|
+
hif(rst==1) { abus_r <= -1; trig_r <= 0 }
|
295
296
|
end
|
296
297
|
# The read procedure.
|
297
298
|
# par do
|
@@ -317,6 +318,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
317
318
|
# blk.call if blk
|
318
319
|
seq do
|
319
320
|
# abus_r <= abus_r + 1
|
321
|
+
trig_r <= 0
|
320
322
|
target <= dbus_r
|
321
323
|
blk.call if blk
|
322
324
|
end
|
@@ -324,7 +326,8 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
324
326
|
helse do
|
325
327
|
# Prepare the read.
|
326
328
|
# abus_r <= abus_r + 1
|
327
|
-
if 2**size.width != size then
|
329
|
+
# if 2**size.width != size then
|
330
|
+
if 2**awidth != size then
|
328
331
|
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
329
332
|
else
|
330
333
|
abus_r <= abus_r + 1
|
@@ -390,7 +393,8 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
390
393
|
helse do
|
391
394
|
# Prepare the read.
|
392
395
|
# abus_r <= abus_r - 1
|
393
|
-
if 2**size.width != size then
|
396
|
+
# if 2**size.width != size then
|
397
|
+
if 2**awidth != size then
|
394
398
|
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
395
399
|
else
|
396
400
|
abus_r <= abus_r - 1
|
@@ -607,7 +611,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
607
611
|
helse do
|
608
612
|
# Prepare the read.
|
609
613
|
# abus_r <= abus_r + 1
|
610
|
-
if 2**size.width != size then
|
614
|
+
# if 2**size.width != size then
|
615
|
+
if 2**awidth != size then
|
611
616
|
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
612
617
|
else
|
613
618
|
abus_r <= abus_r + 1
|
@@ -649,7 +654,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
649
654
|
blk.call if blk
|
650
655
|
# Prepare the write.
|
651
656
|
# abus_w <= abus_w + 1
|
652
|
-
if 2**size.width != size then
|
657
|
+
# if 2**size.width != size then
|
658
|
+
if 2**awidth != size then
|
653
659
|
abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
|
654
660
|
else
|
655
661
|
abus_w <= abus_w + 1
|
@@ -716,7 +722,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
716
722
|
helse do
|
717
723
|
# Prepare the read.
|
718
724
|
# abus_r <= abus_r - 1
|
719
|
-
if 2**size.width != size then
|
725
|
+
# if 2**size.width != size then
|
726
|
+
if 2**awidth != size then
|
720
727
|
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
721
728
|
else
|
722
729
|
abus_r <= abus_r - 1
|
@@ -758,7 +765,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
758
765
|
blk.call if blk
|
759
766
|
# Prepare the write.
|
760
767
|
# abus_w <= abus_w - 1
|
761
|
-
if 2**size.width != size then
|
768
|
+
# if 2**size.width != size then
|
769
|
+
if 2**awidth != size then
|
762
770
|
abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
|
763
771
|
else
|
764
772
|
abus_w <= abus_w - 1
|
@@ -839,9 +847,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
839
847
|
|
840
848
|
# Defines the ports of the memory as branchs of the channel.
|
841
849
|
|
842
|
-
# The number branch (accesser).
|
850
|
+
# # The number branch (accesser).
|
851
|
+
# The number branch (reader/writer).
|
843
852
|
brancher(:anum) do
|
844
|
-
size.times { |i| accesser_inout :"reg_#{i}" }
|
853
|
+
# size.times { |i| accesser_inout :"reg_#{i}" }
|
854
|
+
size.times { |i| reader_input :"reg_#{i}" }
|
855
|
+
size.times { |i| writer_output :"reg_#{i}" }
|
845
856
|
|
846
857
|
# Defines the read procedure of register number +num+
|
847
858
|
# using +target+ as target of access result.
|
@@ -884,6 +895,39 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
884
895
|
|
885
896
|
end
|
886
897
|
|
898
|
+
# The number read branch (reader).
|
899
|
+
brancher(:rnum) do
|
900
|
+
size.times { |i| reader_input :"reg_#{i}" }
|
901
|
+
|
902
|
+
# Defines the read procedure of register number +num+
|
903
|
+
# using +target+ as target of access result.
|
904
|
+
reader do |blk,num,target|
|
905
|
+
regs = size.times.map {|i| send(:"reg_#{i}") }
|
906
|
+
# The read procedure.
|
907
|
+
par do
|
908
|
+
# No reset, so can perform the read.
|
909
|
+
target <= regs[num]
|
910
|
+
blk.call if blk
|
911
|
+
end
|
912
|
+
end
|
913
|
+
end
|
914
|
+
|
915
|
+
# The number write branch (writer).
|
916
|
+
brancher(:wnum) do
|
917
|
+
size.times { |i| writer_output :"reg_#{i}" }
|
918
|
+
|
919
|
+
# Defines the read procedure of register number +num+
|
920
|
+
# using +target+ as target of access result.
|
921
|
+
writer do |blk,num,target|
|
922
|
+
regs = size.times.map {|i| send(:"reg_#{i}") }
|
923
|
+
# The write procedure.
|
924
|
+
par do
|
925
|
+
regs[num] <= target
|
926
|
+
blk.call if blk
|
927
|
+
end
|
928
|
+
end
|
929
|
+
end
|
930
|
+
|
887
931
|
|
888
932
|
# The address branches.
|
889
933
|
# Read with address
|
@@ -959,7 +1003,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
959
1003
|
awidth = (size-1).width
|
960
1004
|
awidth = 1 if awidth == 0
|
961
1005
|
[awidth].inner :abus_r
|
962
|
-
reader_inout :abus_r
|
1006
|
+
# reader_inout :abus_r
|
1007
|
+
reader_output :abus_r
|
963
1008
|
|
964
1009
|
# Defines the read procedure at address +addr+
|
965
1010
|
# using +target+ as target of access result.
|
@@ -982,7 +1027,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
982
1027
|
blk.call if blk
|
983
1028
|
# Prepare the next read.
|
984
1029
|
# abus_r <= abus_r + 1
|
985
|
-
if 2**size.width != size then
|
1030
|
+
# if 2**size.width != size then
|
1031
|
+
if 2**awidth != size then
|
986
1032
|
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
987
1033
|
else
|
988
1034
|
abus_r <= abus_r + 1
|
@@ -1028,7 +1074,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
1028
1074
|
blk.call if blk
|
1029
1075
|
# Prepare the next write.
|
1030
1076
|
# abus_w <= abus_w + 1
|
1031
|
-
if 2**size.width != size then
|
1077
|
+
# if 2**size.width != size then
|
1078
|
+
if 2**awidth != size then
|
1032
1079
|
abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
|
1033
1080
|
else
|
1034
1081
|
abus_w <= abus_w + 1
|
@@ -1076,7 +1123,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
1076
1123
|
blk.call if blk
|
1077
1124
|
# Prepare the next read.
|
1078
1125
|
# abus_r <= abus_r - 1
|
1079
|
-
if 2**size.width != size then
|
1126
|
+
# if 2**size.width != size then
|
1127
|
+
if 2**awidth != size then
|
1080
1128
|
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
1081
1129
|
else
|
1082
1130
|
abus_r <= abus_r - 1
|
@@ -1122,7 +1170,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
1122
1170
|
blk.call if blk
|
1123
1171
|
# Prepare the next write.
|
1124
1172
|
# abus_w <= abus_w - 1
|
1125
|
-
if 2**size.width != size then
|
1173
|
+
# if 2**size.width != size then
|
1174
|
+
if 2**awidth != size then
|
1126
1175
|
abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
|
1127
1176
|
else
|
1128
1177
|
abus_w <= abus_w - 1
|
@@ -1338,7 +1387,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1338
1387
|
end
|
1339
1388
|
# Prepare the read.
|
1340
1389
|
# abus_r <= abus_r + 1
|
1341
|
-
if 2**size.width != size then
|
1390
|
+
# if 2**size.width != size then
|
1391
|
+
if 2**awidth != size then
|
1342
1392
|
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
1343
1393
|
else
|
1344
1394
|
abus_r <= abus_r + 1
|
@@ -1379,7 +1429,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1379
1429
|
blk.call if blk
|
1380
1430
|
# Prepare the write.
|
1381
1431
|
# abus_w <= abus_w + 1
|
1382
|
-
if 2**size.width != size then
|
1432
|
+
# if 2**size.width != size then
|
1433
|
+
if 2**awidth != size then
|
1383
1434
|
abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
|
1384
1435
|
else
|
1385
1436
|
abus_w <= abus_w + 1
|
@@ -1425,7 +1476,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1425
1476
|
end
|
1426
1477
|
# Prepare the read.
|
1427
1478
|
# abus_r <= abus_r - 1
|
1428
|
-
if 2**size.width != size then
|
1479
|
+
# if 2**size.width != size then
|
1480
|
+
if 2**awidth != size then
|
1429
1481
|
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
1430
1482
|
else
|
1431
1483
|
abus_r <= abus_r - 1
|
@@ -1466,7 +1518,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1466
1518
|
blk.call if blk
|
1467
1519
|
# Prepare the write.
|
1468
1520
|
abus_w <= abus_w - 1
|
1469
|
-
if 2**size.width != size then
|
1521
|
+
# if 2**size.width != size then
|
1522
|
+
if 2**awidth != size then
|
1470
1523
|
abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
|
1471
1524
|
else
|
1472
1525
|
abus_w <= abus_w - 1
|
data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: HDLRuby
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 2.4.
|
4
|
+
version: 2.4.27
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Lovic Gauthier
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2021-01-05 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|
@@ -207,6 +207,7 @@ files:
|
|
207
207
|
- lib/HDLRuby/hruby_low2sym.rb
|
208
208
|
- lib/HDLRuby/hruby_low2vhd.rb
|
209
209
|
- lib/HDLRuby/hruby_low_bool2select.rb
|
210
|
+
- lib/HDLRuby/hruby_low_casts_without_expression.rb
|
210
211
|
- lib/HDLRuby/hruby_low_cleanup.rb
|
211
212
|
- lib/HDLRuby/hruby_low_fix_types.rb
|
212
213
|
- lib/HDLRuby/hruby_low_mutable.rb
|