HDLRuby 2.4.20 → 2.4.27

checksums.yaml

@@ -1,7 +1,7 @@
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data/lib/HDLRuby/hdr_samples/rom.rb

@@ -1,12 +1,14 @@
 
+signed[7..0].typedef(:typ)
+
 # Describes an 8-bit data 4-bit address ROM.
 system :rom4_8 do
     [2..0].input :addr
     [7..0].output :data0,:data1,:data2
 
     bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
-    bit[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
-    bit[7..0][-8].constant content2: (8).times.to_a
+    signed[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
+    typ[-8].constant content2: (8).times.to_a
 
     data0 <= content0[addr]
     data1 <= content1[addr]

data/lib/HDLRuby/hdr_samples/with_connector_memory.rb

@@ -40,10 +40,14 @@ system :channel_connector do
 
     serializer(typ,clk.negedge,[reader_inputs_x,reader_inputs_h],writer_inputs_serializer)
 
-    # merger([typ]*2,clk.negedge,[reader_inputs_x,reader_inputs_h], writer_inputs_meger)
-
-    # duplicator(typ,clk.negedge,reader_inputs_r,[])
-
+    mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_r) # 入力値を格納するrom(x)
+    mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_duplicator0) #
+    mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_duplicator1) #
+    reader_inputs_r    = rom_inputs_r.branch(:rinc)
+    writer_duplicator0 = ram_duplicator0.branch(:winc)
+    writer_duplicator1 = ram_duplicator1.branch(:winc)
+
+    duplicator(typ,clk.posedge,reader_inputs_r,[writer_duplicator0, writer_duplicator1])
 
     timed do
       # リセット

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -61,5 +61,6 @@ system :fix_test do
         !10.ns
         c <= a * b
         !10.ns
+        c <= (a+b) * b
     end
 end

data/lib/HDLRuby/hdrcc.rb

@@ -19,6 +19,7 @@ require 'HDLRuby/hruby_low_with_port'
 require 'HDLRuby/hruby_low_with_var'
 require 'HDLRuby/hruby_low_without_concat'
 require 'HDLRuby/hruby_low_without_connection'
+require 'HDLRuby/hruby_low_casts_without_expression'
 require 'HDLRuby/hruby_low_cleanup'
 
 require 'HDLRuby/hruby_verilog.rb'
@@ -577,6 +578,7 @@ elsif $options[:verilog] then
     # top_system = $top_system
     # Make description compatible with verilog generation.
     $top_system.each_systemT_deep do |systemT|
+        systemT.casts_without_expression!
         systemT.to_upper_space!
         systemT.to_global_systemTs!
         # systemT.break_types!

data/lib/HDLRuby/hruby_low.rb

@@ -1183,6 +1183,11 @@ module HDLRuby::Low
             return false
         end
 
+        # Tells if the type of of vector kind.
+        def vector?
+            return false
+        end
+
         # Gets the bitwidth of the type, by default 0.
         # Bit, signed, unsigned and Float base have a width of 1.
         def width
@@ -1410,7 +1415,7 @@ module HDLRuby::Low
 
             # Sets the delegations
             self.extend Forwardable
-            [ :signed?, :unsigned?, :fixed?, :float?, :leaf?,
+            [ :signed?, :unsigned?, :fixed?, :float?, :leaf?, :vector?,
               :width, :range?, :range, :base?, :base, :types?,
               :get_all_types, :get_type, :each, :each_type, 
               :regular?,
@@ -1466,6 +1471,11 @@ module HDLRuby::Low
         # The base type of the vector
         attr_reader :base
 
+        # Tells if the type of of vector kind.
+        def vector?
+            return true
+        end
+
         # Tells if the type has a base.
         def base?
             return true

data/lib/HDLRuby/hruby_low_casts_without_expression.rb

@@ -0,0 +1,326 @@
+require 'HDLRuby'
+require 'HDLRuby/hruby_tools'
+require 'HDLRuby/hruby_low_mutable'
+require 'HDLRuby/hruby_low_with_bool'
+
+
+module HDLRuby::Low
+
+
+##
+# Replace expressions in cast operators with variables.
+# Use for generating Verilog code generation since bit extension cannot
+# be performed on expression but only on signals. 
+#
+########################################################################
+    
+
+    ## Extends the SystemT class with functionality for extracting 
+    #  expressions from cast.
+    class SystemT
+
+        # Extracts the expressions from the casts.
+        def casts_without_expression!
+            self.scope.casts_without_expression!
+            return self
+        end
+
+    end
+
+
+    ## Extends the Scope class with functionality for extracting 
+    #  expressions from cast.
+    class Scope
+
+        # Extracts the expressions from the casts.
+        def casts_without_expression!
+            # Recurse on the sub scopes.
+            self.each_scope(&:casts_without_expression!)
+
+            # Apply on the connections.
+            self.each_connection(&:casts_without_expression!)
+
+            # Apply on the behaviors.
+            self.each_behavior do |behavior|
+                behavior.block.casts_without_expression!
+            end
+            return self
+        end
+    end
+
+
+    ## Extends the Transmit class with functionality for extracting 
+    #  expressions from cast.
+    class Transmit
+
+        # Extracts the expressions from the casts.
+        def casts_without_expression!
+            # Apply on the left value.
+            self.set_left!(self.left.casts_without_expression)
+            # Apply on the right value.
+            self.set_right!(self.right.casts_without_expression)
+            return self
+        end
+    end
+    
+    ## Extends the If class with functionality for extracting 
+    #  expressions from cast.
+    class If
+
+        # Extracts the expressions from the casts.
+        def casts_without_expression!
+            # Apply on the condition.
+            self.set_condition!(self.condition.casts_without_expression)
+            # Apply on the yes.
+            self.yes.casts_without_expression!
+            # Apply on the noifs.
+            @noifs.map! do |cond,stmnt|
+                [cond.casts_without_expression,stmnt.casts_without_expression!]
+            end
+            # Apply on the no if any.
+            self.no.casts_without_expression! if self.no
+            return self
+        end
+    end
+
+    ## Extends the When class with functionality for extracting 
+    #  expressions from cast.
+    class When
+
+        # Extracts the expressions from the casts.
+        def casts_without_expression!
+            # Apply on the match.
+            self.set_match!(self.match.casts_without_expression)
+            # Apply on the statement.
+            self.statement.casts_without_expression!
+            return self
+        end
+    end
+
+
+    ## Extends the Case class with functionality for extracting 
+    #  expressions from cast.
+    class Case
+
+        # Extracts the expressions from the casts.
+        def casts_without_expression!
+            # No need to apply on the value!
+            # Apply on the value.
+            self.set_value!(self.value.casts_without_expression)
+            # Apply on the whens.
+            self.each_when(&:casts_without_expression!)
+            # Apply on the default if any.
+            self.default.casts_without_expression! if self.default
+            return self
+        end
+    end
+
+
+    ## Extends the TimeWait class with functionality for extracting 
+    #  expressions from cast.
+    class TimeWait
+        # Extracts the expressions from the casts.
+        def casts_without_expression!
+            # Nothing to do.
+            return self
+        end
+    end
+
+    ## Extends the TimeRepeat class with functionality for extracting 
+    #  expressions from cast.
+    class TimeRepeat
+        # Extracts the expressions from the casts.
+        def casts_without_expression!
+            # Simply recurse on the stamtement.
+            self.statement.casts_without_expression!
+            return self
+        end
+    end
+
+
+    ## Extends the Block class with functionality for extracting 
+    #  expressions from cast.
+    class Block
+
+        # Extracts the expressions from the casts.
+        def casts_without_expression!
+            # Apply on each statement.
+            self.each_statement(&:casts_without_expression!)
+            return self
+        end
+    end
+
+
+    ## Extends the Value class with functionality for extracting 
+    #  expressions from cast.
+    class Value
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Simple clones.
+            return self.clone
+        end
+    end
+
+
+    ## Extends the Cast class with functionality for extracting 
+    #  expressions from cast.
+    class Cast
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Recurse on the child.
+            nchild = self.child.casts_without_expression
+            # Process the cast.
+            unless (nchild.is_a?(Ref)) then
+                # Need to extract the child.
+                # Create signal holding the child.
+                stmnt = self.statement
+                if (stmnt.is_a?(Connection)) then
+                    # Specific case of connections: need to build
+                    # a new block.
+                    scop = stmnt.parent
+                    scop.delete_connection!(stmnt)
+                    stmnt = Transmit.new(stmnt.left.clone, stmnt.right.clone)
+                    blk = Block.new(:seq)
+                    scop.add_behavior(Behavior.new(blk))
+                    blk.add_statement(stmnt)
+                else
+                    blk = stmnt.block
+                end
+                name = HDLRuby.uniq_name
+                typ = nchild.type
+                sig = blk.add_inner(SignalI.new(name,typ))
+                # Add a statement assigning the child to the new signal.
+                nref = RefName.new(typ,RefThis.new,name)
+                nstmnt = Transmit.new(nref,nchild)
+                idx = blk.each_statement.find_index(stmnt)
+                blk.insert_statement!(idx,nstmnt)
+                # Replace the child by a reference to the created
+                # signal.
+                nchild = nref.clone
+            end
+            return Cast.new(self.type,nchild)
+        end
+    end
+
+    ## Extends the Unary class with functionality for extracting 
+    #  expressions from cast.
+    class Unary
+
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Recurse on the sub node.
+            return Unary.new(self.type,self.operator,
+                             self.child.casts_without_expression)
+            return self
+        end
+    end
+
+
+    ## Extends the Binary class with functionality for extracting 
+    #  expressions from cast.
+    class Binary
+
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Recurse on the sub nodes.
+            return Binary.new(self.type,self.operator,
+                              self.left.casts_without_expression,
+                              self.right.casts_without_expression)
+        end
+    end
+
+    
+
+    ## Extends the Select class with functionality for extracting 
+    #  expressions from cast.
+    class Select
+
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Recurse on the sub node.
+            return Select.new(self.type,"?", 
+                              self.select.casts_without_expression,
+                              *self.each_choice.map do |choice|
+                                  choice.casts_without_expression
+                              end )
+            return self
+        end
+    end
+
+
+    ## Extends the Concat class with functionality for converting booleans
+    #  in assignments to select operators.
+    class Concat
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Recurse on the sub expressions.
+            return Concat.new(self.type,self.each_expression.map do |expr|
+                expr.casts_without_expression
+            end )
+        end
+    end
+
+
+    ## Extends the RefConcat class with functionality for converting booleans
+    #  in assignments to select operators.
+    class RefConcat
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Recurse on the sub references.
+            return RefConcat.new(self.type,self.each_expression.map do |expr|
+                expr.casts_without_expression
+            end )
+        end
+    end
+
+
+    ## Extends the RefIndex class with functionality for converting booleans
+    #  in assignments to select operators.
+    class RefIndex
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Recurse on the sub references.
+            return RefIndex.new(self.type,
+                                self.ref.casts_without_expression,
+                                self.index.casts_without_expression)
+        end
+    end
+
+
+    ## Extends the RefRange class with functionality for converting booleans
+    #  in assignments to select operators.
+    class RefRange
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Recurse on the sub references.
+            return RefRange.new(self.type,
+                                self.ref.casts_without_expression,
+                                self.range.first.casts_without_expression ..
+                                self.range.last.casts_without_expression)
+        end
+    end
+
+
+    ## Extends the RefName class with functionality for converting booleans
+    #  in assignments to select operators.
+    class RefName
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Recurse on the sub references.
+            return RefName.new(self.type,
+                               self.ref.casts_without_expression,
+                               self.name)
+        end
+    end
+
+
+    ## Extends the RefThis class with functionality for converting booleans
+    #  in assignments to select operators.
+    class RefThis 
+        # Extracts the expressions from the casts.
+        def casts_without_expression
+            # Simply clone.
+            return self.clone
+        end
+    end
+end

data/lib/HDLRuby/hruby_verilog.rb

@@ -11,6 +11,10 @@ include HDLRuby::Verilog
 module HDLRuby::Low
 
 
+    # The list of base types used both in verilog and HDLRuby
+    VERILOG_BASE_TYPES = ["signed"]
+
+
 # Sample of very handy for programming.
 # puts "class=#{self.yes.class}"       # Confirm class of self.yes.
 # puts "methods=#{self.right.methods}" # Confirm method of self.right.
@@ -456,7 +460,10 @@ class Block
                             $fm.fm_par["#{tmt.left.to_verilog}"] = tmt.right
                         end
                         new_block.add_statement(tmt.clone)           
-                    end         
+                    end
+                else
+                    # Other statements are simply added as is.
+                    new_block.add_statement(statement.clone)
                 end
             end
 
@@ -1349,7 +1356,8 @@ end
 class TypeVector
     # Converts the system to Verilog code.
     def to_verilog
-        if self.base.name.to_s != "bit"
+        # if self.base.name.to_s != "bit"
+        if VERILOG_BASE_TYPES.include?(self.base.name.to_s)
             return " #{self.base.name.to_s}[#{self.range.first}:#{self.range.last}]"
         end
         return " [#{self.range.first}:#{self.range.last}]"
@@ -1598,7 +1606,7 @@ end
 class Unary
     # Converts the system to Verilog code.
     def to_verilog
-        return "#{self.operator}#{self.child.to_verilog}"
+        return "#{self.operator[0]}#{self.child.to_verilog}"
     end
 end
 
@@ -1609,10 +1617,37 @@ class Cast
     #       by traditional verilog.
     def to_verilog
         # return "#{self.type.to_verilog}'(#{self.child.to_verilog})"
+        if self.child.is_a?(Value) then
+            return self.child.to_verilog
+        end
+        # Get the type widths, used for computing extensions or truncations.
+        cw = self.child.type.width
+        sw = self.type.width
         if self.type.signed? then
-            return "$signed(#{self.child.to_verilog})"
+            # return "$signed(#{self.child.to_verilog})"
+            if (sw>cw) then
+                # Need to sign extend.
+                return "$signed({{#{sw-cw}{#{self.child.to_verilog}[#{cw-1}]}}," +
+                  "#{self.child.to_verilog}})"
+            elsif (sw<cw) then
+                # Need to truncate
+                return "$signed(#{self.child.to_verilog}[#{sw-1}:0])"
+            else
+                # Only enforce signed.
+                return "$signed(#{self.child.to_verilog})"
+            end
         else
-            return "$unsigned(#{self.child.to_verilog})"
+            # return "$unsigned(#{self.child.to_verilog})"
+            if (sw>cw) then
+                # Need to extend.
+                return "$unsigned({{#{sw-cw}{1'b0}},#{self.child.to_verilog}})"
+            elsif (sw<cw) then
+                # Need to truncate
+                return "$unsigned(#{self.child.to_verilog}[#{sw-1}:0])"
+            else
+                # Only enforce signed.
+                return "$unsigned(#{self.child.to_verilog})"
+            end
         end
     end
 end
@@ -1670,15 +1705,15 @@ class Delay
     def to_verilog
         time = self.value.to_s
         if(self.unit.to_s == "ps") then
-            return "##{time}"
+            return "##{time};"
         elsif(self.unit.to_s == "ns")
-            return "##{time}000"
+            return "##{time}000;"
         elsif(self.unit.to_s == "us")
-            return "##{time}000000"
+            return "##{time}000000;"
         elsif(self.unit.to_s == "ms")
-            return "##{time}000000000"
+            return "##{time}000000000;"
         elsif(self.unit.to_s == "s")
-            return "##{time}000000000000"
+            return "##{time}000000000000;"
         end
     end
 end
@@ -1690,6 +1725,20 @@ end
 
 # Enhance SystemT with generation of verilog code.
 class SystemT
+    
+    ## Tells if a connection is actually a port connection.
+    def port_output_connection?(connection)
+        return self.each_systemI.find do |systemI|
+            if connection.right.is_a?(RefName) && 
+            connection.right.ref.is_a?(RefName) &&
+            systemI.name == connection.right.ref.name
+                puts "port_connection for right=#{connection.right.name} and systemI=#{systemI.name}"
+                true
+            else
+                false
+            end
+        end
+    end
 
     ## Tells if an expression is a reference to port +systemI.signal+.
     def port_assign?(expr, systemI, signal)
@@ -1728,6 +1777,12 @@ class SystemT
     # Converts the system to Verilog code.
     def to_verilog
         # Preprocessing
+        # Force seq block to par: ULTRA TEMPORARY! ICIICI
+        self.each_behavior do |behavior|
+            behavior.each_block_deep do |block|
+                block.set_mode!(:par) unless block.is_a?(TimeBlock)
+            end
+        end
         # Detect the registers
         regs = []
         # The left values.
@@ -1741,6 +1796,17 @@ class SystemT
                 end
             end
         end
+        # # puts "regs has clk?: #{regs.include?("clk")}"
+        # # puts "for system #{self.name}"
+        # # Remove the left values of connection, they do not count.
+        # self.scope.each_connection do |connection|
+        #     # Skip port connections.
+        #     next if !self.port_output_connection?(connection) 
+        #     # puts "Not counting left in connection: #{connection.to_verilog}"
+        #     # puts "i.e.: #{connection.left.to_verilog}"
+        #     regs.delete(connection.left.to_verilog)
+        # end
+        # # puts "Now regs has clk?: #{regs.include?("clk")}"
         # And the initialized signals.
         self.each_output do |output|
             regs << output.to_verilog if output.value
@@ -1750,10 +1816,12 @@ class SystemT
         end
         # And the array types signals.
         self.each_signal do |sig|
-            regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
         end
         self.each_inner do |sig|
-            regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
         end
 
         # Code generation
@@ -1932,9 +2000,11 @@ class SystemT
 
         code << "\n"
 
+        # puts "For system=#{self.name}"
         # transliation of the instantiation part.
         # Generate the instances connections.
         self.each_systemI do |systemI| 
+            # puts "Processing systemI = #{systemI.name}"
             # Its Declaration.
             code << " " * 3
             systemT = systemI.systemT

data/lib/HDLRuby/std/channel.rb

@@ -778,15 +778,30 @@ module HDLRuby::High::Std
                 # Port in same system as the channel case.
                 # Add them to the current system.
                 HDLRuby::High.cur_system.open do
-                    locs.each  do |name,sig|
-                        port_pairs << [sig, sig.type.inner(name)]
+                    # locs.each  do |name,sig|
+                    #     port_pairs << [sig, sig.type.inner(name)]
+                    # end
+                    loc_inputs.each  do |name,sig|
+                        port_pairs << [sig, sig.type.inner(name),:input]
+                    end
+                    loc_outputs.each  do |name,sig|
+                        port_pairs << [sig, sig.type.inner(name),:output]
+                    end
+                    loc_inouts.each  do |name,sig|
+                        port_pairs << [sig, sig.type.inner(name),:inout]
                     end
                 end
                 obj = self
                 # Make the inner connection
-                port_pairs.each do |sig, port|
+                # port_pairs.each do |sig, port|
+                port_pairs.each do |sig, port, dir|
                     sig.parent.open do
-                        port.to_ref <= sig
+                        # port.to_ref <= sig
+                        if dir == :input then
+                            port.to_ref <= sig
+                        else
+                            sig <= port.to_ref
+                        end
                     end
                 end
             else
@@ -796,23 +811,28 @@ module HDLRuby::High::Std
                     # The inputs
                     loc_inputs.each  do |name,sig|
                         # puts "name=#{name} sig.name=#{sig.name}"
-                        port_pairs << [sig, sig.type.input(name)]
+                        port_pairs << [sig, sig.type.input(name),:input]
                     end
                     # The outputs
                     loc_outputs.each do |name,sig| 
-                        port_pairs << [sig, sig.type.output(name)]
+                        port_pairs << [sig, sig.type.output(name),:output]
                     end
                     # The inouts
                     loc_inouts.each  do |name,sig| 
-                        port_pairs << [sig, sig.type.inout(name)]
+                        port_pairs << [sig, sig.type.inout(name),:inout]
                     end
                 end
                 obj = self
                 # Make the connection of the instance.
                 HDLRuby::High.cur_system.on_instance do |inst|
                     obj.scope.open do
-                        port_pairs.each do |sig, port|
-                            RefObject.new(inst,port.to_ref) <= sig
+                        port_pairs.each do |sig, port, dir|
+                            # RefObject.new(inst,port.to_ref) <= sig
+                            if dir == :input then
+                                RefObject.new(inst,port.to_ref) <= sig
+                            else
+                                sig <= RefObject.new(inst,port.to_ref)
+                            end
                         end
                     end
                 end
@@ -870,15 +890,30 @@ module HDLRuby::High::Std
                 # Port in same system as the channel case.
                 # Add them to the current system.
                 HDLRuby::High.cur_system.open do
-                    locs.each  do |name,sig|
-                        port_pairs << [sig, sig.type.inner(name)]
+                    # locs.each  do |name,sig|
+                    #     port_pairs << [sig, sig.type.inner(name)]
+                    # end
+                    loc_inputs.each  do |name,sig|
+                        port_pairs << [sig, sig.type.inner(name),:input]
+                    end
+                    loc_outputs.each  do |name,sig|
+                        port_pairs << [sig, sig.type.inner(name),:output]
+                    end
+                    loc_inouts.each  do |name,sig|
+                        port_pairs << [sig, sig.type.inner(name),:inout]
                     end
                 end
                 obj = self
                 # Make the inner connection
-                port_pairs.each do |sig, port|
+                # port_pairs.each do |sig, port|
+                port_pairs.each do |sig, port, dir|
                     sig.parent.open do
-                        port.to_ref <= sig
+                        # port.to_ref <= sig
+                        if dir == :input then
+                            port.to_ref <= sig
+                        else
+                            sig <= port.to_ref
+                        end
                     end
                 end
             else
@@ -887,23 +922,29 @@ module HDLRuby::High::Std
                 HDLRuby::High.cur_system.open do
                     # The inputs
                     loc_inputs.each  do |name,sig|
-                        port_pairs << [sig, sig.type.input(name)]
+                        port_pairs << [sig, sig.type.input(name),:input]
                     end
                     # The outputs
                     loc_outputs.each do |name,sig| 
-                        port_pairs << [sig, sig.type.output(name)]
+                        port_pairs << [sig, sig.type.output(name),:output]
                     end
                     # The inouts
                     loc_inouts.each  do |name,sig| 
-                        port_pairs << [sig, sig.type.inout(name)]
+                        port_pairs << [sig, sig.type.inout(name),:inout]
                     end
                 end
                 obj = self
                 # Make the connection of the instance.
                 HDLRuby::High.cur_system.on_instance do |inst|
                     obj.scope.open do
-                        port_pairs.each do |sig, port|
-                            RefObject.new(inst,port.to_ref) <= sig
+                        port_pairs.each do |sig, port, dir|
+                            # RefObject.new(inst,port.to_ref) <= sig
+                            # RefObject.new(inst,port.to_ref) <= sig
+                            if dir == :input then
+                                RefObject.new(inst,port.to_ref) <= sig
+                            else
+                                sig <= RefObject.new(inst,port.to_ref)
+                            end
                         end
                     end
                 end

data/lib/HDLRuby/std/connector.rb

@@ -13,7 +13,7 @@ module HDLRuby::High::Std
     # duplicator using a handshake protocol. If set to nil, the duplicator
     # runs automatically.
     function :duplicator do |typ, ev, in_ch, out_chs, req = nil, ack = nil|
-        ev = ev.poswedge unless ev.is_a?(Event)
+        ev = ev.posedge unless ev.is_a?(Event)
         inner :in_ack
         inner :in_req
         out_acks = out_chs.size.times.map { |i| inner(:"out_ack#{i}") }

data/lib/HDLRuby/std/linear.rb

@@ -229,7 +229,6 @@ module HDLRuby::High::Std
                 hif(~rvok) { right.read(rv) { rvok <= 1 } }
                 lefts.each_with_index do |left,i|
                     hif(~lvoks[i]) { left.read(lvs[i])  { lvoks[i] <= 1 } }
-                    # accs[i].read(avs[i])
                     hif(lvoks[i] & rvok & ~woks[i]) do
                         ack <= 1
                         run <= 0
@@ -237,10 +236,6 @@ module HDLRuby::High::Std
                             avs[i] <= add.(avs[i],mul.(lvs[i],rv))
                             accs[i].write(avs[i]) do
                                 woks[i] <= 1
-                                # seq do
-                                #     lvoks[i] <= 0
-                                #     rvok <= lvoks.reduce(:|)
-                                # end
                             end
                         end
                     end

data/lib/HDLRuby/std/memory.rb

@@ -289,9 +289,10 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
             rst  = send(rst_name)
             top_block.unshift do
                 # Initialize the address so that the next access is at address 0.
-                hif(rst==1) { abus_r <= -1 }
-                # Reset so switch of the access trigger.
-                trig_r <= 0
+                # hif(rst==1) { abus_r <= -1 }
+                # # Reset so switch of the access trigger.
+                # trig_r <= 0
+                hif(rst==1) { abus_r <= -1; trig_r <= 0 }
             end
             # The read procedure.
         #     par do
@@ -317,6 +318,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                         # blk.call if blk
                         seq do
                             # abus_r <= abus_r + 1
+                            trig_r <= 0
                             target <= dbus_r
                             blk.call if blk
                         end
@@ -324,7 +326,8 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                     helse do
                         # Prepare the read.
                         # abus_r <= abus_r + 1
-                        if 2**size.width != size then
+                        # if 2**size.width != size then
+                        if 2**awidth != size then
                             abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
                         else
                             abus_r <= abus_r + 1
@@ -390,7 +393,8 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                     helse do
                         # Prepare the read.
                         # abus_r <= abus_r - 1
-                        if 2**size.width != size then
+                        # if 2**size.width != size then
+                        if 2**awidth != size then
                             abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
                         else
                             abus_r <= abus_r - 1
@@ -607,7 +611,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     helse do
                         # Prepare the read.
                         # abus_r <= abus_r + 1
-                        if 2**size.width != size then
+                        # if 2**size.width != size then
+                        if 2**awidth != size then
                             abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
                         else
                             abus_r <= abus_r + 1
@@ -649,7 +654,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the write.
                     # abus_w <= abus_w + 1
-                    if 2**size.width != size then
+                    # if 2**size.width != size then
+                    if 2**awidth != size then
                         abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
                     else
                         abus_w <= abus_w + 1
@@ -716,7 +722,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     helse do
                         # Prepare the read.
                         # abus_r <= abus_r - 1
-                        if 2**size.width != size then
+                        # if 2**size.width != size then
+                        if 2**awidth != size then
                             abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
                         else
                             abus_r <= abus_r - 1
@@ -758,7 +765,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the write.
                     # abus_w <= abus_w - 1
-                    if 2**size.width != size then
+                    # if 2**size.width != size then
+                    if 2**awidth != size then
                         abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
                     else
                         abus_w <= abus_w - 1
@@ -839,9 +847,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
 
     # Defines the ports of the memory as branchs of the channel.
     
-    # The number branch (accesser).
+    # # The number branch (accesser).
+    # The number branch (reader/writer).
     brancher(:anum) do
-        size.times { |i| accesser_inout :"reg_#{i}" }
+        # size.times { |i| accesser_inout :"reg_#{i}" }
+        size.times { |i| reader_input :"reg_#{i}" }
+        size.times { |i| writer_output :"reg_#{i}" }
 
         # Defines the read procedure of register number +num+
         # using +target+ as target of access result.
@@ -884,6 +895,39 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
 
     end
 
+    # The number read branch (reader).
+    brancher(:rnum) do
+        size.times { |i| reader_input :"reg_#{i}" }
+
+        # Defines the read procedure of register number +num+
+        # using +target+ as target of access result.
+        reader do |blk,num,target|
+            regs = size.times.map {|i| send(:"reg_#{i}") }
+            # The read procedure.
+            par do
+                # No reset, so can perform the read.
+                target <= regs[num]
+                blk.call if blk
+            end
+        end
+    end
+
+    # The number write branch (writer).
+    brancher(:wnum) do
+        size.times { |i| writer_output :"reg_#{i}" }
+
+        # Defines the read procedure of register number +num+
+        # using +target+ as target of access result.
+        writer do |blk,num,target|
+            regs = size.times.map {|i| send(:"reg_#{i}") }
+            # The write procedure.
+            par do
+                regs[num] <= target
+                blk.call if blk
+            end
+        end
+    end
+
     
     # The address branches.
     # Read with address
@@ -959,7 +1003,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
         awidth = (size-1).width
         awidth = 1 if awidth == 0
         [awidth].inner :abus_r
-        reader_inout :abus_r
+        # reader_inout :abus_r
+        reader_output :abus_r
 
         # Defines the read procedure at address +addr+
         # using +target+ as target of access result.
@@ -982,7 +1027,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the next read.
                     # abus_r <= abus_r + 1
-                    if 2**size.width != size then
+                    # if 2**size.width != size then
+                    if 2**awidth != size then
                         abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
                     else
                         abus_r <= abus_r + 1
@@ -1028,7 +1074,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the next write.
                     # abus_w <= abus_w + 1
-                    if 2**size.width != size then
+                    # if 2**size.width != size then
+                    if 2**awidth != size then
                         abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
                     else
                         abus_w <= abus_w + 1
@@ -1076,7 +1123,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the next read.
                     # abus_r <= abus_r - 1
-                    if 2**size.width != size then
+                    # if 2**size.width != size then
+                    if 2**awidth != size then
                         abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
                     else
                         abus_r <= abus_r - 1
@@ -1122,7 +1170,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the next write.
                     # abus_w <= abus_w - 1
-                    if 2**size.width != size then
+                    # if 2**size.width != size then
+                    if 2**awidth != size then
                         abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
                     else
                         abus_w <= abus_w - 1
@@ -1338,7 +1387,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     end
                     # Prepare the read.
                     # abus_r <= abus_r + 1
-                    if 2**size.width != size then
+                    # if 2**size.width != size then
+                    if 2**awidth != size then
                         abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
                     else
                         abus_r <= abus_r + 1
@@ -1379,7 +1429,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the write.
                     # abus_w <= abus_w + 1
-                    if 2**size.width != size then
+                    # if 2**size.width != size then
+                    if 2**awidth != size then
                         abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
                     else
                         abus_w <= abus_w + 1
@@ -1425,7 +1476,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     end
                     # Prepare the read.
                     # abus_r <= abus_r - 1
-                    if 2**size.width != size then
+                    # if 2**size.width != size then
+                    if 2**awidth != size then
                         abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
                     else
                         abus_r <= abus_r - 1
@@ -1466,7 +1518,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the write.
                     abus_w <= abus_w - 1
-                    if 2**size.width != size then
+                    # if 2**size.width != size then
+                    if 2**awidth != size then
                         abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
                     else
                         abus_w <= abus_w - 1

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.20"
+  VERSION = "2.4.27"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.20
+  version: 2.4.27
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-12-09 00:00:00.000000000 Z
+date: 2021-01-05 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -207,6 +207,7 @@ files:
 - lib/HDLRuby/hruby_low2sym.rb
 - lib/HDLRuby/hruby_low2vhd.rb
 - lib/HDLRuby/hruby_low_bool2select.rb
+- lib/HDLRuby/hruby_low_casts_without_expression.rb
 - lib/HDLRuby/hruby_low_cleanup.rb
 - lib/HDLRuby/hruby_low_fix_types.rb
 - lib/HDLRuby/hruby_low_mutable.rb