HDLRuby 2.4.20 → 2.4.21
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
checksums.yaml
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@@ -1,7 +1,7 @@
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 28c1956d124429de349aede3dce3644cca530400479dedb09bedc3326a1fdb76
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data.tar.gz: cd76438901da8bff407b7db4abef07399192c19f0349af0c9e0e545a1a22cf1d
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 89ccd495fa050a3f552ea73e52f726a08f56f5a937691209622a4d008a62905134d3a4765265ee07ff4c8aca59bc097221d4f75fc9da445ba3115fe6aee293ea
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data.tar.gz: 47150e816409de410e41f8aa5a22e7bcc514ac88d2798d0282cb1efa5f660ec0e20d35015f807c43e7823ef4ae406125aba45bcd28b2acaf740991528549c413
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@@ -40,10 +40,14 @@ system :channel_connector do
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serializer(typ,clk.negedge,[reader_inputs_x,reader_inputs_h],writer_inputs_serializer)
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mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_r) # 入力値を格納するrom(x)
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mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_duplicator0) #
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mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_duplicator1) #
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reader_inputs_r = rom_inputs_r.branch(:rinc)
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writer_duplicator0 = ram_duplicator0.branch(:winc)
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writer_duplicator1 = ram_duplicator1.branch(:winc)
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duplicator(typ,clk.posedge,reader_inputs_r,[writer_duplicator0, writer_duplicator1])
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timed do
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# リセット
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@@ -13,7 +13,7 @@ module HDLRuby::High::Std
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# duplicator using a handshake protocol. If set to nil, the duplicator
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# runs automatically.
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function :duplicator do |typ, ev, in_ch, out_chs, req = nil, ack = nil|
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ev = ev.
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ev = ev.posedge unless ev.is_a?(Event)
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inner :in_ack
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inner :in_req
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out_acks = out_chs.size.times.map { |i| inner(:"out_ack#{i}") }
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data/lib/HDLRuby/std/memory.rb
CHANGED
@@ -289,9 +289,10 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
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rst = send(rst_name)
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top_block.unshift do
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# Initialize the address so that the next access is at address 0.
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hif(rst==1) { abus_r <= -1 }
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# Reset so switch of the access trigger.
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trig_r <= 0
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# hif(rst==1) { abus_r <= -1 }
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# # Reset so switch of the access trigger.
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# trig_r <= 0
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hif(rst==1) { abus_r <= -1; trig_r <= 0 }
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end
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# The read procedure.
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# par do
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@@ -317,6 +318,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
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# blk.call if blk
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seq do
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# abus_r <= abus_r + 1
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trig_r <= 0
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target <= dbus_r
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blk.call if blk
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end
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data/lib/HDLRuby/version.rb
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metadata
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@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: HDLRuby
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version: !ruby/object:Gem::Version
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version: 2.4.
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version: 2.4.21
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platform: ruby
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authors:
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- Lovic Gauthier
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autorequire:
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bindir: exe
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cert_chain: []
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date: 2020-12-
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date: 2020-12-10 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: bundler
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