HDLRuby 2.4.17 → 2.4.22

checksums.yaml

@@ -1,7 +1,7 @@
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data/lib/HDLRuby/hdr_samples/rom.rb

@@ -1,12 +1,14 @@
 
+signed[7..0].typedef(:typ)
+
 # Describes an 8-bit data 4-bit address ROM.
 system :rom4_8 do
     [2..0].input :addr
     [7..0].output :data0,:data1,:data2
 
     bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
-    bit[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
-    bit[7..0][-8].constant content2: (8).times.to_a
+    signed[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
+    typ[-8].constant content2: (8).times.to_a
 
     data0 <= content0[addr]
     data1 <= content1[addr]

data/lib/HDLRuby/hdr_samples/with_connector.rb

@@ -125,9 +125,12 @@ end
 # Module for testing the connector.
 system :with_connectors do
     inner :clk, :rst
-    [4].inner :counter #, :res_0,:res_1,:res_2,:res_3
+
+    # First tester.
+    [4].inner :counter
     [4*4].inner :res
     inner :ack_in, :ack_out
+    inner :dup_req, :dup_ack
 
     # The input queue.
     queue(bit[4],4,clk,rst).(:in_qu)
@@ -141,11 +144,27 @@ system :with_connectors do
     queue(bit[4*4],4,clk,rst).(:out_qu)
 
     # Connect the input queue to the middle queues.
-    duplicator(bit[4],clk.negedge,in_qu,mid_qus)
+    duplicator(bit[4],clk.negedge,in_qu,mid_qus,dup_req,dup_ack)
 
     # Connect the middle queues to the output queue.
     merger([bit[4]]*4,clk.negedge,mid_qus,out_qu)
 
+
+    # Second tester.
+    [4].inner :counterb
+    [4].inner :resb
+    inner :ack_inb0, :ack_inb1, :ack_outb
+
+    # The input queues.
+    queue(bit[4],4,clk,rst).(:in_qub0)
+    queue(bit[4],4,clk,rst).(:in_qub1)
+
+    # The output queue.
+    queue(bit[4],4,clk,rst).(:out_qub)
+
+    # Connect then with a serializer.
+    serializer(bit[4],clk.negedge,[in_qub0,in_qub1],out_qub)
+
     # # Slow version, always work
     # par(clk.posedge) do
     #     ack_in <= 0
@@ -171,25 +190,39 @@ system :with_connectors do
     # Fast version but assumes connected channels are blocking
     par(clk.posedge) do
         ack_in <= 0
-        hif(rst) { counter <= 0 }
+        ack_inb0 <= 0
+        ack_inb1 <= 0
+        hif(rst) { counter <= 0; counterb <= 0 }
         helse do
             in_qu.write(counter)  do
                 ack_in <= 1
                 counter <= counter + 1
             end
             hif(ack_in) do
-                # mid_qu0.read(res_0)
-                # mid_qu1.read(res_1)
-                # mid_qu2.read(res_2)
-                # mid_qu3.read(res_3)
                 out_qu.read(res)
             end
+            hif(~ack_inb0) do
+                in_qub0.write(counterb) do
+                    ack_inb0 <= 1
+                    counterb <= counterb + 1
+                end
+            end
+            helse do
+                in_qub1.write(counterb) do
+                    ack_inb1 <= 1
+                    counterb <= counterb + 1
+                end
+            end
+            hif(ack_inb0 | ack_inb1) do
+                out_qub.read(resb)
+            end
         end
     end
 
     timed do
         clk <= 0
         rst <= 0
+        dup_req <= 0
         !10.ns
         clk <= 1
         !10.ns
@@ -204,6 +237,13 @@ system :with_connectors do
         !10.ns
         clk <= 0
         rst <= 0
+        4.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+        end
+        dup_req <= 1
         16.times do
             !10.ns
             clk <= 1

data/lib/HDLRuby/hdr_samples/with_connector_memory.rb

@@ -0,0 +1,102 @@
+require 'std/memory.rb'
+require "std/fixpoint.rb"
+require 'std/channel.rb'
+require 'std/connector.rb'
+
+include HDLRuby::High::Std
+
+system :channel_connector do
+    # データ型の宣言
+    integer_width = 4 # 整数部のビット幅
+    decimal_width = 4 # 実数部のビット幅
+    address_width = 4 # lutのアドレスのビット幅
+    typ = signed[integer_width + decimal_width] # データ型
+    
+    inputs_x = _00010011
+    inputs_h = _10100001
+    columns = [2, 2, 1]
+
+    inner :clk,   # clock
+          :rst,   # reset
+          :req,   # request
+          :fill   # 入力値のメモリへの書き込み
+
+    # inputs_x = quantize(inputs_x, typ, decimal_width)
+    # inputs_h = quantize(inputs_h, typ, decimal_width)
+
+    mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_x) # 入力値を格納するrom(x)
+
+    mem_rom(typ, columns[0], clk, rst, inputs_h, rinc: :rst, winc: :rst).(:rom_inputs_h) # 入力値を格納するrom(h)
+
+    mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_serializer) #
+
+    mem_dual(typ, columns[0]*2, clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_merger) #
+
+    reader_inputs_x = rom_inputs_x.branch(:rinc) #入力値xの読みだし用branch
+    reader_inputs_h = rom_inputs_h.branch(:rinc) #入力値hの読みだし用branch
+    writer_inputs_serializer = ram_inputs_serializer.branch(:winc) #入力値を合成した値の書き込み用branch
+    writer_inputs_meger = ram_inputs_merger.branch(:winc) #入力値を合成した値の書き込み用branch
+  
+
+    serializer(typ,clk.negedge,[reader_inputs_x,reader_inputs_h],writer_inputs_serializer)
+
+    mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_r) # 入力値を格納するrom(x)
+    mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_duplicator0) #
+    mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_duplicator1) #
+    reader_inputs_r    = rom_inputs_r.branch(:rinc)
+    writer_duplicator0 = ram_duplicator0.branch(:winc)
+    writer_duplicator1 = ram_duplicator1.branch(:winc)
+
+    duplicator(typ,clk.posedge,reader_inputs_r,[writer_duplicator0, writer_duplicator1])
+
+    timed do
+      # リセット
+      clk <= 0
+      rst <= 0
+      req <= 0
+      fill <= 0
+      !10.ps
+
+      # メモリ読み出し位置の初期化
+      rst <= 1
+      !10.ps
+      clk <= 1
+      !10.ps
+      clk <= 0
+      !10.ps
+      clk <= 1
+      !10.ps
+
+      # パラメータのメモリへの書き込み
+      clk <= 0
+      rst <= 0
+      fill <= 1
+
+      !10.ps
+      10.times do |i|
+        clk <= 1
+        !10.ps
+        clk <= 0
+        !10.ps
+      end
+
+      fill <= 0
+      clk <= 1
+      !10.ps
+
+      # 計算の実行
+      clk <= 0
+      req <= 1
+      !10.ps
+      clk <= 1
+      !10.ps
+      clk <= 0
+      !10.ps
+      30.times do
+        clk <= 1
+        !10.ps
+        clk <= 0
+        !10.ps
+      end
+    end
+end

data/lib/HDLRuby/hruby_low.rb

@@ -1183,6 +1183,11 @@ module HDLRuby::Low
             return false
         end
 
+        # Tells if the type of of vector kind.
+        def vector?
+            return false
+        end
+
         # Gets the bitwidth of the type, by default 0.
         # Bit, signed, unsigned and Float base have a width of 1.
         def width
@@ -1410,7 +1415,7 @@ module HDLRuby::Low
 
             # Sets the delegations
             self.extend Forwardable
-            [ :signed?, :unsigned?, :fixed?, :float?, :leaf?,
+            [ :signed?, :unsigned?, :fixed?, :float?, :leaf?, :vector?,
               :width, :range?, :range, :base?, :base, :types?,
               :get_all_types, :get_type, :each, :each_type, 
               :regular?,
@@ -1466,6 +1471,11 @@ module HDLRuby::Low
         # The base type of the vector
         attr_reader :base
 
+        # Tells if the type of of vector kind.
+        def vector?
+            return true
+        end
+
         # Tells if the type has a base.
         def base?
             return true

data/lib/HDLRuby/hruby_verilog.rb

@@ -11,6 +11,10 @@ include HDLRuby::Verilog
 module HDLRuby::Low
 
 
+    # The list of base types used both in verilog and HDLRuby
+    VERILOG_BASE_TYPES = ["signed"]
+
+
 # Sample of very handy for programming.
 # puts "class=#{self.yes.class}"       # Confirm class of self.yes.
 # puts "methods=#{self.right.methods}" # Confirm method of self.right.
@@ -1349,7 +1353,8 @@ end
 class TypeVector
     # Converts the system to Verilog code.
     def to_verilog
-        if self.base.name.to_s != "bit"
+        # if self.base.name.to_s != "bit"
+        if VERILOG_BASE_TYPES.include?(self.base.name.to_s)
             return " #{self.base.name.to_s}[#{self.range.first}:#{self.range.last}]"
         end
         return " [#{self.range.first}:#{self.range.last}]"
@@ -1750,10 +1755,12 @@ class SystemT
         end
         # And the array types signals.
         self.each_signal do |sig|
-            regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
         end
         self.each_inner do |sig|
-            regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
         end
 
         # Code generation

data/lib/HDLRuby/std/connector.rb

@@ -9,13 +9,28 @@ module HDLRuby::High::Std
     # channel +in_ch+ and connect it to channels +out_chs+ with data of
     # +typ+.
     # The duplication is done according to event +ev+.
-    function :duplicator do |typ, ev, in_ch, out_chs|
-        ev = ev.poswedge unless ev.is_a?(Event)
-        inner :in_ack, :in_req
+    # The optional req and ack arguments are the signals for controlling the
+    # duplicator using a handshake protocol. If set to nil, the duplicator
+    # runs automatically.
+    function :duplicator do |typ, ev, in_ch, out_chs, req = nil, ack = nil|
+        ev = ev.posedge unless ev.is_a?(Event)
+        inner :in_ack
+        inner :in_req
         out_acks = out_chs.size.times.map { |i| inner(:"out_ack#{i}") }
         typ.inner :data
         par(ev) do
-            in_req <= 1
+            if (ack) then
+                # Output ack mode.
+                ack <= 0
+            end
+            if (req) then
+                # Input request mode.
+                in_req <= 0
+                hif(req) { in_req <= 1 }
+            else
+                # Automatic mode.
+                in_req <= 1
+            end
             out_acks.each { |ack| ack <= 0 }
             out_acks.each do |ack| 
                 hif(ack == 1) { in_req <= 0 }
@@ -30,6 +45,10 @@ module HDLRuby::High::Std
                 end
                 hif (out_acks.reduce(_1) { |sum,ack| ack & sum }) do
                     out_acks.each { |ack| ack <= 0 }
+                    if (ack) then
+                        # Output ack mode.
+                        ack <= 1
+                    end
                 end
             end
         end
@@ -37,7 +56,7 @@ module HDLRuby::High::Std
 
     # Function for generating a connector that merges the output of
     # channels +in_chs+ and connects the result to channel +out_ch+ with
-    # data of +typ+.
+    # data of types from +typs+.
     # The merge is done according to event +ev+.
     function :merger do |typs, ev, in_chs, out_ch|
         ev = ev.posedge unless ev.is_a?(Event)
@@ -63,5 +82,48 @@ module HDLRuby::High::Std
     end
 
 
+    # Function for generating a connector that serialize to the output of
+    # channels +in_chs+ and connects the result to channel +out_ch+ with
+    # data of +typ+.
+    # The merge is done according to event +ev+.
+    function :serializer do |typ, ev, in_chs, out_ch|
+        ev = ev.posedge unless ev.is_a?(Event)
+        size = in_chs.size
+        inner :out_ack
+        # in_reqs = size.times.map { |i| inner(:"in_req#{i}") }
+        in_acks = size.times.map { |i| inner(:"in_ack#{i}") }
+        datas =   size.times.map { |i| typ.inner(:"data#{i}") }
+        # The inpt channel selector
+        [size.width].inner :idx
+        inner :reading
+        par(ev) do
+            # in_reqs.each { |req| req <= 1 }
+            idx <= 0
+            reading <= 0
+            out_ack <= 0
+            hif(idx == size-1) { in_acks.each { |ack| ack <= 0 } }
+            # hif((idx == 0) & (in_reqs.reduce(_1) { |sum,req| req & sum })) do
+            hif(idx == 0) do
+                hif(~reading) do
+                    size.times { |i| in_acks[i] <= 0 }
+                end
+                reading <= 1
+                in_chs.each_with_index do |ch,i|
+                    hif(~in_acks[i]) do
+                        ch.read(datas[i]) { in_acks[i] <= 1 }
+                    end
+                end
+            end
+            hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
+                hcase(idx)
+                datas.each_with_index do |data,i|
+                    hwhen(i) do
+                        out_ch.write(data) { idx <= idx + 1; out_ack <= 1 }
+                    end
+                end
+            end
+        end
+    end
+
 
 end 

data/lib/HDLRuby/std/memory.rb

@@ -289,9 +289,10 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
             rst  = send(rst_name)
             top_block.unshift do
                 # Initialize the address so that the next access is at address 0.
-                hif(rst==1) { abus_r <= -1 }
-                # Reset so switch of the access trigger.
-                trig_r <= 0
+                # hif(rst==1) { abus_r <= -1 }
+                # # Reset so switch of the access trigger.
+                # trig_r <= 0
+                hif(rst==1) { abus_r <= -1; trig_r <= 0 }
             end
             # The read procedure.
         #     par do
@@ -317,6 +318,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                         # blk.call if blk
                         seq do
                             # abus_r <= abus_r + 1
+                            trig_r <= 0
                             target <= dbus_r
                             blk.call if blk
                         end
@@ -1704,6 +1706,127 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
 
 end
 
+
+# Queue memory of +size+ elements of +typ+ typ, syncrhonized on +clk+
+# (positive and negative edges) and reset on +rst+.
+# At each rising edge of +clk+ a read and a write is guaranteed to be
+# completed provided they are triggered.
+#
+# NOTE: this channel does not have any branch.
+HDLRuby::High::Std.channel(:mem_queue) do |typ,size,clk,rst|
+    # The inner buffer of the queue.
+    typ[-size].inner :buffer
+    # The read and write pointers.
+    [size.width].inner :rptr, :wptr
+    # The read and write command signals.
+    inner :rreq, :wreq
+    # The read and write ack signals.
+    inner :rack, :wack
+    # The read/write data registers.
+    typ.inner :rdata, :wdata
+
+    # The flags telling of the channel is synchronized
+    inner :rsync, :wsync
+
+    # The process handling the decoupled access to the buffer.
+    par(clk.posedge) do
+        hif(rst) { rptr <= 0; wptr <= 0 }
+        helse do
+            hif(~rsync) do
+                hif (~rreq) { rack <= 0 }
+                hif(rreq & (~rack) & (rptr != wptr)) do
+                    rdata <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    rack <= 1
+                end
+            end
+
+            hif(~wsync) do
+                hif (~wreq) { wack <= 0 }
+                hif(wreq & (~wack) & (((wptr+1) % size) != rptr)) do
+                    buffer[wptr] <= wdata
+                    wptr <= (wptr + 1) % size
+                    wack <= 1
+                end
+            end
+        end
+    end
+
+    reader_output :rreq, :rptr, :rsync
+    reader_input :rdata, :rack, :wptr, :buffer
+
+    # The read primitive.
+    reader do |blk,target|
+        if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
+            # Same clk event, synchrone case: perform a direct access.
+            # Now perform the access.
+            top_block.unshift do
+                rsync <= 1
+                rreq <= 0
+            end
+            seq do
+                hif(rptr != wptr) do
+                    # target <= rdata
+                    target <= buffer[rptr]
+                    rptr <= (rptr + 1) % size
+                    blk.call if blk
+                end
+            end
+        else
+            # Different clk event, perform a decoupled access.
+            top_block.unshift do
+                rsync <= 0
+                rreq <= 0
+            end
+            par do
+                hif (~rack) { rreq <= 1 }
+                helsif(rreq) do
+                    rreq <= 0
+                    target <= rdata
+                    blk.call if blk
+                end
+            end
+        end
+    end
+
+    writer_output :wreq, :wdata, :wptr, :wsync, :buffer
+    writer_input :wack, :rptr
+
+    # The write primitive.
+    writer do |blk,target|
+        if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
+            # Same clk event, synchrone case: perform a direct access.
+            top_block.unshift do
+                wsync <= 1
+                wreq <= 0
+            end
+            hif(((wptr+1) % size) != rptr) do
+                buffer[wptr] <= target
+                wptr <= (wptr + 1) % size
+                blk.call if blk
+            end
+        else
+            # Different clk event, asynchrone case: perform a decoupled access.
+            top_block.unshift do
+                wsync <= 0
+                wreq <= 0
+            end
+            seq do
+                hif (~wack) do
+                    wreq <= 1
+                    wdata <= target
+                end
+                helsif(wreq) do
+                    wreq <= 0
+                    blk.call if blk
+                end
+            end
+        end
+    end
+end
+
+
+
 # HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
 #     # Ensure typ is a type.
 #     typ = typ.to_type

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.17"
+  VERSION = "2.4.22"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.17
+  version: 2.4.22
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-11-29 00:00:00.000000000 Z
+date: 2021-01-01 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -126,6 +126,7 @@ files:
 - lib/HDLRuby/hdr_samples/with_channel.rb
 - lib/HDLRuby/hdr_samples/with_class.rb
 - lib/HDLRuby/hdr_samples/with_connector.rb
+- lib/HDLRuby/hdr_samples/with_connector_memory.rb
 - lib/HDLRuby/hdr_samples/with_decoder.rb
 - lib/HDLRuby/hdr_samples/with_fixpoint.rb
 - lib/HDLRuby/hdr_samples/with_fsm.rb