HDLRuby 2.4.17 → 2.4.22
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/rom.rb +4 -2
- data/lib/HDLRuby/hdr_samples/with_connector.rb +47 -7
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +102 -0
- data/lib/HDLRuby/hruby_low.rb +11 -1
- data/lib/HDLRuby/hruby_verilog.rb +10 -3
- data/lib/HDLRuby/std/connector.rb +67 -5
- data/lib/HDLRuby/std/memory.rb +126 -3
- data/lib/HDLRuby/version.rb +1 -1
- metadata +3 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: bd32be1a749a209488dea4e2d6d05c8c90a2a181ce48575288e33dc65c25ff02
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data.tar.gz: fc615ba447dc1fe712b2620f39d4f6fbbc1a5a698efa2c38b0ca4f075dc5a53f
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 6b81a944107060ac2844260d83d90cac747decf72b3facf9fa06bb4453267679de12dbbc72c08a3016701a304ef1c1941b7689358e125cd00d1112f028e302cb
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data.tar.gz: 369b9864dc3504ab0536c6e3a1df19b70cda921f46c1680bfdf7b78087348f93864285dada62e52db9ab105b15510cb98c1054bfd870d01ee13913e3d5216d4e
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signed[7..0].typedef(:typ)
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# Describes an 8-bit data 4-bit address ROM.
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system :rom4_8 do
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[2..0].input :addr
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[7..0].output :data0,:data1,:data2
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bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
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-
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-
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signed[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
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typ[-8].constant content2: (8).times.to_a
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data0 <= content0[addr]
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data1 <= content1[addr]
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@@ -125,9 +125,12 @@ end
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# Module for testing the connector.
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system :with_connectors do
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inner :clk, :rst
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-
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+
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# First tester.
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[4].inner :counter
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[4*4].inner :res
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inner :ack_in, :ack_out
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inner :dup_req, :dup_ack
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# The input queue.
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queue(bit[4],4,clk,rst).(:in_qu)
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@@ -141,11 +144,27 @@ system :with_connectors do
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queue(bit[4*4],4,clk,rst).(:out_qu)
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# Connect the input queue to the middle queues.
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duplicator(bit[4],clk.negedge,in_qu,mid_qus)
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duplicator(bit[4],clk.negedge,in_qu,mid_qus,dup_req,dup_ack)
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# Connect the middle queues to the output queue.
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merger([bit[4]]*4,clk.negedge,mid_qus,out_qu)
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# Second tester.
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[4].inner :counterb
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[4].inner :resb
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inner :ack_inb0, :ack_inb1, :ack_outb
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# The input queues.
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queue(bit[4],4,clk,rst).(:in_qub0)
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queue(bit[4],4,clk,rst).(:in_qub1)
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# The output queue.
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queue(bit[4],4,clk,rst).(:out_qub)
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# Connect then with a serializer.
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serializer(bit[4],clk.negedge,[in_qub0,in_qub1],out_qub)
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# # Slow version, always work
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# par(clk.posedge) do
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# ack_in <= 0
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@@ -171,25 +190,39 @@ system :with_connectors do
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# Fast version but assumes connected channels are blocking
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par(clk.posedge) do
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ack_in <= 0
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-
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ack_inb0 <= 0
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ack_inb1 <= 0
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hif(rst) { counter <= 0; counterb <= 0 }
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helse do
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in_qu.write(counter) do
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ack_in <= 1
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counter <= counter + 1
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end
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hif(ack_in) do
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-
# mid_qu0.read(res_0)
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# mid_qu1.read(res_1)
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# mid_qu2.read(res_2)
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# mid_qu3.read(res_3)
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out_qu.read(res)
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end
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hif(~ack_inb0) do
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in_qub0.write(counterb) do
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ack_inb0 <= 1
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counterb <= counterb + 1
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end
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end
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helse do
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in_qub1.write(counterb) do
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ack_inb1 <= 1
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counterb <= counterb + 1
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end
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end
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hif(ack_inb0 | ack_inb1) do
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out_qub.read(resb)
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end
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end
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end
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timed do
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clk <= 0
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rst <= 0
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dup_req <= 0
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!10.ns
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clk <= 1
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!10.ns
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@@ -204,6 +237,13 @@ system :with_connectors do
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!10.ns
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clk <= 0
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rst <= 0
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4.times do
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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end
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dup_req <= 1
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16.times do
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!10.ns
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clk <= 1
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@@ -0,0 +1,102 @@
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require 'std/memory.rb'
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require "std/fixpoint.rb"
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require 'std/channel.rb'
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require 'std/connector.rb'
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include HDLRuby::High::Std
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system :channel_connector do
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# データ型の宣言
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integer_width = 4 # 整数部のビット幅
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decimal_width = 4 # 実数部のビット幅
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address_width = 4 # lutのアドレスのビット幅
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typ = signed[integer_width + decimal_width] # データ型
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inputs_x = _00010011
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inputs_h = _10100001
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columns = [2, 2, 1]
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inner :clk, # clock
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:rst, # reset
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:req, # request
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:fill # 入力値のメモリへの書き込み
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# inputs_x = quantize(inputs_x, typ, decimal_width)
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# inputs_h = quantize(inputs_h, typ, decimal_width)
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mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_x) # 入力値を格納するrom(x)
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mem_rom(typ, columns[0], clk, rst, inputs_h, rinc: :rst, winc: :rst).(:rom_inputs_h) # 入力値を格納するrom(h)
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mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_serializer) #
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mem_dual(typ, columns[0]*2, clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_merger) #
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reader_inputs_x = rom_inputs_x.branch(:rinc) #入力値xの読みだし用branch
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reader_inputs_h = rom_inputs_h.branch(:rinc) #入力値hの読みだし用branch
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writer_inputs_serializer = ram_inputs_serializer.branch(:winc) #入力値を合成した値の書き込み用branch
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writer_inputs_meger = ram_inputs_merger.branch(:winc) #入力値を合成した値の書き込み用branch
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serializer(typ,clk.negedge,[reader_inputs_x,reader_inputs_h],writer_inputs_serializer)
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mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_r) # 入力値を格納するrom(x)
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mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_duplicator0) #
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mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_duplicator1) #
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reader_inputs_r = rom_inputs_r.branch(:rinc)
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writer_duplicator0 = ram_duplicator0.branch(:winc)
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writer_duplicator1 = ram_duplicator1.branch(:winc)
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duplicator(typ,clk.posedge,reader_inputs_r,[writer_duplicator0, writer_duplicator1])
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timed do
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# リセット
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clk <= 0
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rst <= 0
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req <= 0
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fill <= 0
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!10.ps
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# メモリ読み出し位置の初期化
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rst <= 1
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!10.ps
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clk <= 1
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!10.ps
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clk <= 0
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!10.ps
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clk <= 1
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!10.ps
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# パラメータのメモリへの書き込み
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clk <= 0
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rst <= 0
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fill <= 1
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!10.ps
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10.times do |i|
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clk <= 1
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!10.ps
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clk <= 0
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!10.ps
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end
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fill <= 0
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clk <= 1
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!10.ps
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# 計算の実行
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clk <= 0
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req <= 1
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!10.ps
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clk <= 1
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!10.ps
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clk <= 0
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!10.ps
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30.times do
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clk <= 1
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!10.ps
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clk <= 0
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!10.ps
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end
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end
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end
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data/lib/HDLRuby/hruby_low.rb
CHANGED
@@ -1183,6 +1183,11 @@ module HDLRuby::Low
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return false
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end
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# Tells if the type of of vector kind.
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def vector?
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return false
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end
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# Gets the bitwidth of the type, by default 0.
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# Bit, signed, unsigned and Float base have a width of 1.
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def width
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# Sets the delegations
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self.extend Forwardable
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[ :signed?, :unsigned?, :fixed?, :float?, :leaf?,
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[ :signed?, :unsigned?, :fixed?, :float?, :leaf?, :vector?,
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:width, :range?, :range, :base?, :base, :types?,
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:get_all_types, :get_type, :each, :each_type,
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:regular?,
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# The base type of the vector
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attr_reader :base
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# Tells if the type of of vector kind.
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def vector?
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return true
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end
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# Tells if the type has a base.
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def base?
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return true
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module HDLRuby::Low
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# The list of base types used both in verilog and HDLRuby
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VERILOG_BASE_TYPES = ["signed"]
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# Sample of very handy for programming.
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# puts "class=#{self.yes.class}" # Confirm class of self.yes.
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# puts "methods=#{self.right.methods}" # Confirm method of self.right.
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class TypeVector
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# Converts the system to Verilog code.
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def to_verilog
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if self.base.name.to_s != "bit"
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# if self.base.name.to_s != "bit"
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if VERILOG_BASE_TYPES.include?(self.base.name.to_s)
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return " #{self.base.name.to_s}[#{self.range.first}:#{self.range.last}]"
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end
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return " [#{self.range.first}:#{self.range.last}]"
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end
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# And the array types signals.
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self.each_signal do |sig|
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regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
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# regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
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regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
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end
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self.each_inner do |sig|
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regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
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# regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
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regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
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end
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# Code generation
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# channel +in_ch+ and connect it to channels +out_chs+ with data of
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# +typ+.
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# The duplication is done according to event +ev+.
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-
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# The optional req and ack arguments are the signals for controlling the
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# duplicator using a handshake protocol. If set to nil, the duplicator
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# runs automatically.
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function :duplicator do |typ, ev, in_ch, out_chs, req = nil, ack = nil|
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ev = ev.posedge unless ev.is_a?(Event)
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inner :in_ack
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inner :in_req
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out_acks = out_chs.size.times.map { |i| inner(:"out_ack#{i}") }
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typ.inner :data
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par(ev) do
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-
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if (ack) then
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# Output ack mode.
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ack <= 0
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end
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if (req) then
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# Input request mode.
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in_req <= 0
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hif(req) { in_req <= 1 }
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else
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# Automatic mode.
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in_req <= 1
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end
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out_acks.each { |ack| ack <= 0 }
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out_acks.each do |ack|
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hif(ack == 1) { in_req <= 0 }
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@@ -30,6 +45,10 @@ module HDLRuby::High::Std
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end
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31
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hif (out_acks.reduce(_1) { |sum,ack| ack & sum }) do
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32
47
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out_acks.each { |ack| ack <= 0 }
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48
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if (ack) then
|
49
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# Output ack mode.
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50
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ack <= 1
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51
|
+
end
|
33
52
|
end
|
34
53
|
end
|
35
54
|
end
|
@@ -37,7 +56,7 @@ module HDLRuby::High::Std
|
|
37
56
|
|
38
57
|
# Function for generating a connector that merges the output of
|
39
58
|
# channels +in_chs+ and connects the result to channel +out_ch+ with
|
40
|
-
# data of +
|
59
|
+
# data of types from +typs+.
|
41
60
|
# The merge is done according to event +ev+.
|
42
61
|
function :merger do |typs, ev, in_chs, out_ch|
|
43
62
|
ev = ev.posedge unless ev.is_a?(Event)
|
@@ -63,5 +82,48 @@ module HDLRuby::High::Std
|
|
63
82
|
end
|
64
83
|
|
65
84
|
|
85
|
+
# Function for generating a connector that serialize to the output of
|
86
|
+
# channels +in_chs+ and connects the result to channel +out_ch+ with
|
87
|
+
# data of +typ+.
|
88
|
+
# The merge is done according to event +ev+.
|
89
|
+
function :serializer do |typ, ev, in_chs, out_ch|
|
90
|
+
ev = ev.posedge unless ev.is_a?(Event)
|
91
|
+
size = in_chs.size
|
92
|
+
inner :out_ack
|
93
|
+
# in_reqs = size.times.map { |i| inner(:"in_req#{i}") }
|
94
|
+
in_acks = size.times.map { |i| inner(:"in_ack#{i}") }
|
95
|
+
datas = size.times.map { |i| typ.inner(:"data#{i}") }
|
96
|
+
# The inpt channel selector
|
97
|
+
[size.width].inner :idx
|
98
|
+
inner :reading
|
99
|
+
par(ev) do
|
100
|
+
# in_reqs.each { |req| req <= 1 }
|
101
|
+
idx <= 0
|
102
|
+
reading <= 0
|
103
|
+
out_ack <= 0
|
104
|
+
hif(idx == size-1) { in_acks.each { |ack| ack <= 0 } }
|
105
|
+
# hif((idx == 0) & (in_reqs.reduce(_1) { |sum,req| req & sum })) do
|
106
|
+
hif(idx == 0) do
|
107
|
+
hif(~reading) do
|
108
|
+
size.times { |i| in_acks[i] <= 0 }
|
109
|
+
end
|
110
|
+
reading <= 1
|
111
|
+
in_chs.each_with_index do |ch,i|
|
112
|
+
hif(~in_acks[i]) do
|
113
|
+
ch.read(datas[i]) { in_acks[i] <= 1 }
|
114
|
+
end
|
115
|
+
end
|
116
|
+
end
|
117
|
+
hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
|
118
|
+
hcase(idx)
|
119
|
+
datas.each_with_index do |data,i|
|
120
|
+
hwhen(i) do
|
121
|
+
out_ch.write(data) { idx <= idx + 1; out_ack <= 1 }
|
122
|
+
end
|
123
|
+
end
|
124
|
+
end
|
125
|
+
end
|
126
|
+
end
|
127
|
+
|
66
128
|
|
67
129
|
end
|
data/lib/HDLRuby/std/memory.rb
CHANGED
@@ -289,9 +289,10 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
289
289
|
rst = send(rst_name)
|
290
290
|
top_block.unshift do
|
291
291
|
# Initialize the address so that the next access is at address 0.
|
292
|
-
hif(rst==1) { abus_r <= -1 }
|
293
|
-
# Reset so switch of the access trigger.
|
294
|
-
trig_r <= 0
|
292
|
+
# hif(rst==1) { abus_r <= -1 }
|
293
|
+
# # Reset so switch of the access trigger.
|
294
|
+
# trig_r <= 0
|
295
|
+
hif(rst==1) { abus_r <= -1; trig_r <= 0 }
|
295
296
|
end
|
296
297
|
# The read procedure.
|
297
298
|
# par do
|
@@ -317,6 +318,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
317
318
|
# blk.call if blk
|
318
319
|
seq do
|
319
320
|
# abus_r <= abus_r + 1
|
321
|
+
trig_r <= 0
|
320
322
|
target <= dbus_r
|
321
323
|
blk.call if blk
|
322
324
|
end
|
@@ -1704,6 +1706,127 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1704
1706
|
|
1705
1707
|
end
|
1706
1708
|
|
1709
|
+
|
1710
|
+
# Queue memory of +size+ elements of +typ+ typ, syncrhonized on +clk+
|
1711
|
+
# (positive and negative edges) and reset on +rst+.
|
1712
|
+
# At each rising edge of +clk+ a read and a write is guaranteed to be
|
1713
|
+
# completed provided they are triggered.
|
1714
|
+
#
|
1715
|
+
# NOTE: this channel does not have any branch.
|
1716
|
+
HDLRuby::High::Std.channel(:mem_queue) do |typ,size,clk,rst|
|
1717
|
+
# The inner buffer of the queue.
|
1718
|
+
typ[-size].inner :buffer
|
1719
|
+
# The read and write pointers.
|
1720
|
+
[size.width].inner :rptr, :wptr
|
1721
|
+
# The read and write command signals.
|
1722
|
+
inner :rreq, :wreq
|
1723
|
+
# The read and write ack signals.
|
1724
|
+
inner :rack, :wack
|
1725
|
+
# The read/write data registers.
|
1726
|
+
typ.inner :rdata, :wdata
|
1727
|
+
|
1728
|
+
# The flags telling of the channel is synchronized
|
1729
|
+
inner :rsync, :wsync
|
1730
|
+
|
1731
|
+
# The process handling the decoupled access to the buffer.
|
1732
|
+
par(clk.posedge) do
|
1733
|
+
hif(rst) { rptr <= 0; wptr <= 0 }
|
1734
|
+
helse do
|
1735
|
+
hif(~rsync) do
|
1736
|
+
hif (~rreq) { rack <= 0 }
|
1737
|
+
hif(rreq & (~rack) & (rptr != wptr)) do
|
1738
|
+
rdata <= buffer[rptr]
|
1739
|
+
rptr <= (rptr + 1) % depth
|
1740
|
+
rack <= 1
|
1741
|
+
end
|
1742
|
+
end
|
1743
|
+
|
1744
|
+
hif(~wsync) do
|
1745
|
+
hif (~wreq) { wack <= 0 }
|
1746
|
+
hif(wreq & (~wack) & (((wptr+1) % size) != rptr)) do
|
1747
|
+
buffer[wptr] <= wdata
|
1748
|
+
wptr <= (wptr + 1) % size
|
1749
|
+
wack <= 1
|
1750
|
+
end
|
1751
|
+
end
|
1752
|
+
end
|
1753
|
+
end
|
1754
|
+
|
1755
|
+
reader_output :rreq, :rptr, :rsync
|
1756
|
+
reader_input :rdata, :rack, :wptr, :buffer
|
1757
|
+
|
1758
|
+
# The read primitive.
|
1759
|
+
reader do |blk,target|
|
1760
|
+
if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
|
1761
|
+
# Same clk event, synchrone case: perform a direct access.
|
1762
|
+
# Now perform the access.
|
1763
|
+
top_block.unshift do
|
1764
|
+
rsync <= 1
|
1765
|
+
rreq <= 0
|
1766
|
+
end
|
1767
|
+
seq do
|
1768
|
+
hif(rptr != wptr) do
|
1769
|
+
# target <= rdata
|
1770
|
+
target <= buffer[rptr]
|
1771
|
+
rptr <= (rptr + 1) % size
|
1772
|
+
blk.call if blk
|
1773
|
+
end
|
1774
|
+
end
|
1775
|
+
else
|
1776
|
+
# Different clk event, perform a decoupled access.
|
1777
|
+
top_block.unshift do
|
1778
|
+
rsync <= 0
|
1779
|
+
rreq <= 0
|
1780
|
+
end
|
1781
|
+
par do
|
1782
|
+
hif (~rack) { rreq <= 1 }
|
1783
|
+
helsif(rreq) do
|
1784
|
+
rreq <= 0
|
1785
|
+
target <= rdata
|
1786
|
+
blk.call if blk
|
1787
|
+
end
|
1788
|
+
end
|
1789
|
+
end
|
1790
|
+
end
|
1791
|
+
|
1792
|
+
writer_output :wreq, :wdata, :wptr, :wsync, :buffer
|
1793
|
+
writer_input :wack, :rptr
|
1794
|
+
|
1795
|
+
# The write primitive.
|
1796
|
+
writer do |blk,target|
|
1797
|
+
if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
|
1798
|
+
# Same clk event, synchrone case: perform a direct access.
|
1799
|
+
top_block.unshift do
|
1800
|
+
wsync <= 1
|
1801
|
+
wreq <= 0
|
1802
|
+
end
|
1803
|
+
hif(((wptr+1) % size) != rptr) do
|
1804
|
+
buffer[wptr] <= target
|
1805
|
+
wptr <= (wptr + 1) % size
|
1806
|
+
blk.call if blk
|
1807
|
+
end
|
1808
|
+
else
|
1809
|
+
# Different clk event, asynchrone case: perform a decoupled access.
|
1810
|
+
top_block.unshift do
|
1811
|
+
wsync <= 0
|
1812
|
+
wreq <= 0
|
1813
|
+
end
|
1814
|
+
seq do
|
1815
|
+
hif (~wack) do
|
1816
|
+
wreq <= 1
|
1817
|
+
wdata <= target
|
1818
|
+
end
|
1819
|
+
helsif(wreq) do
|
1820
|
+
wreq <= 0
|
1821
|
+
blk.call if blk
|
1822
|
+
end
|
1823
|
+
end
|
1824
|
+
end
|
1825
|
+
end
|
1826
|
+
end
|
1827
|
+
|
1828
|
+
|
1829
|
+
|
1707
1830
|
# HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
1708
1831
|
# # Ensure typ is a type.
|
1709
1832
|
# typ = typ.to_type
|
data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: HDLRuby
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 2.4.
|
4
|
+
version: 2.4.22
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Lovic Gauthier
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2021-01-01 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|
@@ -126,6 +126,7 @@ files:
|
|
126
126
|
- lib/HDLRuby/hdr_samples/with_channel.rb
|
127
127
|
- lib/HDLRuby/hdr_samples/with_class.rb
|
128
128
|
- lib/HDLRuby/hdr_samples/with_connector.rb
|
129
|
+
- lib/HDLRuby/hdr_samples/with_connector_memory.rb
|
129
130
|
- lib/HDLRuby/hdr_samples/with_decoder.rb
|
130
131
|
- lib/HDLRuby/hdr_samples/with_fixpoint.rb
|
131
132
|
- lib/HDLRuby/hdr_samples/with_fsm.rb
|