HDLRuby 2.4.15 → 2.4.17

data/lib/HDLRuby/hdr_samples/make_multi_channels_v.rb

@@ -0,0 +1,24 @@
+#!/usr/bin/ruby
+# Script for generating the vcd files.
+
+# The configuration scenarii
+$scenarii = [
+              [:_clk2_clk2,      :register],    #  0
+              [:_clk2_nclk2,     :register],    #  1
+              [:_clk2_clk3,      :register],    #  2
+              [:_clk3_clk2,      :register],    #  3
+              [:_clk2_clk2,      :handshake],   #  4
+              [:_clk2_nclk2,     :handshake],   #  5
+              [:_clk2_clk3,      :handshake],   #  6
+              [:_clk3_clk2,      :handshake],   #  7
+              [:clk2_clk2_clk2,  :queue],       #  8
+              [:clk2_clk2_nclk2, :queue],       #  9
+              [:clk1_clk2_clk3,  :queue],       # 10
+              [:clk3_clk2_clk1,  :queue],       # 11
+              [:clk2_clk3_clk1,  :queue],       # 12
+              [:clk2_clk1_clk3,  :queue],       # 13
+            ]
+$scenarii.each_with_index do |scenarii,i|
+    puts "scenario: [#{i}] #{scenarii}"
+    `bundle exec ../hdrcc.rb --verilog with_multi_channels.rb WithMultiChannelPaper.V#{i} #{i}`
+end

data/lib/HDLRuby/hdr_samples/with_multi_channels.rb

@@ -23,12 +23,6 @@ channel(:queue) do |typ,depth,clk,rst|
     par(clk.posedge) do
         hif(rst) { rptr <= 0; wptr <= 0 }
         helse do
-            # hif(rsync) do
-            #     hif(rptr != wptr) do
-            #         rdata <= buffer[rptr]
-            #     end
-            # end
-            # helse do
             hif(~rsync) do
                 hif (~rreq) { rack <= 0 }
                 hif(rreq & (~rack) & (rptr != wptr)) do
@@ -38,10 +32,6 @@ channel(:queue) do |typ,depth,clk,rst|
                 end
             end
 
-            # hif(wsync) do
-            #     buffer[wptr] <= wdata
-            # end
-            # helse do
             hif(~wsync) do
                 hif (~wreq) { wack <= 0 }
                 hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
@@ -67,7 +57,6 @@ channel(:queue) do |typ,depth,clk,rst|
             end
             seq do
                 hif(rptr != wptr) do
-                    # target <= rdata
                     target <= buffer[rptr]
                     rptr <= (rptr + 1) % depth
                     blk.call if blk
@@ -102,7 +91,6 @@ channel(:queue) do |typ,depth,clk,rst|
                 wreq <= 0
             end
             hif(((wptr+1) % depth) != rptr) do
-                # wdata <= target
                 buffer[wptr] <= target
                 wptr <= (wptr + 1) % depth
                 blk.call if blk

data/lib/HDLRuby/hruby_tools.rb

@@ -29,8 +29,14 @@ module HDLRuby
     class ::Integer
 
         # Gets the bit width
+        # NOTE: returns infinity if the number is negative.
         def width
-            return Math.log2(self+1).ceil
+            return self >= 0 ? Math.log2(self+1).ceil : 1.0/0.0
+        end
+
+        # Tells if the value is a power of 2.
+        def pow2?
+            return self > 0 && (self & (self - 1) == 0)
         end
     end
 

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.15"
+  VERSION = "2.4.17"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.15
+  version: 2.4.17
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-11-20 00:00:00.000000000 Z
+date: 2020-11-29 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -66,6 +66,10 @@ files:
 - lib/HDLRuby/alcc.rb
 - lib/HDLRuby/backend/hruby_allocator.rb
 - lib/HDLRuby/backend/hruby_c_allocator.rb
+- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v
+- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_213.v
+- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v
+- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_rg_23.v
 - lib/HDLRuby/hdr_samples/adder.rb
 - lib/HDLRuby/hdr_samples/adder_assign_error.rb
 - lib/HDLRuby/hdr_samples/adder_bench.rb
@@ -84,6 +88,7 @@ files:
 - lib/HDLRuby/hdr_samples/include.rb
 - lib/HDLRuby/hdr_samples/instance_open.rb
 - lib/HDLRuby/hdr_samples/linear_test.rb
+- lib/HDLRuby/hdr_samples/make_multi_channels_v.rb
 - lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb
 - lib/HDLRuby/hdr_samples/mei8.rb
 - lib/HDLRuby/hdr_samples/mei8_bench.rb