HDLRuby 2.4.12 → 2.4.14

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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@@ -3,23 +3,23 @@
3
3
 
4
4
  # The configuration scenarii
5
5
  $scenarii = [
6
- [:sync, :register], # 00
7
- [:sync, :handshake], # 01
8
- [:sync, :queue], # 02
9
- [:nsync, :register], # 03
10
- [:nsync, :handshake], # 04
11
- [:nsync, :queue], # 05
12
- [:async, :register], # 06
13
- [:async, :handshake], # 07
14
- [:async, :queue], # 08
15
- [:proco, :register], # 09
16
- [:proco, :handshake], # 10
17
- [:proco, :queue], # 11
18
- [:double,:register], # 12
19
- [:double,:handshake], # 13
20
- [:double,:queue] # 14
6
+ [:_clk2_clk2, :register], # 0
7
+ [:_clk2_nclk2, :register], # 1
8
+ [:_clk2_clk3, :register], # 2
9
+ [:_clk3_clk2, :register], # 3
10
+ [:_clk2_clk2, :handshake], # 4
11
+ [:_clk2_nclk2, :handshake], # 5
12
+ [:_clk2_clk3, :handshake], # 6
13
+ [:_clk3_clk2, :handshake], # 7
14
+ [:clk2_clk2_clk2, :queue], # 8
15
+ [:clk2_clk2_nclk2, :queue], # 9
16
+ [:clk1_clk2_clk3, :queue], # 10
17
+ [:clk3_clk2_clk1, :queue], # 11
18
+ [:clk2_clk3_clk1, :queue], # 12
19
+ [:clk2_clk1_clk3, :queue], # 13
21
20
  ]
22
- (0..11).each do |i|
21
+ $scenarii.each_with_index do |scenarii,i|
22
+ puts "scenario: [#{i}] #{scenarii}"
23
23
  `bundle exec ../hdrcc.rb -S --vcd with_multi_channels.rb WithMultiChannelPaper #{i}`
24
- `mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{$scenarii[i][0]}_#{$scenarii[i][1]}.vcd`
24
+ `mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{scenarii[0]}_#{scenarii[1]}.vcd`
25
25
  end
@@ -0,0 +1,207 @@
1
+ require 'std/channel.rb'
2
+ require 'std/connector.rb'
3
+
4
+ include HDLRuby::High::Std
5
+
6
+ # Sample for testing the connectors of channels.
7
+
8
+ # Channel describing a buffered queue storing data of +typ+ type of +depth+,
9
+ # synchronized through clk and reset on +rst+.
10
+ channel(:queue) do |typ,depth,clk,rst|
11
+ # The inner buffer of the queue.
12
+ typ[-depth].inner :buffer
13
+ # The read and write pointers.
14
+ [depth.width].inner :rptr, :wptr
15
+ # The read and write command signals.
16
+ inner :rreq, :wreq
17
+ # The read and write ack signals.
18
+ inner :rack, :wack
19
+ # The read/write data registers.
20
+ typ.inner :rdata, :wdata
21
+
22
+ # The flags telling of the channel is synchronized
23
+ inner :rsync, :wsync
24
+
25
+ # The process handling the decoupled access to the buffer.
26
+ par(clk.posedge) do
27
+ hif(rst) { rptr <= 0; wptr <= 0 }
28
+ helse do
29
+ hif(~rsync) do
30
+ hif (~rreq) { rack <= 0 }
31
+ hif(rreq & (~rack) & (rptr != wptr)) do
32
+ rdata <= buffer[rptr]
33
+ rptr <= (rptr + 1) % depth
34
+ rack <= 1
35
+ end
36
+ end
37
+
38
+ hif(~wsync) do
39
+ hif (~wreq) { wack <= 0 }
40
+ hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
41
+ buffer[wptr] <= wdata
42
+ wptr <= (wptr + 1) % depth
43
+ wack <= 1
44
+ end
45
+ end
46
+ end
47
+ end
48
+
49
+ reader_output :rreq, :rptr, :rsync
50
+ reader_input :rdata, :rack, :wptr, :buffer
51
+
52
+ # The read primitive.
53
+ reader do |blk,target|
54
+ if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
55
+ # Same clk event, synchrone case: perform a direct access.
56
+ # Now perform the access.
57
+ top_block.unshift do
58
+ rsync <= 1
59
+ rreq <= 0
60
+ end
61
+ seq do
62
+ hif(rptr != wptr) do
63
+ # target <= rdata
64
+ target <= buffer[rptr]
65
+ rptr <= (rptr + 1) % depth
66
+ blk.call if blk
67
+ end
68
+ end
69
+ else
70
+ # Different clk event, perform a decoupled access.
71
+ top_block.unshift do
72
+ rsync <= 0
73
+ rreq <= 0
74
+ end
75
+ par do
76
+ hif (~rack) { rreq <= 1 }
77
+ helsif(rreq) do
78
+ rreq <= 0
79
+ target <= rdata
80
+ blk.call if blk
81
+ end
82
+ end
83
+ end
84
+ end
85
+
86
+ writer_output :wreq, :wdata, :wptr, :wsync, :buffer
87
+ writer_input :wack, :rptr
88
+
89
+ # The write primitive.
90
+ writer do |blk,target|
91
+ if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
92
+ # Same clk event, synchrone case: perform a direct access.
93
+ top_block.unshift do
94
+ wsync <= 1
95
+ wreq <= 0
96
+ end
97
+ hif(((wptr+1) % depth) != rptr) do
98
+ buffer[wptr] <= target
99
+ wptr <= (wptr + 1) % depth
100
+ blk.call if blk
101
+ end
102
+ else
103
+ # Different clk event, asynchrone case: perform a decoupled access.
104
+ top_block.unshift do
105
+ wsync <= 0
106
+ wreq <= 0
107
+ end
108
+ seq do
109
+ hif (~wack) do
110
+ wreq <= 1
111
+ wdata <= target
112
+ end
113
+ helsif(wreq) do
114
+ wreq <= 0
115
+ blk.call if blk
116
+ end
117
+ end
118
+ end
119
+ end
120
+ end
121
+
122
+
123
+
124
+
125
+ # Module for testing the connector.
126
+ system :with_connectors do
127
+ inner :clk, :rst
128
+ [4].inner :counter, :res_0,:res_1,:res_2,:res_3
129
+ inner :ack_in, :ack_out
130
+
131
+ # The input queue.
132
+ queue(bit[4],4,clk,rst).(:in_qu)
133
+
134
+ # The first output queue.
135
+ queue(bit[4],4,clk,rst).(:out_qu0)
136
+ queue(bit[4],4,clk,rst).(:out_qu1)
137
+ queue(bit[4],4,clk,rst).(:out_qu2)
138
+ queue(bit[4],4,clk,rst).(:out_qu3)
139
+
140
+ # Connect them
141
+ duplicator([4],clk.negedge,in_qu,[out_qu0,out_qu1,out_qu2,out_qu3])
142
+
143
+ # # Slow version, always work
144
+ # par(clk.posedge) do
145
+ # ack_in <= 0
146
+ # ack_out <= 1
147
+ # hif(rst) { counter <= 0 }
148
+ # helse do
149
+ # hif(ack_out) do
150
+ # ack_out <= 0
151
+ # in_qu.write(counter) do
152
+ # ack_in <= 1
153
+ # counter <= counter + 1
154
+ # end
155
+ # end
156
+ # hif(ack_in) do
157
+ # out_qu0.read(res_0)
158
+ # out_qu1.read(res_1)
159
+ # out_qu2.read(res_2)
160
+ # out_qu3.read(res_3) { ack_out <= 1 }
161
+ # end
162
+ # end
163
+ # end
164
+
165
+ # Fast version but assumes connected channels are blocking
166
+ par(clk.posedge) do
167
+ ack_in <= 0
168
+ hif(rst) { counter <= 0 }
169
+ helse do
170
+ in_qu.write(counter) do
171
+ ack_in <= 1
172
+ counter <= counter + 1
173
+ end
174
+ hif(ack_in) do
175
+ out_qu0.read(res_0)
176
+ out_qu1.read(res_1)
177
+ out_qu2.read(res_2)
178
+ out_qu3.read(res_3)
179
+ end
180
+ end
181
+ end
182
+
183
+ timed do
184
+ clk <= 0
185
+ rst <= 0
186
+ !10.ns
187
+ clk <= 1
188
+ !10.ns
189
+ clk <= 0
190
+ rst <= 1
191
+ !10.ns
192
+ clk <= 1
193
+ !10.ns
194
+ clk <= 0
195
+ !10.ns
196
+ clk <= 1
197
+ !10.ns
198
+ clk <= 0
199
+ rst <= 0
200
+ 16.times do
201
+ !10.ns
202
+ clk <= 1
203
+ !10.ns
204
+ clk <= 0
205
+ end
206
+ end
207
+ end
@@ -10,36 +10,51 @@ channel(:queue) do |typ,depth,clk,rst|
10
10
  # The read and write pointers.
11
11
  [depth.width].inner :rptr, :wptr
12
12
  # The read and write command signals.
13
- inner :rcmd, :wcmd
13
+ inner :rreq, :wreq
14
14
  # The read and write ack signals.
15
15
  inner :rack, :wack
16
- # The ack check deactivator (for synchron accesses).
17
- inner :hrack, :hwack
18
16
  # The read/write data registers.
19
17
  typ.inner :rdata, :wdata
20
18
 
19
+ # The flags telling of the channel is synchronized
20
+ inner :rsync, :wsync
21
+
21
22
  # The process handling the decoupled access to the buffer.
22
23
  par(clk.posedge) do
23
- # rack <= 0
24
- # wack <= 0
25
- hif (~rcmd) { rack <= 0 }
26
- hif (~wcmd) { wack <= 0 }
27
24
  hif(rst) { rptr <= 0; wptr <= 0 }
28
- hif(rcmd & (hrack|~rack) & (rptr != wptr)) do
29
- rptr <= (rptr + 1) % depth
30
- rack <= 1
31
- end
32
- hif(wcmd & (hwack|~wack) & (((wptr+1) % depth) != rptr)) do
33
- buffer[wptr] <= wdata
34
- # buffer[1] <= wdata
35
- wptr <= (wptr + 1) % depth
36
- wack <= 1
25
+ helse do
26
+ # hif(rsync) do
27
+ # hif(rptr != wptr) do
28
+ # rdata <= buffer[rptr]
29
+ # end
30
+ # end
31
+ # helse do
32
+ hif(~rsync) do
33
+ hif (~rreq) { rack <= 0 }
34
+ hif(rreq & (~rack) & (rptr != wptr)) do
35
+ rdata <= buffer[rptr]
36
+ rptr <= (rptr + 1) % depth
37
+ rack <= 1
38
+ end
39
+ end
40
+
41
+ # hif(wsync) do
42
+ # buffer[wptr] <= wdata
43
+ # end
44
+ # helse do
45
+ hif(~wsync) do
46
+ hif (~wreq) { wack <= 0 }
47
+ hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
48
+ buffer[wptr] <= wdata
49
+ wptr <= (wptr + 1) % depth
50
+ wack <= 1
51
+ end
52
+ end
37
53
  end
38
54
  end
39
- par { rdata <= buffer[rptr] }
40
55
 
41
- reader_output :rcmd, :rptr, :hrack
42
- reader_input :rdata, :rack
56
+ reader_output :rreq, :rptr, :rsync
57
+ reader_input :rdata, :rack, :wptr, :buffer
43
58
 
44
59
  # The read primitive.
45
60
  reader do |blk,target|
@@ -47,66 +62,66 @@ channel(:queue) do |typ,depth,clk,rst|
47
62
  # Same clk event, synchrone case: perform a direct access.
48
63
  # Now perform the access.
49
64
  top_block.unshift do
50
- rcmd <= 0
51
- hrack <= 1
65
+ rsync <= 1
66
+ rreq <= 0
52
67
  end
53
68
  seq do
54
- rptr <= (rptr + 1) % depth
55
- target <= rdata
56
- blk.call if blk
69
+ hif(rptr != wptr) do
70
+ # target <= rdata
71
+ target <= buffer[rptr]
72
+ rptr <= (rptr + 1) % depth
73
+ blk.call if blk
74
+ end
57
75
  end
58
76
  else
59
77
  # Different clk event, perform a decoupled access.
60
78
  top_block.unshift do
61
- rcmd <= 0
62
- hrack <= 0
63
- hif(rack) do
64
- blk.call if blk
65
- end
79
+ rsync <= 0
80
+ rreq <= 0
66
81
  end
67
- seq do
68
- # hif(rack) do
69
- # blk.call if blk
70
- # end
71
- # helse do
72
- hif(rack==0) do
73
- rcmd <= 1
82
+ par do
83
+ hif (~rack) { rreq <= 1 }
84
+ helsif(rreq) do
85
+ rreq <= 0
74
86
  target <= rdata
87
+ blk.call if blk
75
88
  end
76
89
  end
77
90
  end
78
91
  end
79
92
 
80
- writer_output :wcmd, :wdata, :hwack
81
- writer_input :wack
93
+ writer_output :wreq, :wdata, :wptr, :wsync, :buffer
94
+ writer_input :wack, :rptr
82
95
 
83
96
  # The write primitive.
84
97
  writer do |blk,target|
85
98
  if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
86
99
  # Same clk event, synchrone case: perform a direct access.
87
100
  top_block.unshift do
88
- wcmd <= 0
89
- hwack <= 1
101
+ wsync <= 1
102
+ wreq <= 0
103
+ end
104
+ hif(((wptr+1) % depth) != rptr) do
105
+ # wdata <= target
106
+ buffer[wptr] <= target
107
+ wptr <= (wptr + 1) % depth
108
+ blk.call if blk
90
109
  end
91
- wcmd <= 1
92
- wdata <= target
93
- blk.call if blk
94
110
  else
95
111
  # Different clk event, asynchrone case: perform a decoupled access.
96
112
  top_block.unshift do
97
- wcmd <= 0
98
- hwack <= 0
99
- hif(wack) do
100
- blk.call if blk
101
- end
113
+ wsync <= 0
114
+ wreq <= 0
102
115
  end
103
116
  seq do
104
- # hif(wack) do
105
- # blk.call if blk
106
- # end
107
- # helse
108
- hif(wack==0) { wcmd <= 1 }
109
- wdata <= target
117
+ hif (~wack) do
118
+ wreq <= 1
119
+ wdata <= target
120
+ end
121
+ helsif(wreq) do
122
+ wreq <= 0
123
+ blk.call if blk
124
+ end
110
125
  end
111
126
  end
112
127
  end
@@ -181,82 +196,28 @@ channel(:handshake) do |typ|
181
196
  end
182
197
  end
183
198
 
184
- # Channel describing a handshake for transmitting data of +typ+ type, reset
185
- # by +rst+
186
- channel(:handshake2) do |typ|
187
- # The data signal.
188
- typ.inner :data
189
- # The request and acknowledge.
190
- inner :req, :ack
191
- # The write flag
192
- inner :wf
193
-
194
- reader_input :ack, :data
195
- reader_output :req
196
-
197
- # The read primitive.
198
- reader do |blk,target|
199
- top_block.unshift do
200
- req <= 0
201
- hif(ack & req == 1) do
202
- target <= data
203
- req <= 0
204
- blk.call if blk
205
- end
206
- end
207
- hif(ack == 0) do
208
- req <= 1
209
- end
210
- end
211
-
212
- writer_input :req
213
- writer_output :ack, :data
214
- writer_inout :wf
215
-
216
- # The read primitive.
217
- writer do |blk,target|
218
- top_block.unshift do
219
- ack <= 0
220
- hif(wf & req & ~ack == 1) do
221
- data <= target
222
- ack <= 1
223
- blk.call if blk
224
- end
225
- hif(~req) { wf <= 0 }
226
- end
227
- hif(~ack) do
228
- wf <= 1
229
- end
230
- end
231
- end
232
-
233
199
 
234
- # $mode = :sync
235
- # $mode = :nsync
236
- # $mode = :async
237
- # $mode = :proco # Producer / Consummer
238
- # $mode = :double # Producer and Consummer with double channels.
200
+ # $mode: channel clock, producer clock, consumer clock (n: not clock)
239
201
  # $channel = :register
240
202
  # $channel = :handshake
241
203
  # $channel = :queue
242
204
 
243
205
  # The configuration scenarii
244
206
  $scenarii = [
245
- [:sync, :register], # 0
246
- [:sync, :handshake], # 1
247
- [:sync, :queue], # 3
248
- [:nsync, :register], # 4
249
- [:nsync, :handshake], # 5
250
- [:nsync, :queue], # 6
251
- [:async, :register], # 7
252
- [:async, :handshake], # 8
253
- [:async, :queue], # 9
254
- [:proco, :register], # 10
255
- [:proco, :handshake], # 11
256
- [:proco, :queue], # 12
257
- [:double,:register], # 13
258
- [:double,:handshake], # 14
259
- [:double,:queue] # 15
207
+ [:_clk2_clk2, :register], # 0
208
+ [:_clk2_nclk2, :register], # 1
209
+ [:_clk2_clk3, :register], # 2
210
+ [:_clk3_clk2, :register], # 3
211
+ [:_clk2_clk2, :handshake], # 4
212
+ [:_clk2_nclk2, :handshake], # 5
213
+ [:_clk2_clk3, :handshake], # 6
214
+ [:_clk3_clk2, :handshake], # 7
215
+ [:clk2_clk2_clk2, :queue], # 8
216
+ [:clk2_clk2_nclk2, :queue], # 9
217
+ [:clk1_clk2_clk3, :queue], # 10
218
+ [:clk3_clk2_clk1, :queue], # 11
219
+ [:clk2_clk3_clk1, :queue], # 12
220
+ [:clk2_clk1_clk3, :queue], # 13
260
221
  ]
261
222
 
262
223
  # The configuration
@@ -266,113 +227,72 @@ puts "scenario: #{$scenarii[ARGV[-1].to_i]}"
266
227
 
267
228
  # Testing the queue channel.
268
229
  system :test_queue do
269
- inner :clk, :rst, :clk2, :clk3
230
+ inner :rst, :clk1, :clk2, :clk3
270
231
  [8].inner :idata, :odata, :odata2
271
232
  [4].inner :counter
272
233
 
234
+
235
+ # Assign the clocks
236
+ mode = $mode.to_s.split("_")
237
+ if ($channel == :queue) then
238
+ clk_que = send(mode[0])
239
+ end
240
+ ev_pro = mode[1][0] == "n" ?
241
+ send(mode[1][1..-1]).negedge : send(mode[1]).posedge
242
+ ev_con = mode[2][0] == "n" ?
243
+ send(mode[2][1..-1]).negedge : send(mode[2]).posedge
244
+
245
+ # Set up the channel
273
246
  if $channel == :register then
274
247
  register(bit[8]).(:my_ch)
275
- register(bit[8]).(:my_ch2)
276
248
  elsif $channel == :handshake then
277
249
  handshake(bit[8],rst).(:my_ch)
278
- handshake(bit[8],rst).(:my_ch2)
279
250
  elsif $channel == :queue then
280
- queue(bit[8],5,clk,rst).(:my_ch)
281
- queue(bit[8],5,clk,rst).(:my_ch2)
251
+ queue(bit[8],3,clk_que,rst).(:my_ch)
282
252
  end
283
253
 
284
- ev = $mode == :sync ? clk.posedge :
285
- $mode == :nsync ? clk.negedge : clk2.posedge
286
-
287
- if $mode != :proco && $mode != :double then
288
- # Sync/Neg sync and async tests mode
289
- par(ev) do
290
- hif(rst) do
291
- counter <= 0
292
- idata <= 0
293
- # odata <= 0
294
- end
295
- helse do
296
- hif (counter < 4) do
297
- my_ch.write(idata) do
298
- idata <= idata + 1
299
- counter <= counter + 1
300
- end
301
- end
302
- helsif ((counter > 10) & (counter < 15)) do
303
- my_ch.read(odata) do
304
- # idata <= idata - odata
305
- counter <= counter + 1
306
- end
307
- end
308
- helse do
309
- counter <= counter + 1
310
- end
311
- end
254
+ # Producter/consumer mode
255
+ # Producer
256
+ par(ev_pro) do
257
+ hif(rst) do
258
+ idata <= 0
312
259
  end
313
- elsif $mode == :proco then
314
- # Producter/consumer mode
315
- # Producer
316
- par(clk2.posedge) do
317
- hif(rst) do
318
- idata <= 0
319
- end
320
- helse do
321
- my_ch.write(idata) do
322
- idata <= idata + 1
323
- end
260
+ helse do
261
+ my_ch.write(idata) do
262
+ idata <= idata + 1
324
263
  end
325
264
  end
326
- # Consumer
327
- par(clk3.posedge) do
328
- hif(rst) do
329
- counter <= 0
330
- end
331
- helse do
332
- my_ch.read(odata) do
333
- counter <= counter + 1
334
- end
335
- end
265
+ end
266
+ # Consumer
267
+ par(ev_con) do
268
+ hif(rst) do
269
+ counter <= 0
336
270
  end
337
- else
338
- # Producer and consumer are commicating through two layers of channels
339
- par(ev) do
340
- hif(rst) do
341
- counter <= 0
342
- idata <= 0
343
- end
344
- helse do
345
- my_ch.write(idata) do
346
- idata <= idata + 1
347
- end
348
- my_ch.read(odata) do
349
- my_ch2.write(odata)
350
- end
351
- my_ch2.read(odata2) do
352
- counter <= counter + 1
353
- end
271
+ helse do
272
+ my_ch.read(odata) do
273
+ counter <= counter + 1
354
274
  end
355
275
  end
356
276
  end
357
277
 
358
278
  timed do
359
- clk <= 0
279
+ clk1 <= 0
360
280
  clk2 <= 0
361
281
  clk3 <= 0
362
282
  rst <= 0
363
283
  !10.ns
364
- clk <= 1
284
+ clk1 <= 1
365
285
  !10.ns
366
- clk <= 0
286
+ clk1 <= 0
367
287
  rst <= 1
368
288
  !3.ns
369
289
  clk2 <= 1
370
290
  !3.ns
371
291
  clk3 <= 0
372
292
  !4.ns
373
- clk <= 1
293
+ clk1 <= 1
374
294
  !10.ns
375
- clk <= 0
295
+ clk1 <= 0
376
296
  !3.ns
377
297
  clk2 <= 0
378
298
  !3.ns
@@ -381,9 +301,9 @@ system :test_queue do
381
301
  rst <= 0
382
302
  !2.ns
383
303
  64.times do
384
- clk <= 1
304
+ clk1 <= 1
385
305
  !10.ns
386
- clk <= 0
306
+ clk1 <= 0
387
307
  !3.ns
388
308
  clk2 <= ~clk2
389
309
  !3.ns
@@ -0,0 +1,42 @@
1
+ module HDLRuby::High::Std
2
+
3
+ ##
4
+ # Standard HDLRuby::High library: connectors between channels
5
+ #
6
+ ########################################################################
7
+
8
+ # Function for generating a connector that duplicates the output of
9
+ # channel +inch+ and connect it to channels +outchs+ with data of
10
+ # +typ+.
11
+ # The duplication is done according to event +ev+.
12
+ function :duplicator do |typ, ev, inch, outchs|
13
+ ev = ev.poswedge unless ev.is_a?(Event)
14
+ inner :in_ack, :in_req
15
+ out_chacks = outchs.map.with_index do |ch,i|
16
+ [ ch, inner(:"out_ack#{i}") ]
17
+ end
18
+ typ.inner :data
19
+ par(ev) do
20
+ in_req <= 1
21
+ out_chacks.each { |ch,ack| ack <= 0 }
22
+ out_chacks.each do |ch,ack|
23
+ hif(ack == 1) { in_req <= 0 }
24
+ end
25
+ hif(in_req) do
26
+ in_ack <= 0
27
+ inch.read(data) { in_ack <= 1 }
28
+ end
29
+ hif(in_ack) do
30
+ out_chacks.each do |ch,ack|
31
+ hif(ack == 0) { ch.write(data) { ack <= 1 } }
32
+ end
33
+ hif (out_chacks.reduce(_1) { |sum,(ch,ack)| ack & sum }) do
34
+ out_chacks.each { |ch,ack| ack <= 0 }
35
+ end
36
+ end
37
+ end
38
+ end
39
+
40
+
41
+
42
+ end
@@ -1,3 +1,3 @@
1
1
  module HDLRuby
2
- VERSION = "2.4.12"
2
+ VERSION = "2.4.14"
3
3
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: HDLRuby
3
3
  version: !ruby/object:Gem::Version
4
- version: 2.4.12
4
+ version: 2.4.14
5
5
  platform: ruby
6
6
  authors:
7
7
  - Lovic Gauthier
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2020-10-30 00:00:00.000000000 Z
11
+ date: 2020-11-16 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler
@@ -120,6 +120,7 @@ files:
120
120
  - lib/HDLRuby/hdr_samples/tuple.rb
121
121
  - lib/HDLRuby/hdr_samples/with_channel.rb
122
122
  - lib/HDLRuby/hdr_samples/with_class.rb
123
+ - lib/HDLRuby/hdr_samples/with_connector.rb
123
124
  - lib/HDLRuby/hdr_samples/with_decoder.rb
124
125
  - lib/HDLRuby/hdr_samples/with_fixpoint.rb
125
126
  - lib/HDLRuby/hdr_samples/with_fsm.rb
@@ -272,6 +273,7 @@ files:
272
273
  - lib/HDLRuby/sim/hruby_value_pool.c
273
274
  - lib/HDLRuby/std/channel.rb
274
275
  - lib/HDLRuby/std/clocks.rb
276
+ - lib/HDLRuby/std/connector.rb
275
277
  - lib/HDLRuby/std/counters.rb
276
278
  - lib/HDLRuby/std/decoder.rb
277
279
  - lib/HDLRuby/std/fixpoint.rb