HDLRuby 2.4.1 → 2.4.6

checksums.yaml

@@ -1,7 +1,7 @@
 ---
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+  data.tar.gz: a5d2677dd07c54224dfb189d28c5c82015c4b099b7b204049402d1df940ac19e9051f9e199e56e6f2d043134697b307873b53e80dc86728bca2ebdc1087ce39f

data/lib/HDLRuby/hdr_samples/bstr_bench.rb

@@ -0,0 +1,14 @@
+
+# A benchmark for the bit string generation in case of signed values.
+system :bstr_bench do
+    signed[7..0].inner :val
+
+    timed do
+        val <= 0
+        !10.ns
+        val <= 26
+        !10.ns
+        val <= -25
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_multi_channels.rb

@@ -174,13 +174,22 @@ channel(:handshake) do |typ|
 end
 
 
-$mode = :prodcons
 # $mode = :sync
 # $mode = :nsync
 # $mode = :async
+# $mode = :proco  # Producter / Consummer
 # $channel = :register
 # $channel = :handshake
-$channel = :queue
+# $channel = :queue
+
+# The configuration scenarii
+$scenarii = [ [:sync,  :register], [:sync,  :handshake], [:sync,  :queue],
+              [:nsync, :register], [:nsync, :handshake], [:nsync, :queue],
+              [:async, :register], [:async, :handshake], [:async, :queue],
+              [:proco, :register], [:proco, :handshake], [:proco, :queue] ]
+
+# The configuration
+$mode, $channel = $scenarii[11]
 
 # Testing the queue channel.
 system :test_queue do
@@ -199,7 +208,7 @@ system :test_queue do
     ev = $mode == :sync ? clk.posedge : 
          $mode == :nsync ? clk.negedge : clk2.posedge
 
-    if $mode != :prodcons then
+    if $mode != :proco then
         # Sync/Neg sync and async tests mode
         par(ev) do
             hif(rst) do
@@ -263,27 +272,28 @@ system :test_queue do
         rst <= 1
         !3.ns
         clk2 <= 1
-        !1.ns
-        clk3 <= 1
-        !6.ns
+        !3.ns
+        clk3 <= 0
+        !4.ns
         clk <= 1
         !10.ns
         clk <= 0
-        rst <= 0
         !3.ns
         clk2 <= 0
-        !1.ns
+        !3.ns
         clk3 <= 1
-        !6.ns
+        !2.ns
+        rst <= 0
+        !2.ns
         64.times do
             clk <= 1
             !10.ns
             clk <= 0
             !3.ns
             clk2 <= ~clk2
-            !1.ns
+            !3.ns
             hif (clk2 == 0) { clk3 <= ~ clk3 }
-            !6.ns
+            !4.ns
         end
     end
 end

data/lib/HDLRuby/hruby_bstr.rb

@@ -35,10 +35,13 @@ module HDLRuby
             # Maybe str is an numeric.
             if str.is_a?(Numeric) then
                 # Yes, convert it to a binary string.
-                str = str.to_s(2)
+                num = str
+                str = num.to_s(2)
                 # And fix the sign.
                 if str[0] == "-" then
-                    str = str[1..-1]
+                    # str = str[1..-1]
+                    str = (2**str.size+num).to_s(2)
+                    puts "str=#{str}"
                     sign = "-"
                 else
                     sign = "+"

data/lib/HDLRuby/hruby_low2c.rb

@@ -111,6 +111,8 @@ module HDLRuby::Low
             res << "int main(int argc, char* argv[]) {\n"
             # Build the objects.
             objs.each { |obj| res << "   #{Low2C.make_name(obj)}();\n" }
+            # Sets the top systemT.
+            res << "   top_system = #{Low2C.obj_name(top)};\n"
             # Starts the simulation.
             res<< "   hruby_sim_core(\"#{name}\",#{init_visualizer},-1);\n"
             # Close the main.
@@ -1329,6 +1331,10 @@ module HDLRuby::Low
                 res << "block->owner = NULL;\n"
             end
 
+            # The name
+            res << " " * (level+1)*3
+            res << "block->name = \"#{self.name}\";\n"
+
             # Add the inner signals declaration.
             res << " " * (level+1)*3
             res << "block->num_inners = #{self.each_inner.to_a.size};\n"
@@ -1439,8 +1445,14 @@ module HDLRuby::Low
                 str = self.content.is_a?(BitString) ?
                     self.content.to_s : self.content.to_s(2).rjust(32,"0")
             else
-                sign = self.content>=0 ? "0" : "1"
-                str = self.content.abs.to_s(2).rjust(width,sign).upcase
+                # sign = self.content>=0 ? "0" : "1"
+                # str = self.content.abs.to_s(2).rjust(width,sign).upcase
+                if self.content >= 0 then
+                    str = self.content.to_s(2).rjust(width,"0").upcase
+                else
+                    str = (2**width+self.content).to_s(2).upcase
+                end
+                # puts "content=#{self.content} str=#{str}"
             end
             # Is it a fully defined number?
             if str =~ /^[01]+$/ then

data/lib/HDLRuby/sim/hruby_sim.h

@@ -474,6 +474,7 @@ typedef struct BlockS_ {
     Kind kind;          /* The kind of object. */
     Object owner;       /* The owner if any. */
 
+    char* name;         /* The name of the block. */
     int num_inners;     /* The number of inners. */
     SignalI* inners;    /* The inners of the scope. */
     void (*function)(); /* The function to execute for the block. */
@@ -496,6 +497,9 @@ typedef struct EventS_ {
 /* The time units. */
 typedef enum { S, MS, US, NS, PS, FS } Unit;
 
+/** The top system. */
+extern SystemT top_system;
+
 /** Adds a timed behavior for processing. 
  *  @param behavior the timed behavior to register */
 extern void register_timed_behavior(Behavior behavior);
@@ -574,17 +578,17 @@ typedef struct {
     void (*print_signal)(SignalI);
 } PrinterS;
 
-PrinterS printer;
+extern PrinterS printer;
 
 /** Initializes the visualization printer engine.
  *  @param print_time the time printer
  *  @param print_name the name printer
  *  @param print_value the value printer
  *  @param print_signal the signal state printer. */
-void init_visualizer(void (*print_time)(unsigned long long), 
-                     void (*print_name)(Object),
-                     void (*print_value)(Value),
-                     void (*print_signal)(SignalI));
+extern void init_visualizer(void (*print_time)(unsigned long long), 
+                            void (*print_name)(Object),
+                            void (*print_value)(Value),
+                            void (*print_signal)(SignalI));
 
 // /** Prints the time.
 //  *  @param time the time to show. */

data/lib/HDLRuby/sim/hruby_sim_core.c

@@ -12,6 +12,9 @@
  *  hruby_low2c. 
  *  */
 
+/** The top system. */
+SystemT top_system;
+
 /** The number of all the signals. */
 static int num_all_signals = 0;
 /** The capacity of the set of signals. */

data/lib/HDLRuby/sim/hruby_sim_vcd.c

@@ -64,35 +64,49 @@ static void vcd_print_time(unsigned long long time) {
 }
 
 
-/** Prints the name of an object.
+/** Prints the name of an object without its hierarchy.
  *  @param object the object to print the name. */
 static void vcd_print_name(Object object) {
-    /* Recurse on the owner if any. */
-    // printf("owner=%p\n",object->owner);
-    if (object->owner != NULL) {
-        vcd_print_name(object->owner);
-        vcd_print("$");
-    }
     /* Depending on the kind of object. */
     switch(object->kind) {
         case SYSTEMT:
         case SIGNALI:
         case SCOPE:
         case SYSTEMI:
+        case BLOCK:
             /* Print the name if name. */
             /* Trick: SystemT, SignalI, Scope and SystemI have the
              * field name at the same place. */
-            if (((SystemI)object)->name != NULL) {
+            if ((((Block)object)->name != NULL) &&
+                    strlen(((Block)object)->name)>0) {
                 char name[256];
-                strncpy(name,((SystemI)object)->name,256);
+                strncpy(name,((Block)object)->name,256);
                 replace_char(name,':','$');
                 vcd_print("%s",name);
+            } else {
+                /* No name, use the address of the object as name generator.*/
+                vcd_print("$%p",(void*)object);
             }
+            break;
         default: /* Nothing to do */
             break;
     }
 }
 
+
+/** Prints the name of an object incluing its heirarchy.
+ *  @param object the object to print the name. */
+static void vcd_print_full_name(Object object) {
+    /* Recurse on the owner if any. */
+    // printf("owner=%p\n",object->owner);
+    if (object->owner != NULL) {
+        vcd_print_full_name(object->owner);
+        vcd_print("$");
+    }
+    /* Print the name of the object. */
+    vcd_print_name(object);
+}
+
 /** Prints a value.
  *  @param value the value to print */
 static void vcd_print_value(Value value) {
@@ -127,23 +141,169 @@ static void vcd_print_value(Value value) {
  *  @param signal the signal to declare */
 static void vcd_print_var(SignalI signal) {
     vcd_print("$var wire %d ",type_width(signal->type));
-    vcd_print_name((Object)signal);
+    vcd_print_full_name((Object)signal);
     vcd_print(" ");
     vcd_print_name((Object)signal);
     vcd_print(" $end\n");
 }
 
 
-/** Prints a signal.
+/** Prints a signal with its future value if any.
  *  @param signal the signal to show */
-static void vcd_print_signal(SignalI signal) {
-    vcd_print_value(signal->f_value);
-    vcd_print(" ");
-    vcd_print_name((Object)signal);
-    vcd_print("\n");
+static void vcd_print_signal_fvalue(SignalI signal) {
+    if (signal->f_value) {
+        vcd_print_value(signal->f_value);
+        vcd_print(" ");
+        vcd_print_full_name((Object)signal);
+        vcd_print("\n");
+    }
+}
+
+
+/** Prints a signal with its current value if any
+ *  @param signal the signal to show */
+static void vcd_print_signal_cvalue(SignalI signal) {
+    if (signal->c_value) {
+        vcd_print_value(signal->c_value);
+        vcd_print(" ");
+        vcd_print_full_name((Object)signal);
+        vcd_print("\n");
+    }
+}
+
+
+/** Prints the hierarchy content of a system type.
+ *  @param system the system to print. */
+static void vcd_print_systemT_content(SystemT system);
+
+/** Prints the hierarchy of a scope.
+ *  @param scope the scope to print. */
+static void vcd_print_scope(Scope scope);
+
+
+/** Prints the hierarchy of a block.
+ *  @param block the block to print. */
+static void vcd_print_block(Block block) {
+    int i;
+    /* Do not print block with no declaration. */
+    if (block->num_inners == 0) return;
+
+    /* Declares the block if named. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)block);
+    vcd_print(" $end\n");
+
+    /* Declare the inners of the systems. */
+    for(i=0; i<block->num_inners; ++i) {
+        vcd_print_var(block->inners[i]);
+    }
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
 }
 
 
+/** Prints the hierarchy of a system instances.
+ *  @param scope the scope to print. */
+static void vcd_print_systemI(SystemI systemI) {
+    /* Declares the systemI. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)systemI);
+    vcd_print(" $end\n");
+
+    /* Declares its content. */
+    vcd_print_systemT_content(systemI->system);
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
+}
+
+
+/** Prints the hierarchy inside a scope.
+ *  @param scope the scope to print the inside. */
+static void vcd_print_scope_content(Scope scope) {
+    int i;
+
+    /* Declare the inners of the systems. */
+    for(i=0; i<scope->num_inners; ++i) {
+        vcd_print_var(scope->inners[i]);
+    }
+
+    /* Recurse on the system instances. */
+    for(i=0; i<scope->num_systemIs; ++i) {
+        vcd_print_systemI(scope->systemIs[i]);
+    }
+
+    /* Recurse on the sub scopes. */
+    for(i=0; i<scope->num_scopes; ++i) {
+        vcd_print_scope(scope->scopes[i]);
+    }
+
+    /* Recurse on the behaviors. */
+    for(i=0; i<scope->num_behaviors; ++i) {
+        vcd_print_block(scope->behaviors[i]->block);
+    }
+}
+
+
+/** Prints the hierarchy of a scope.
+ *  @param scope the scope to print. */
+static void vcd_print_scope(Scope scope) {
+    /* Do not print block with no declaration. */
+    if (scope->num_inners == 0 && scope->num_scopes == 0 && scope->num_behaviors == 0) return;
+    /* Declares the scope. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)scope);
+    vcd_print(" $end\n");
+
+    /* Declares its content. */
+    vcd_print_scope_content(scope);
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
+}
+
+
+/** Prints the hierarchy content of a system type.
+ *  @param system the system to print. */
+static void vcd_print_systemT_content(SystemT system) {
+    int i;
+
+    /* Declare the inputs of the systems. */
+    for(i = 0; i<system->num_inputs; ++i) {
+        vcd_print_var(system->inputs[i]);
+    }
+    /* Declare the outputs of the systems. */
+    for(i = 0; i<system->num_outputs; ++i) {
+        vcd_print_var(system->outputs[i]);
+    }
+    /* Declare the inouts of the systems. */
+    for(i = 0; i<system->num_inouts; ++i) {
+        vcd_print_var(system->inouts[i]);
+    }
+    /* Recurse on the content of the scope (the scope header is the system).*/
+    vcd_print_scope_content(system->scope);
+}
+
+
+/** Prints the hierarchy of a system type.
+ *  @param system the system to print. */
+static void vcd_print_systemT(SystemT system) {
+    int i;
+    /* Declares the module. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)system);
+    vcd_print(" $end\n");
+
+    /* Declares the content. */
+    vcd_print_systemT_content(system);
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
+}
+
+
+
 
 
 /* high-end print functions. */
@@ -164,7 +324,7 @@ static void vcd_print_header() {
     /* The version section. */
     vcd_print("$version\n");
     vcd_print("   Generated from HDLRuby simulator\n");
-    vcd_print("$end");
+    vcd_print("$end\n");
     
     /* The comment section. */
     vcd_print("$comment\n");
@@ -174,20 +334,25 @@ static void vcd_print_header() {
     /* The time scale section: for now 1ps only. */
     vcd_print("$timescale 1ps $end\n");
 
-    /* The scope section: nothing specific. */
-    vcd_print("$scope module logic $end\n");
+    // /* The scope section: nothing specific. */
+    // vcd_print("$scope module logic $end\n");
 
-    /* The variables declaration. */
-    each_all_signal(&vcd_print_var);
+    // /* The variables declaration. */
+    // each_all_signal(&vcd_print_var);
 
+    // /* Ends the declarations. */
+    // vcd_print("$upscope $end\n");
+    // vcd_print("$enddefinitions $end\n");
+
+    /* The declaration of the hierarchy and the variables
+     * from the top system. */
+    vcd_print_systemT(top_system);
     /* Ends the declarations. */
-    vcd_print("$upscope $end\n");
     vcd_print("$enddefinitions $end\n");
 
     /* Display the initializations. */
     vcd_print("$dumpvars\n");
-    // Maybe nothing to do.
-    // each_all_init_signal(&vcd_print_signal);
+    each_all_signal(&vcd_print_signal_cvalue);
     vcd_print("$end\n");
 }
 
@@ -206,9 +371,9 @@ extern void init_vcd_visualizer(char* name) {
 
     /* Initialize the vizualizer printer engine. */
     init_visualizer(&vcd_print_time,
-                    &vcd_print_name,
+                    &vcd_print_full_name,
                     &vcd_print_value,
-                    &vcd_print_signal);
+                    &vcd_print_signal_fvalue);
 
     /* Prints the header of the vcd file. */
     vcd_print_header();

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.1"
+  VERSION = "2.4.6"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.1
+  version: 2.4.6
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-09-24 00:00:00.000000000 Z
+date: 2020-10-07 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -75,6 +75,7 @@ files:
 - lib/HDLRuby/hdr_samples/addsub.rb
 - lib/HDLRuby/hdr_samples/addsubz.rb
 - lib/HDLRuby/hdr_samples/alu.rb
+- lib/HDLRuby/hdr_samples/bstr_bench.rb
 - lib/HDLRuby/hdr_samples/calculator.rb
 - lib/HDLRuby/hdr_samples/counter_bench.rb
 - lib/HDLRuby/hdr_samples/dff.rb