HDLRuby 2.3.8 → 2.4.10

data/lib/HDLRuby/sim/hruby_sim_vizualize.c

@@ -7,26 +7,51 @@
  *  generated by hruby_low2c. 
  **/
 
+/* The print function pointers. */
+
+PrinterS printer;
+
+
+/** Initializes the visualization printer engine.
+ *  @param print_time the time printer
+ *  @param print_name the name printer
+ *  @param print_value the value printer
+ *  @param print_signal the signal state printer. */
+void init_visualizer(void (*print_time)(unsigned long long), 
+                     void (*print_name)(Object),
+                     void (*print_value)(Value),
+                     void (*print_signal)(SignalI)) {
+    printer.print_time = print_time; 
+    printer.print_name = print_name; 
+    printer.print_value = print_value; 
+    printer.print_signal = print_signal; 
+}
+
+                    
+
+
+/* The default printing functions. */
+
 /** Prints the time.
  *  @param time the time to show. */
-void print_time(unsigned long long time) {
+static void default_print_time(unsigned long long time) {
     printf("# %llups",time);
 }
 
 /** Prints the time and goes to the next line.
- *  @param time the time to show. */
-void println_time(unsigned long long time) {
-    print_time(time);
+ *  @par1am time the time to show. */
+static void default_println_time(unsigned long long time) {
+    default_print_time(time);
     printf("\n");
 }
 
 /** Prints the name of an object.
  *  @param object the object to print the name. */
-void print_name(Object object) {
+static void default_print_name(Object object) {
     /* Recurse on the owner if any. */
     // printf("owner=%p\n",object->owner);
     if (object->owner != NULL) {
-        print_name(object->owner);
+        default_print_name(object->owner);
         printf("::");
     }
     /* Depending on the kind of object. */
@@ -48,7 +73,7 @@ void print_name(Object object) {
 
 /** Prints a value.
  *  @param value the value to print */
-void print_value(Value value) {
+static void default_print_value(Value value) {
     if (value->numeric) {
         unsigned long long width = type_width(value->type);
         unsigned long long mask = 1ULL << (width-1);
@@ -77,15 +102,29 @@ void print_value(Value value) {
 
 /** Prints a signal.
  *  @param signal the signal to show */
-void print_signal(SignalI signal) {
-    print_name((Object)signal);
+static void default_print_signal(SignalI signal) {
+    default_print_name((Object)signal);
     printf(": ");
-    print_value(signal->f_value);
+    default_print_value(signal->f_value);
 }
 
 /** Prints a signal and goes to the next line.
  *  @param signal the signal to show */
-void println_signal(SignalI signal) {
-    print_signal(signal);
+static void default_println_signal(SignalI signal) {
+    default_print_signal(signal);
     printf("\n");
 }
+
+
+
+/* Set up the visualizer. */
+
+/** Set up the default vizualization engine.
+ *  @param name the name of the vizualization. */
+void init_default_visualizer(char* name) {
+    /* Initialize the vizualizer printer engine. */
+    init_visualizer(&default_println_time,
+                    &default_print_name,
+                    &default_print_value,
+                    &default_println_signal);
+}

data/lib/HDLRuby/std/fixpoint.rb

@@ -52,10 +52,18 @@ module HDLRuby::High::Std
                         end
                         # Redefine the multiplication and division for fixed point.
                         typ.define_operator(:*) do |left,right|
-                            (left.as([isize+fsize*2])*right) >> fsize
+                            if (typ.signed?) then
+                                (left.as(signed[isize+fsize*2])*right) >> fsize
+                            else
+                                (left.as([isize+fsize*2])*right) >> fsize
+                            end
                         end
                         typ.define_operator(:/) do |left,right|
-                            (left.as([isize+fsize*2]) << fsize) / right
+                            if (typ.signed?) then
+                                (left.as(signed[isize+fsize*2]) << fsize) / right
+                            else
+                                (left.as([isize+fsize*2]) << fsize) / right
+                            end
                         end
                         typ
                     end

data/lib/HDLRuby/std/linear.rb

@@ -209,6 +209,7 @@ module HDLRuby::High::Std
         # lv and rv are valid.
         lvoks = lefts.each_with_index.map { |left,i| inner :"lvok#{i}" }
         inner :rvok
+        woks = lefts.each_with_index.map { |left,i| inner :"wok#{i}" }
         # Run flag
         inner :run
         par(ev) do
@@ -218,28 +219,39 @@ module HDLRuby::High::Std
                 rvok <= 0
                 lefts.each_with_index do |left,i|
                     lvoks[i] <= 0
-                    # accs[i].write(0)
-                    avs[i] <= 0
+                    # avs[i] <= 0
+                    woks[i] <= 0
                 end
             end
             hif(req | run) do
                 run <= 1
                 # Computation request.
-                right.read(rv) { rvok <= 1 }
+                hif(~rvok) { right.read(rv) { rvok <= 1 } }
                 lefts.each_with_index do |left,i|
-                    left.read(lvs[i])  { lvoks[i] <= 1 }
+                    hif(~lvoks[i]) { left.read(lvs[i])  { lvoks[i] <= 1 } }
                     # accs[i].read(avs[i])
-                    hif(lvoks[i] & rvok) do
+                    hif(lvoks[i] & rvok & ~woks[i]) do
                         ack <= 1
                         run <= 0
-                        # accs[i].write(add.(avs[i],mul.(lvs[i],rv)))
                         seq do
                             avs[i] <= add.(avs[i],mul.(lvs[i],rv))
-                            accs[i].write(avs[i])
+                            accs[i].write(avs[i]) do
+                                woks[i] <= 1
+                                # seq do
+                                #     lvoks[i] <= 0
+                                #     rvok <= lvoks.reduce(:|)
+                                # end
+                            end
                         end
                     end
+                    hif (woks.reduce(:&)) do
+                        woks.each { |wok| wok <= 0 }
+                        lvoks.each { | lvok| lvok <=0 }
+                        rvok <= 0
+                    end
                 end
             end
+            helse { avs.each {|av| av <= 0 } }
             # helse do
             #     rvok <= 0
             #     lefts.each_with_index do |left,i|

data/lib/HDLRuby/std/memory.rb

@@ -34,6 +34,7 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Ensure clk_e is an event, if not set it to a positive edge.
     clk_e = clk_e.posedge unless clk_e.is_a?(Event)
 
@@ -209,6 +210,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Process the table of reset mapping for the branches.
     # Ensures br_srts is a hash.
     br_rsts = br_rsts.to_hash
@@ -292,17 +294,43 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                 trig_r <= 0
             end
             # The read procedure.
+        #     par do
+        #         hif(rst == 0) do
+        #             # No reset, so can perform the read.
+        #             hif(trig_r == 1) do
+        #                 # The trigger was previously set, read ok.
+        #                 target <= dbus_r
+        #                 blk.call if blk
+        #             end
+        #             # Prepare the read.
+        #             abus_r <= abus_r + 1
+        #             trig_r <= 1
+        #         end
+        #     end
+            # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r + 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r + 1
+                        if 2**size.width != size then
+                            abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                        else
+                            abus_r <= abus_r + 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r + 1
-                    trig_r <= 1
                 end
             end
         end
@@ -331,18 +359,44 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                 # Reset so switch of the access trigger.
                 trig_r <= 0
             end
+            # # The read procedure.
+            # par do
+            #     hif(rst == 0) do
+            #         # No reset, so can perform the read.
+            #         hif(trig_r == 1) do
+            #             # The trigger was previously set, read ok.
+            #             target <= dbus_r
+            #             blk.call if blk
+            #         end
+            #         # Prepare the read.
+            #         abus_r <= abus_r - 1
+            #         trig_r <= 1
+            #     end
+            # end
             # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r - 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r - 1
+                        if 2**size.width != size then
+                            abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                        else
+                            abus_r <= abus_r - 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r - 1
-                    trig_r <= 1
                 end
             end
         end
@@ -392,6 +446,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Process the table of reset mapping for the branches.
     # puts "first br_rsts=#{br_rsts}"
     # if br_rsts.is_a?(Array) then
@@ -541,12 +596,24 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r + 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r + 1
+                        if 2**size.width != size then
+                            abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                        else
+                            abus_r <= abus_r + 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r + 1
-                    trig_r <= 1
                 end
             end
         end
@@ -581,7 +648,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -613,18 +685,44 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                 # Reset so switch of the access trigger.
                 trig_r <= 0
             end
+            # # The read procedure.
+            # par do
+            #     hif(rst == 0) do
+            #         # No reset, so can perform the read.
+            #         hif(trig_r == 1) do
+            #             # The trigger was previously set, read ok.
+            #             target <= dbus_r
+            #             blk.call if blk
+            #         end
+            #         # Prepare the read.
+            #         abus_r <= abus_r - 1
+            #         trig_r <= 1
+            #     end
+            # end
             # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r - 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r - 1
+                        if 2**size.width != size then
+                            abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                        else
+                            abus_r <= abus_r - 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r - 1
-                    trig_r <= 1
                 end
             end
         end
@@ -659,7 +757,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w - 1
+                    # abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -853,6 +956,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
+        awidth = size.width-1
+        awidth = 1 if awidth == 0
         [size.width-1].inner :abus_r
         reader_inout :abus_r
 
@@ -876,7 +981,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next read.
-                    abus_r <= abus_r + 1
+                    # abus_r <= abus_r + 1
+                    if 2**size.width != size then
+                        abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                    else
+                        abus_r <= abus_r + 1
+                    end
                 end
             end
         end
@@ -915,7 +1025,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                 end
             end
         end
@@ -933,6 +1048,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
+        awidth = size.width - 1
+        awidth = 1 if awidth == 0
         [size.width-1].inner :abus_r
         reader_inout :abus_r
 
@@ -956,7 +1073,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next read.
-                    abus_r <= abus_r - 1
+                    # abus_r <= abus_r - 1
+                    if 2**size.width != size then
+                        abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                    else
+                        abus_r <= abus_r - 1
+                    end
                 end
             end
         end
@@ -995,7 +1117,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next write.
-                    abus_w <= abus_w - 1
+                    # abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                 end
             end
         end
@@ -1043,7 +1170,9 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size*nbanks-1).width
+    awidth = 1 if awidth == 0
     awidth_b = (size-1).width # Bank width
+    awidth_b = 1 if awidth_b == 0
     # Ensures br_srts is a hash.
     br_rsts = br_rsts.to_hash
 
@@ -1204,7 +1333,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                         blk.call if blk
                     end
                     # Prepare the read.
-                    abus_r <= abus_r + 1
+                    # abus_r <= abus_r + 1
+                    if 2**size.width != size then
+                        abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                    else
+                        abus_r <= abus_r + 1
+                    end
                     trig_r <= 1
                 end
             end
@@ -1240,7 +1374,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -1281,7 +1420,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                         blk.call if blk
                     end
                     # Prepare the read.
-                    abus_r <= abus_r - 1
+                    # abus_r <= abus_r - 1
+                    if 2**size.width != size then
+                        abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                    else
+                        abus_r <= abus_r - 1
+                    end
                     trig_r <= 1
                 end
             end
@@ -1318,6 +1462,11 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the write.
                     abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end