HDLRuby 2.3.8 → 2.4.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 164191b6cbfda40e60bc6b253c95a0ff511164007c83adf53c7f86383b404464
-  data.tar.gz: 5344dd9f624089cab1488d9e10b67e542cb83639db81e397c0d2241c67a43527
+  metadata.gz: 65ef28718e6de9e9d1358073d2d7ae8bd914a3f942b48d6cd45c8f28f545a906
+  data.tar.gz: 0d469d886d79f65ebfc69a4c4f95d2d8f50c0ada6f4fdbf0349d3c9650fa4581
 SHA512:
-  metadata.gz: 5e9b00b3fad458789078bcaca6d8d45e7ac5877ff14a3971ce2ddac186ed15a1ad2aa440d3c5619c66f324e9f6dbeda5c8bcf2aa5de3389aa12d631abbd780a4
-  data.tar.gz: '08dc450e1e3807d85f8ffb22888c037b081bed44dab318fac5fb33611f706c58191a2b06379b0798b61bbf3578d0e058b144ee8995e4212250826366bd306e9e'
+  metadata.gz: 4d458fe640fd29e1e31470b1f395333c3fd344703903c0c7d126e780d9e6f93c419f18a4e4cbaadc91461d19ed0087388a249fe3ccd87b2ed29d731733ecbc5b
+  data.tar.gz: 1ff098b2ca9bff7758bff7a5bb5e20df7272f53f103944037f9575b55444e6179781129e5d87e301a4e29b885bee5cc82794918ad85ac8236894603759d66212

data/README.md

@@ -50,6 +50,7 @@ Where:
 | `-s, --syntax`    | Output the Ruby syntax tree                          |
 | `-C, --clang`     | Output the C code of the simulator                   |
 | `-S, --sim`       | Output the executable simulator and execute it       |
+| `--vcd`           | Make the simulator generate a vcd file               |
 | `-d, --directory` | Specify the base directory for loading the HDLRuby files |
 | `-D, --debug`     | Set the HDLRuby debug mode |
 | `-t, --top system`| Specify the top system describing the circuit to compile |

data/lib/HDLRuby/hdr_samples/with_multi_channels.rb

@@ -0,0 +1,290 @@
+require "std/channel.rb"
+
+include HDLRuby::High::Std
+
+# Channel describing a buffered queue storing data of +typ+ type of +depth+,
+# synchronized through clk and reset on +rst+.
+channel(:queue) do |typ,depth,clk,rst|
+    # The inner buffer of the queue.
+    typ[-depth].inner :buffer
+    # The read and write pointers.
+    [depth.width].inner :rptr, :wptr
+    # The read and write command signals.
+    inner :rcmd, :wcmd
+    # The read and write ack signals.
+    inner :rack, :wack
+    # The ack check deactivator (for synchron accesses).
+    inner :hrack, :hwack
+    # The read/write data registers.
+    typ.inner :rdata, :wdata
+
+    # The process handling the decoupled access to the buffer.
+    par(clk.posedge) do
+        # rack <= 0
+        # wack <= 0
+        hif (~rcmd) { rack <= 0 }
+        hif (~wcmd) { wack <= 0 }
+        hif(rst) { rptr <= 0; wptr <= 0 }
+        hif(rcmd & (hrack|~rack) & (rptr != wptr)) do
+            rptr <= (rptr + 1) % depth
+            rack <= 1
+        end
+        hif(wcmd & (hwack|~wack) & (((wptr+1) % depth) != rptr)) do
+            buffer[wptr] <= wdata
+            # buffer[1] <= wdata
+            wptr <= (wptr + 1) % depth
+            wack <= 1
+        end
+    end
+    par { rdata <= buffer[rptr] }
+
+    reader_output :rcmd, :rptr, :hrack
+    reader_input :rdata, :rack
+
+    # The read primitive.
+    reader do |blk,target|
+        if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
+            # Same clk event, synchrone case: perform a direct access.
+            # Now perform the access.
+            top_block.unshift do
+                rcmd <= 0
+                hrack <= 1
+            end
+            seq do
+                rptr <= (rptr + 1) % depth
+                target <= rdata
+                blk.call if blk
+            end
+        else
+            # Different clk event, perform a decoupled access.
+            top_block.unshift do
+                rcmd <= 0
+                hrack <= 0
+            end
+            seq do
+                hif(rack) do
+                    blk.call if blk
+                end
+                helse do
+                    rcmd <= 1 
+                    target <= rdata
+                end
+            end
+        end
+    end
+
+    writer_output :wcmd, :wdata, :hwack
+    writer_input :wack
+
+    # The write primitive.
+    writer do |blk,target|
+        if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
+            # Same clk event, synchrone case: perform a direct access.
+            top_block.unshift do
+                wcmd <= 0
+                hwack <= 1
+            end
+            wcmd <= 1
+            wdata <= target
+            blk.call if blk
+        else
+            # Different clk event, asynchrone case: perform a decoupled access.
+            top_block.unshift do
+                wcmd <= 0
+                hwack <= 0
+            end
+            seq do
+                hif(wack) do
+                    blk.call if blk
+                end
+                helse { wcmd <= 1 }
+                wdata <= target
+            end
+        end
+    end
+end
+
+
+# Channel describing a register of +typ+ type.
+channel(:register) do |typ|
+    # The register.
+    typ.inner :buffer
+
+    reader_input :buffer
+
+    # The read primitive.
+    reader do |blk,target|
+        target <= buffer
+        blk.call if blk
+    end
+
+    writer_output :buffer
+
+    # The read primitive.
+    writer do |blk,target|
+        buffer <= target
+        blk.call if blk
+    end
+end
+
+
+
+# Channel describing a handshake for transmitting data of +typ+ type, reset
+# by +rst+
+channel(:handshake) do |typ|
+    # The data signal.
+    typ.inner :data
+    # The request and acknowledge.
+    typ.inner :req, :ack
+
+    reader_input :ack, :data
+    reader_output :req
+
+    # The read primitive.
+    reader do |blk,target|
+        top_block.unshift do
+            req <= 0
+        end
+        hif(ack == 0) do
+            req <= 1
+        end
+        helsif(req) do
+            target <= data
+            req <= 0
+            blk.call if blk
+        end
+    end
+
+    writer_input :req
+    writer_output :ack, :data
+
+    # The read primitive.
+    writer do |blk,target|
+        top_block.unshift do
+            ack <= 0
+        end
+        hif(req) do
+            hif(~ack) do
+                data <= target
+                blk.call if blk
+            end
+            ack <= 1
+        end
+    end
+end
+
+
+$mode = :prodcons
+# $mode = :sync
+# $mode = :nsync
+# $mode = :async
+# $channel = :register
+# $channel = :handshake
+$channel = :queue
+
+# Testing the queue channel.
+system :test_queue do
+    inner :clk, :rst, :clk2, :clk3
+    [8].inner :idata, :odata
+    [4].inner :counter
+
+    if $channel == :register then
+        register(bit[8]).(:my_ch)
+    elsif $channel == :handshake then
+        handshake(bit[8],rst).(:my_ch)
+    elsif $channel == :queue then
+        queue(bit[8],5,clk,rst).(:my_ch)
+    end
+
+    ev = $mode == :sync ? clk.posedge : 
+         $mode == :nsync ? clk.negedge : clk2.posedge
+
+    if $mode != :prodcons then
+        # Sync/Neg sync and async tests mode
+        par(ev) do
+            hif(rst) do
+                counter <= 0
+                idata <= 0
+                odata <= 0
+            end
+            helse do
+                hif (counter < 4) do
+                    my_ch.write(idata) do
+                        idata <= idata + 1
+                        counter <= counter + 1
+                    end
+                end
+                helsif ((counter > 10) & (counter < 15)) do
+                    my_ch.read(odata) do
+                        idata <= idata - odata
+                        counter <= counter + 1
+                    end
+                end
+                helse do
+                    counter <= counter + 1
+                end
+            end
+        end
+    else
+        # Producter/consumer mode
+        # Producer
+        par(clk2.posedge) do
+            hif(rst) do
+                idata <= 0
+            end
+            helse do
+                my_ch.write(idata) do
+                    idata <= idata + 1
+                end
+            end
+        end
+        # Consumer
+        par(clk3.posedge) do
+            hif(rst) do
+                counter <= 0
+            end
+            helse do
+                my_ch.read(odata) do
+                    counter <= counter + 1
+                end
+            end
+        end
+    end
+
+    timed do
+        clk <= 0
+        clk2 <= 0
+        clk3 <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !3.ns
+        clk2 <= 1
+        !1.ns
+        clk3 <= 1
+        !6.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !3.ns
+        clk2 <= 0
+        !1.ns
+        clk3 <= 1
+        !6.ns
+        64.times do
+            clk <= 1
+            !10.ns
+            clk <= 0
+            !3.ns
+            clk2 <= ~clk2
+            !1.ns
+            hif (clk2 == 0) { clk3 <= ~ clk3 }
+            !6.ns
+        end
+    end
+end
+

data/lib/HDLRuby/hdrcc.rb

@@ -269,6 +269,9 @@ $optparse = OptionParser.new do |opts|
         $options[:multiple] = v
         $options[:sim] = v
     end
+    opts.on("--vcd", "The simulator will generate a vcd file") do |v|
+        $options[:vcd] = v
+    end
     opts.on("-v", "--verilog","Output in Verlog HDL format") do |v|
         $options[:verilog] = v
         $options[:multiple] = v
@@ -515,9 +518,15 @@ elsif $options[:clang] then
         # Generate the code for it.
         $main = File.open($name,"w")
 
+        # Select the vizualizer depending on the options.
+        init_visualizer = $options[:vcd] ? "init_vcd_visualizer" :
+                                           "init_default_visualizer"
+
         # Generate the code of the main function.
         # HDLRuby start code
-        $main << HDLRuby::Low::Low2C.main($top_system,
+        $main << HDLRuby::Low::Low2C.main("hruby_simulator",
+                                         init_visualizer,
+                                         $top_system,
                                          $top_system.each_systemT_deep.to_a.reverse,$hnames)
         $main.close
 

data/lib/HDLRuby/hruby_high.rb

@@ -2791,6 +2791,14 @@ module HDLRuby::High
             return RefObject.new(@base,@object)
         end
 
+        # Comparison for hash: structural comparison.
+        def eql?(obj)
+            return false unless obj.is_a?(RefObject)
+            return false unless @base.eql?(obj.base)
+            return false unless @object.eql?(obj.object)
+            return true
+        end
+
         # Converts the name reference to a HDLRuby::Low::RefName.
         def to_low
             # return HDLRuby::Low::RefName.new(@base.to_ref.to_low,@object.name)

data/lib/HDLRuby/hruby_low.rb

@@ -1978,14 +1978,6 @@ module HDLRuby::Low
 
         include Hparent
 
-        # # Creates a new behavior.
-        # def initialize
-        #     # Initialize the sensitivity list.
-        #     @events = []
-        #     # Initialize the block list.
-        #     @blocks = []
-        # end
-
         # The block executed by the behavior.
         attr_reader :block
 
@@ -2074,6 +2066,11 @@ module HDLRuby::Low
             return !@events.empty?
         end
 
+        # Tells if it is activated on one of +events+.
+        def on_event?(*events)
+            @events.any? { |ev0| events.any? { |ev1| ev0.eql?(ev1) } }
+        end
+
         # Tells if there is a positive or negative edge event.
         def on_edge?
             @events.each do |event|
@@ -2619,6 +2616,15 @@ module HDLRuby::Low
             end
         end
 
+        # Gets the behavior the statement is in.
+        def behavior
+            if self.parent.is_a?(Behavior) then
+                return self.parent
+            else
+                return self.parent.behavior
+            end
+        end
+
         # Gets the top block, i.e. the first block of the current behavior.
         def top_block
             return self.parent.is_a?(Behavior) ? self : self.parent.top_block
@@ -4368,7 +4374,7 @@ module HDLRuby::Low
             # Recurse on the select.
             return true if @select.use_name?(*names)
             # Recurse on the choices.
-            return @choices.include? { |choice| choice.use_name?(*names) }
+            return @choices.any? { |choice| choice.use_name?(*names) }
         end
 
         # Clones the select (deeply)
@@ -4453,7 +4459,7 @@ module HDLRuby::Low
         # Tell if the expression includes a signal whose name is one of +names+.
         def use_name?(*names)
             # Recurse on the expressions.
-            return @expressions.include? { |expr| expr.use_name?(*names) }
+            return @expressions.any? { |expr| expr.use_name?(*names) }
         end
 
         # Clones the concatenated expression (deeply)
@@ -4601,7 +4607,7 @@ module HDLRuby::Low
         # Tell if the expression includes a signal whose name is one of +names+.
         def use_name?(*names)
             # Recurse on the references.
-            return @refs.include? { |expr| expr.use_name?(*names) }
+            return @refs.any? { |expr| expr.use_name?(*names) }
         end
 
         # Clones the concatenated references (deeply)

data/lib/HDLRuby/hruby_low2c.rb

@@ -106,13 +106,13 @@ module HDLRuby::Low
 
         ## Generates the main for making the objects of +objs+ and
         #  for starting the simulation and including the files from +hnames+
-        def self.main(top,objs,hnames)
+        def self.main(name,init_visualizer,top,objs,hnames)
             res = Low2C.includes(*hnames)
             res << "int main(int argc, char* argv[]) {\n"
             # Build the objects.
             objs.each { |obj| res << "   #{Low2C.make_name(obj)}();\n" }
             # Starts the simulation.
-            res << "   hruby_sim_core(-1);\n"
+            res<< "   hruby_sim_core(\"#{name}\",#{init_visualizer},-1);\n"
             # Close the main.
             res << "}\n"
             return res
@@ -1612,7 +1612,9 @@ module HDLRuby::Low
         #         return "equal_value(#{self.left.to_c(level)}," +
         #                "#{self.right.to_c(level)})"
         #     when :!= then
-        #         return "not_equal_value(#{self.left.to_c(level)}," +
+        #         # return "not_equal_value(#{self.left.to_c(level)}," +
+        #         #        "#{self.right.to_c(level)})"
+        #         return "xor_value(#{self.left.to_c(level)}," +
         #                "#{self.right.to_c(level)})"
         #     when :> then
         #         return "greater_value(#{self.left.to_c(level)}," +
@@ -1681,9 +1683,12 @@ module HDLRuby::Low
             when :rr then
                 res += "dst = rotate_right_value(src0,src1,dst);\n"
             when :== then
-                res += "dst = equal_value(src0,src1,dst);\n"
+                res += "dst = equal_value(src0,src1,dst);\n" +
+                       "dst = reduce_or_value(dst,dst);"
             when :!= then
-                res += "dst = not_equal_value(src0,src1,dst);\n"
+                # res += "dst = not_equal_value(src0,src1,dst);\n"
+                res += "dst = xor_value(src0,src1,dst);\n" +
+                       "dst = reduce_or_value(dst,dst);"
             when :> then
                 res += "dst = greater_value(src0,src1,dst);\n"
             when :< then

data/lib/HDLRuby/hruby_low_resolve.rb

@@ -145,6 +145,7 @@ module HDLRuby::Low
             # puts "Resolve with #{self} and name=#{self.name}"
             # First resolve the sub reference if possible.
             if self.ref.is_a?(RefName) then
+                # puts "ref name=#{self.ref.name}"
                 obj = self.ref.resolve
                 # Look into the object for the name.
                 return obj.get_by_name(self.name)

data/lib/HDLRuby/hruby_low_without_connection.rb

@@ -31,6 +31,7 @@ module HDLRuby::Low
                     outputs_blk = Block.new(:par)
                     timed_blk = TimeBlock.new(:seq)
                     scope.each_connection do |connection|
+                        # puts "For connection: #{connection}"
                         # Check the left and right of the connection
                         # for input or output port.
                         left = connection.left

data/lib/HDLRuby/sim/hruby_sim.h

@@ -170,6 +170,12 @@ extern Value mod_value(Value src0, Value src1, Value dst);
  *  @return dst */
 extern Value not_value(Value src, Value dst);
 
+/** Compute the or of the bits a a value.
+ *  @param src the source value
+ *  @param dst the destination value
+ *  @return dst */
+extern Value reduce_or_value(Value src, Value dst);
+
 /** Computes the AND of two values.
  *  @param src0 the first source value of the and
  *  @param src1 the second source value of the and
@@ -185,43 +191,43 @@ extern Value and_value(Value src0, Value src1, Value dst);
 extern Value or_value(Value src0, Value src1, Value dst);
 
 /** Computes the XOR of two values.
- *  @param src0 the first source value of the or
- *  @param src1 the second source value of the or
+ *  @param src0 the first source value of the xor
+ *  @param src1 the second source value of the xor
  *  @param dst the destination value
  *  @return dst */
 extern Value xor_value(Value src0, Value src1, Value dst);
 
 /** Computes the left shift of two general values.
- *  @param src0 the first source value of the addition
- *  @param src1 the second source value of the addition
+ *  @param src0 the first source value of the shift
+ *  @param src1 the second source value of the shift
  *  @param dst the destination
  *  @return dst */
 Value shift_left_value(Value src0, Value src1, Value dst);
 
 /** Computes the right shift of two general values.
- *  @param src0 the first source value of the addition
- *  @param src1 the second source value of the addition
+ *  @param src0 the first source value of the shift
+ *  @param src1 the second source value of the shift
  *  @param dst the destination
  *  @return dst */
 Value shift_right_value(Value src0, Value src1, Value dst);
 
 /** Computes the equal (NXOR) of two values.
- *  @param src0 the first source value of the addition
- *  @param src1 the second source value of the addition
+ *  @param src0 the first source value of the comparison
+ *  @param src1 the second source value of the comparison
  *  @param dst the destination value
  *  @return dst */
 extern Value equal_value(Value src0, Value src1, Value dst);
 
 /** Computes the lesser comparision of two values.
- *  @param src0 the first source value of the addition
- *  @param src1 the second source value of the addition
+ *  @param src0 the first source value of the comparison
+ *  @param src1 the second source value of the comparison
  *  @param dst the destination value
  *  @return dst */
 extern Value lesser_value(Value src0, Value src1, Value dst);
 
 /** Computes the greater comparision of two values.
- *  @param src0 the first source value of the addition
- *  @param src1 the second source value of the addition
+ *  @param src0 the first source value of the comparison
+ *  @param src1 the second source value of the comparison
  *  @param dst the destination value
  *  @return dst */
 extern Value greater_value(Value src0, Value src1, Value dst);
@@ -555,39 +561,71 @@ extern unsigned long long make_delay(int value, Unit unit);
 
 
 
+/* Iterate over all the signals.
+ * @param func function to applie on each signal. */
+extern void each_all_signal(void (*func)(SignalI));
 
 /* Interface to the visualization engine. */
 
-/** Prints the time.
- *  @param time the time to show. */
-extern void print_time(unsigned long long time);
-
-/** Prints the time and goes to the next line.
- *  @param time the time to show. */
-extern void println_time(unsigned long long time);
-
-/** Prints the name of an object.
- *  @param object the object to print the name. */
-extern void print_name(Object object);
-
-/** Prints a value.
- *  @param value the value to print */
-extern void print_value(Value value);
-
-/** Prints a signal.
- *  @param signal the signal to show */
-extern void print_signal(SignalI signal);
-
-/** Prints a signal and goes to the next line.
- *  @param signal the signal to show */
-extern void println_signal(SignalI signal);
-
+typedef struct {
+    void (*print_time)(unsigned long long);
+    void (*print_name)(Object);
+    void (*print_value)(Value);
+    void (*print_signal)(SignalI);
+} PrinterS;
+
+PrinterS printer;
+
+/** Initializes the visualization printer engine.
+ *  @param print_time the time printer
+ *  @param print_name the name printer
+ *  @param print_value the value printer
+ *  @param print_signal the signal state printer. */
+void init_visualizer(void (*print_time)(unsigned long long), 
+                     void (*print_name)(Object),
+                     void (*print_value)(Value),
+                     void (*print_signal)(SignalI));
+
+// /** Prints the time.
+//  *  @param time the time to show. */
+// extern void print_time(unsigned long long time);
+// 
+// // /** Prints the time and goes to the next line.
+// //  *  @param time the time to show. */
+// // extern void println_time(unsigned long long time);
+// 
+// /** Prints the name of an object.
+//  *  @param object the object to print the name. */
+// extern void print_name(Object object);
+// 
+// /** Prints a value.
+//  *  @param value the value to print */
+// extern void print_value(Value value);
+// 
+// /** Prints a signal.
+//  *  @param signal the signal to show */
+// extern void print_signal(SignalI signal);
+// 
+// // /** Prints a signal and goes to the next line.
+// //  *  @param signal the signal to show */
+// // extern void println_signal(SignalI signal);
+
+/** Sets up the default vizualization engine.
+ *  @param name the name of the vizualization. */
+extern void init_default_visualizer(char* name);
+
+/** Sets up the vcd vizualization engine.
+ *  @param name the name of the vizualization. */
+extern void init_vcd_visualizer(char* name);
 
 /* The interface to the simulator core. */
 
 /** The simulation core function.
+ *  @param name the name of the simulation.
+ *  @param init_vizualizer the vizualizer engine initializer.
  *  @param limit the time limit in fs. */
-extern void hruby_sim_core(unsigned long long limit);
+extern void hruby_sim_core(char* name, void (*init_vizualizer)(char*),
+                           unsigned long long limit);
 
 
 

data/lib/HDLRuby/sim/hruby_sim_calc.c

@@ -714,6 +714,45 @@ static Value not_value_bitstring(Value src, Value dst) {
     return dst;
 }
 
+/** Compute the or of the bits a bitstring value.
+ *  @param src the source value
+ *  @param dst the destination value
+ *  @return dst */
+Value reduce_or_value_bitstring(Value src, Value dst) {
+    /* Compute the width of the result in bits. */
+    unsigned long long width = type_width(src->type);
+
+    /* Update the destination capacity if required. */
+    resize_value(dst,width);
+    /* Set the type and size of the destination from the type of the source.*/
+    dst->type = src->type;
+    dst->numeric = 0;
+
+    /* Get access to the source and destination data. */
+    char* src_data = src->data_str;
+    char* dst_data = dst->data_str;
+
+    /* Performs the reduce or. */
+    unsigned long long count;
+    char res;
+    for(count = 0; count < width; ++count) {
+        /* Performs the reduce or. */
+        char d = src_data[count] - '0'; /* Get and convert to bit. */
+        if ((d == (d&1)) && (res != 'x'-'0')) { /* d is defined. */
+            res |= d;
+        } else {
+            /* res is undefined. */
+            res = 'x' - '0';
+        }
+        /* Apart for the first bit, there are only 0, still we are in
+         * the loop, set it. */
+        dst_data[count] = '0';
+    }
+    dst_data[0] = res + '0';
+    /* Return the destination. */
+    return dst;
+}
+
 
 /** Computes the and of two bitstring values.
  *  @param src0 the first source value of the and
@@ -1575,6 +1614,21 @@ static Value not_value_numeric(Value src, Value dst) {
 }
 
 
+/** Compute the or of the bits a numeric value.
+ *  @param src the source value
+ *  @param dst the destination value
+ *  @return dst */
+Value reduce_or_value_numeric(Value src, Value dst) {
+    /* Sets state of the destination using the first source. */
+    dst->type = src->type;
+    dst->numeric = 1;
+
+    /* Perform the reduce or. */
+    dst->data_int = fix_numeric_type(dst->type, src->data_int != 0);
+    return dst;
+}
+
+
 /** Computes the AND of two numeric values.
  *  @param src0 the first source value of the addition
  *  @param src1 the second source value of the addition
@@ -2093,6 +2147,21 @@ Value not_value(Value src, Value dst) {
 }
 
 
+/** Compute the or of the bits a value.
+ *  @param src the source value
+ *  @param dst the destination value
+ *  @return dst */
+Value reduce_or_value(Value src, Value dst) {
+    if (src->numeric) {
+        /* The source is numeric. */
+        return reduce_or_value_numeric(src,dst);
+    } else {
+        /* The source cannot be numeric, compute bitsitrings. */
+        return reduce_or_value_bitstring(src,dst);
+    }
+}
+
+
 /** Computes the AND of two general values. 
  *  @param src0 the first source value of the addition
  *  @param src1 the second source value of the addition

data/lib/HDLRuby/sim/hruby_sim_core.c

@@ -118,9 +118,10 @@ void hruby_sim_update_signals() {
             /* Is there a change? */
             if (same_content_value(sig->c_value,sig->f_value)) continue;
             /* Yes, process the signal. */
-            println_signal(sig);
-            // printf("c_value="); print_value(sig->c_value);
-            // printf("\nf_value="); print_value(sig->f_value); printf("\n");
+            // println_signal(sig);
+            printer.print_signal(sig);
+            // printf("c_value="); printer.print_value(sig->c_value);
+            // printf("\nf_value="); printer.print_value(sig->f_value); printf("\n");
             // printf("Touched signal: %p (%s)\n",sig,sig->name);
             /* Update the current value of the signal. */
             copy_value(sig->f_value,sig->c_value);
@@ -185,7 +186,8 @@ void hruby_sim_update_signals() {
             SignalI sig = e->data;
             delete_element(e);
             /* Yes, process the signal. */
-            println_signal(sig);
+            // println_signal(sig);
+            printer.print_signal(sig);
             /* Update the current value of the signal. */
             /* Mark the corresponding code as activated. */
             /* Any edge activation. */
@@ -284,7 +286,8 @@ void hruby_sim_advance_time() {
     }
     /* Sets the new activation time. */
     hruby_sim_time = next_time;
-    println_time(hruby_sim_time);
+    // println_time(hruby_sim_time);
+    printer.print_time(hruby_sim_time);
 }
 
 
@@ -393,9 +396,18 @@ void hruby_sim_end_timed_behaviors() {
 
 
 
+// /** The simulation core function.
+//  *  @param limit the time limit in fs. */
+// void hruby_sim_core(unsigned long long limit) {
 /** The simulation core function.
+ *  @param name the name of the simulation.
+ *  @param vizualizer the vizualizer engine initializer.
  *  @param limit the time limit in fs. */
-void hruby_sim_core(unsigned long long limit) {
+void hruby_sim_core(char* name, void (*init_vizualizer)(char*),
+                           unsigned long long limit) {
+    /* Initilize the vizualizer. */
+    init_vizualizer(name);
+
     /* Initialize the time to 0. */
     hruby_sim_time = 0;
 
@@ -597,3 +609,14 @@ unsigned long long make_delay(int value, Unit unit) {
     return -1;
 }
 
+
+
+
+/* Iterate over all the signals.
+ * @param func function to applie on each signal. */
+void each_all_signal(void (*func)(SignalI)) {
+    int i;
+    for(i = 0; i<num_all_signals; ++i) {
+        func(all_signals[i]);
+    }
+}

data/lib/HDLRuby/sim/hruby_sim_vcd.c

@@ -0,0 +1,215 @@
+#include <stdio.h>
+#include <string.h>
+#include <time.h>
+#include <stdarg.h>
+#include "hruby_sim.h"
+
+
+/**
+ *  The HDLRuby simulation vcd format genertion engine, to be used with C code
+ *  generated by hruby_low2c. 
+ **/
+
+/* Global variables storing the configuration of the vcd generation. */
+
+/* The target file. */
+static FILE* vcd_file;
+
+/* The time scale unit in the ps. */
+static unsigned long long vcd_timeunit = 1;
+
+/* Accessing target file. */
+
+/** Prints to the vcd file.
+ *  @param fmt the format for handling the variadic arguments. */
+static int vcd_print(char* fmt, ...) {
+    int ret;
+
+    /* Declare a va_list type variable */
+    va_list myargs;
+
+    /* Initialise the va_list variable with the ... after fmt */
+    va_start(myargs, fmt);
+
+    /* Forward the '...' to vprintf */
+    ret = vfprintf(vcd_file, fmt, myargs);
+
+    /* Clean up the va_list */
+    va_end(myargs);
+
+    return ret;
+}
+
+
+/* Utility functions for printing in vcd format. */
+
+/* Replace all the occurences of a character with another. 
+ * CREDIT: Superlokkus */
+static char* replace_char(char* str, char find, char replace){
+    char *current_pos = strchr(str,find);
+    while (current_pos){
+        *current_pos = replace;
+        current_pos = strchr(current_pos+1,find);
+    }
+    return str;
+}
+
+
+/* Low-end print functions. */
+
+/** Prints the time.
+ *  @param time the time to show (given in ps). */
+static void vcd_print_time(unsigned long long time) {
+    vcd_print("#%llu\n",time/vcd_timeunit);
+}
+
+
+/** Prints the name of an object.
+ *  @param object the object to print the name. */
+static void vcd_print_name(Object object) {
+    /* Recurse on the owner if any. */
+    // printf("owner=%p\n",object->owner);
+    if (object->owner != NULL) {
+        vcd_print_name(object->owner);
+        vcd_print("$");
+    }
+    /* Depending on the kind of object. */
+    switch(object->kind) {
+        case SYSTEMT:
+        case SIGNALI:
+        case SCOPE:
+        case SYSTEMI:
+            /* Print the name if name. */
+            /* Trick: SystemT, SignalI, Scope and SystemI have the
+             * field name at the same place. */
+            if (((SystemI)object)->name != NULL) {
+                char name[256];
+                strncpy(name,((SystemI)object)->name,256);
+                replace_char(name,':','$');
+                vcd_print("%s",name);
+            }
+        default: /* Nothing to do */
+            break;
+    }
+}
+
+/** Prints a value.
+ *  @param value the value to print */
+static void vcd_print_value(Value value) {
+    vcd_print("b");
+    if (value->numeric) {
+        unsigned long long width = type_width(value->type);
+        unsigned long long mask = 1ULL << (width-1);
+        for(; mask > 0; mask >>= 1) {
+            vcd_print("%d",(value->data_int & mask) != 0);
+        }
+    } else {
+        /* Display a bitstring value. */
+        int i;
+        int width = type_width(value->type);
+        char* data = value->data_str;
+        if (value->capacity == 0) {
+            /* The value is empty, therefore undefined. */
+            for(i=width; i>0; --i) {
+                vcd_print("u");
+            }
+        }
+        else {
+            /* The value is not empty. */
+            for(i=width; i>0; --i) {
+                vcd_print("%c",data[i-1]);
+            } 
+        }
+    }
+}
+
+/** Prints a signal declaration.
+ *  @param signal the signal to declare */
+static void vcd_print_var(SignalI signal) {
+    vcd_print("$var wire %d ",type_width(signal->type));
+    vcd_print_name((Object)signal);
+    vcd_print(" ");
+    vcd_print_name((Object)signal);
+    vcd_print(" $end\n");
+}
+
+
+/** Prints a signal.
+ *  @param signal the signal to show */
+static void vcd_print_signal(SignalI signal) {
+    vcd_print_value(signal->f_value);
+    vcd_print(" ");
+    vcd_print_name((Object)signal);
+    vcd_print("\n");
+}
+
+
+
+
+/* high-end print functions. */
+
+/** Prints the header of the vcd file. */
+static void vcd_print_header() {
+    /* The date section. */
+    vcd_print("$date\n");
+    {
+        char text[100];
+        time_t now = time(NULL);
+        struct tm *t = localtime(&now);
+        strftime(text, sizeof(text), "%d %m %Y %H:%M", t);
+        vcd_print("   %s\n", text);
+    }
+    vcd_print("$end\n");
+
+    /* The version section. */
+    vcd_print("$version\n");
+    vcd_print("   Generated from HDLRuby simulator\n");
+    vcd_print("$end");
+    
+    /* The comment section. */
+    vcd_print("$comment\n");
+    vcd_print("   Is it an easter egg?\n");
+    vcd_print("$end\n");
+
+    /* The time scale section: for now 1ps only. */
+    vcd_print("$timescale 1ps $end\n");
+
+    /* The scope section: nothing specific. */
+    vcd_print("$scope module logic $end\n");
+
+    /* The variables declaration. */
+    each_all_signal(&vcd_print_var);
+
+    /* Ends the declarations. */
+    vcd_print("$upscope $end\n");
+    vcd_print("$enddefinitions $end\n");
+
+    /* Display the initializations. */
+    vcd_print("$dumpvars\n");
+    // Maybe nothing to do.
+    // each_all_init_signal(&vcd_print_signal);
+    vcd_print("$end\n");
+}
+
+
+/* The configuration and initialization of the vcd vizualizer. */
+
+
+/** Sets up the vcd vizualization engine.
+ *  @param name the name of the vizualization. */
+extern void init_vcd_visualizer(char* name) {
+    /* Open the resulting file with name: <name>.vcd */
+    char filename[256];
+    strncpy(filename,name,256);
+    strncat(filename,".vcd",256);
+    vcd_file = fopen(filename,"w");
+
+    /* Initialize the vizualizer printer engine. */
+    init_visualizer(&vcd_print_time,
+                    &vcd_print_name,
+                    &vcd_print_value,
+                    &vcd_print_signal);
+
+    /* Prints the header of the vcd file. */
+    vcd_print_header();
+}

data/lib/HDLRuby/sim/hruby_sim_vizualize.c

@@ -7,26 +7,51 @@
  *  generated by hruby_low2c. 
  **/
 
+/* The print function pointers. */
+
+PrinterS printer;
+
+
+/** Initializes the visualization printer engine.
+ *  @param print_time the time printer
+ *  @param print_name the name printer
+ *  @param print_value the value printer
+ *  @param print_signal the signal state printer. */
+void init_visualizer(void (*print_time)(unsigned long long), 
+                     void (*print_name)(Object),
+                     void (*print_value)(Value),
+                     void (*print_signal)(SignalI)) {
+    printer.print_time = print_time; 
+    printer.print_name = print_name; 
+    printer.print_value = print_value; 
+    printer.print_signal = print_signal; 
+}
+
+                    
+
+
+/* The default printing functions. */
+
 /** Prints the time.
  *  @param time the time to show. */
-void print_time(unsigned long long time) {
+static void default_print_time(unsigned long long time) {
     printf("# %llups",time);
 }
 
 /** Prints the time and goes to the next line.
- *  @param time the time to show. */
-void println_time(unsigned long long time) {
-    print_time(time);
+ *  @par1am time the time to show. */
+static void default_println_time(unsigned long long time) {
+    default_print_time(time);
     printf("\n");
 }
 
 /** Prints the name of an object.
  *  @param object the object to print the name. */
-void print_name(Object object) {
+static void default_print_name(Object object) {
     /* Recurse on the owner if any. */
     // printf("owner=%p\n",object->owner);
     if (object->owner != NULL) {
-        print_name(object->owner);
+        default_print_name(object->owner);
         printf("::");
     }
     /* Depending on the kind of object. */
@@ -48,7 +73,7 @@ void print_name(Object object) {
 
 /** Prints a value.
  *  @param value the value to print */
-void print_value(Value value) {
+static void default_print_value(Value value) {
     if (value->numeric) {
         unsigned long long width = type_width(value->type);
         unsigned long long mask = 1ULL << (width-1);
@@ -77,15 +102,29 @@ void print_value(Value value) {
 
 /** Prints a signal.
  *  @param signal the signal to show */
-void print_signal(SignalI signal) {
-    print_name((Object)signal);
+static void default_print_signal(SignalI signal) {
+    default_print_name((Object)signal);
     printf(": ");
-    print_value(signal->f_value);
+    default_print_value(signal->f_value);
 }
 
 /** Prints a signal and goes to the next line.
  *  @param signal the signal to show */
-void println_signal(SignalI signal) {
-    print_signal(signal);
+static void default_println_signal(SignalI signal) {
+    default_print_signal(signal);
     printf("\n");
 }
+
+
+
+/* Set up the visualizer. */
+
+/** Set up the default vizualization engine.
+ *  @param name the name of the vizualization. */
+void init_default_visualizer(char* name) {
+    /* Initialize the vizualizer printer engine. */
+    init_visualizer(&default_println_time,
+                    &default_print_name,
+                    &default_print_value,
+                    &default_println_signal);
+}

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.3.8"
+  VERSION = "2.4.1"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.3.8
+  version: 2.4.1
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-09-18 00:00:00.000000000 Z
+date: 2020-09-24 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -123,6 +123,7 @@ files:
 - lib/HDLRuby/hdr_samples/with_linear.rb
 - lib/HDLRuby/hdr_samples/with_loop.rb
 - lib/HDLRuby/hdr_samples/with_memory.rb
+- lib/HDLRuby/hdr_samples/with_multi_channels.rb
 - lib/HDLRuby/hdr_samples/with_reconf.rb
 - lib/HDLRuby/hdrcc.rb
 - lib/HDLRuby/high_samples/_adder_fault.rb
@@ -262,6 +263,7 @@ files:
 - lib/HDLRuby/sim/hruby_sim_calc.c
 - lib/HDLRuby/sim/hruby_sim_core.c
 - lib/HDLRuby/sim/hruby_sim_list.c
+- lib/HDLRuby/sim/hruby_sim_vcd.c
 - lib/HDLRuby/sim/hruby_sim_vizualize.c
 - lib/HDLRuby/sim/hruby_value_pool.c
 - lib/HDLRuby/std/channel.rb