HDLRuby 2.3.7 → 2.4.9

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Files changed (24) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +1 -0
  3. data/lib/HDLRuby/hdr_samples/bstr_bench.rb +14 -0
  4. data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb +49 -0
  5. data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +27 -0
  6. data/lib/HDLRuby/hdr_samples/with_multi_channels.rb +300 -0
  7. data/lib/HDLRuby/hdrcc.rb +10 -1
  8. data/lib/HDLRuby/hruby_bstr.rb +7 -2
  9. data/lib/HDLRuby/hruby_high.rb +8 -0
  10. data/lib/HDLRuby/hruby_low.rb +107 -8
  11. data/lib/HDLRuby/hruby_low2c.rb +31 -9
  12. data/lib/HDLRuby/hruby_low_mutable.rb +90 -2
  13. data/lib/HDLRuby/hruby_low_resolve.rb +1 -0
  14. data/lib/HDLRuby/hruby_low_without_connection.rb +1 -0
  15. data/lib/HDLRuby/sim/hruby_sim.h +82 -39
  16. data/lib/HDLRuby/sim/hruby_sim_calc.c +89 -5
  17. data/lib/HDLRuby/sim/hruby_sim_core.c +32 -6
  18. data/lib/HDLRuby/sim/hruby_sim_vcd.c +380 -0
  19. data/lib/HDLRuby/sim/hruby_sim_vizualize.c +51 -12
  20. data/lib/HDLRuby/std/fixpoint.rb +10 -2
  21. data/lib/HDLRuby/std/linear.rb +33 -13
  22. data/lib/HDLRuby/std/memory.rb +90 -20
  23. data/lib/HDLRuby/version.rb +1 -1
  24. metadata +6 -2
data/lib/HDLRuby/std/fixpoint.rb CHANGED
@@ -52,10 +52,18 @@ module HDLRuby::High::Std
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  end
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  # Redefine the multiplication and division for fixed point.
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  typ.define_operator(:*) do |left,right|
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- (left.as([isize+fsize*2])*right) >> fsize
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+ if (typ.signed?) then
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+ (left.as(signed[isize+fsize*2])*right) >> fsize
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+ else
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+ (left.as([isize+fsize*2])*right) >> fsize
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+ end
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  end
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  typ.define_operator(:/) do |left,right|
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- (left.as([isize+fsize*2]) << fsize) / right
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+ if (typ.signed?) then
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+ (left.as(signed[isize+fsize*2]) << fsize) / right
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+ else
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+ (left.as([isize+fsize*2]) << fsize) / right
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+ end
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  end
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  typ
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  end
data/lib/HDLRuby/std/linear.rb CHANGED
@@ -209,37 +209,57 @@ module HDLRuby::High::Std
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  # lv and rv are valid.
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  lvoks = lefts.each_with_index.map { |left,i| inner :"lvok#{i}" }
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  inner :rvok
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+ woks = lefts.each_with_index.map { |left,i| inner :"wok#{i}" }
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  # Run flag
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  inner :run
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  par(ev) do
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  ack <= 0
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  run <= 0
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+ hif(~run) do
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+ rvok <= 0
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+ lefts.each_with_index do |left,i|
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+ lvoks[i] <= 0
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+ # avs[i] <= 0
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+ woks[i] <= 0
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+ end
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+ end
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  hif(req | run) do
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  run <= 1
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  # Computation request.
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- right.read(rv) { rvok <= 1 }
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+ hif(~rvok) { right.read(rv) { rvok <= 1 } }
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  lefts.each_with_index do |left,i|
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- left.read(lvs[i]) { lvoks[i] <= 1 }
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+ hif(~lvoks[i]) { left.read(lvs[i]) { lvoks[i] <= 1 } }
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  # accs[i].read(avs[i])
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- hif(lvoks[i] & rvok) do
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+ hif(lvoks[i] & rvok & ~woks[i]) do
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  ack <= 1
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  run <= 0
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- # accs[i].write(add.(avs[i],mul.(lvs[i],rv)))
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  seq do
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  avs[i] <= add.(avs[i],mul.(lvs[i],rv))
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- accs[i].write(avs[i])
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+ accs[i].write(avs[i]) do
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+ woks[i] <= 1
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+ # seq do
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+ # lvoks[i] <= 0
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+ # rvok <= lvoks.reduce(:|)
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+ # end
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+ end
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  end
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  end
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+ hif (woks.reduce(:&)) do
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+ woks.each { |wok| wok <= 0 }
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+ lvoks.each { | lvok| lvok <=0 }
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+ rvok <= 0
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+ end
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  end
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  end
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- helse do
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- rvok <= 0
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- lefts.each_with_index do |left,i|
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- lvoks[i] <= 0
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- # accs[i].write(0)
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- avs[i] <= 0
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- end
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- end
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+ helse { avs.each {|av| av <= 0 } }
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+ # helse do
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+ # rvok <= 0
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+ # lefts.each_with_index do |left,i|
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+ # lvoks[i] <= 0
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+ # # accs[i].write(0)
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+ # avs[i] <= 0
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+ # end
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+ # end
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  end
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  end
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data/lib/HDLRuby/std/memory.rb CHANGED
@@ -292,17 +292,38 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
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  trig_r <= 0
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  end
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  # The read procedure.
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+ # par do
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+ # hif(rst == 0) do
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+ # # No reset, so can perform the read.
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+ # hif(trig_r == 1) do
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+ # # The trigger was previously set, read ok.
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+ # target <= dbus_r
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+ # blk.call if blk
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+ # end
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+ # # Prepare the read.
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+ # abus_r <= abus_r + 1
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+ # trig_r <= 1
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+ # end
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+ # end
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+ # The read procedure.
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  par do
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  hif(rst == 0) do
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  # No reset, so can perform the read.
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  hif(trig_r == 1) do
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  # The trigger was previously set, read ok.
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- target <= dbus_r
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- blk.call if blk
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+ # target <= dbus_r
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+ # blk.call if blk
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+ seq do
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+ # abus_r <= abus_r + 1
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+ target <= dbus_r
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+ blk.call if blk
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+ end
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+ end
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+ helse do
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+ # Prepare the read.
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+ abus_r <= abus_r + 1
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+ trig_r <= 1
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  end
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- # Prepare the read.
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- abus_r <= abus_r + 1
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- trig_r <= 1
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  end
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  end
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  end
@@ -331,18 +352,39 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
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  # Reset so switch of the access trigger.
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  trig_r <= 0
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  end
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+ # # The read procedure.
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+ # par do
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+ # hif(rst == 0) do
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+ # # No reset, so can perform the read.
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+ # hif(trig_r == 1) do
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+ # # The trigger was previously set, read ok.
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+ # target <= dbus_r
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+ # blk.call if blk
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+ # end
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+ # # Prepare the read.
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+ # abus_r <= abus_r - 1
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+ # trig_r <= 1
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+ # end
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+ # end
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  # The read procedure.
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  par do
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  hif(rst == 0) do
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  # No reset, so can perform the read.
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  hif(trig_r == 1) do
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  # The trigger was previously set, read ok.
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- target <= dbus_r
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- blk.call if blk
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+ # target <= dbus_r
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+ # blk.call if blk
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+ seq do
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+ # abus_r <= abus_r - 1
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+ target <= dbus_r
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+ blk.call if blk
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+ end
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+ end
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+ helse do
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+ # Prepare the read.
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+ abus_r <= abus_r - 1
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+ trig_r <= 1
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  end
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- # Prepare the read.
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- abus_r <= abus_r - 1
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- trig_r <= 1
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  end
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  end
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  end
@@ -541,12 +583,19 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
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  # No reset, so can perform the read.
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  hif(trig_r == 1) do
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  # The trigger was previously set, read ok.
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- target <= dbus_r
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- blk.call if blk
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+ # target <= dbus_r
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+ # blk.call if blk
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+ seq do
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+ # abus_r <= abus_r + 1
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+ target <= dbus_r
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+ blk.call if blk
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+ end
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+ end
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+ helse do
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+ # Prepare the read.
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+ abus_r <= abus_r + 1
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+ trig_r <= 1
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  end
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- # Prepare the read.
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- abus_r <= abus_r + 1
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- trig_r <= 1
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  end
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  end
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  end
@@ -613,18 +662,39 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
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  # Reset so switch of the access trigger.
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  trig_r <= 0
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  end
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+ # # The read procedure.
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+ # par do
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+ # hif(rst == 0) do
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+ # # No reset, so can perform the read.
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+ # hif(trig_r == 1) do
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+ # # The trigger was previously set, read ok.
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+ # target <= dbus_r
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+ # blk.call if blk
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+ # end
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+ # # Prepare the read.
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+ # abus_r <= abus_r - 1
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+ # trig_r <= 1
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+ # end
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+ # end
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  # The read procedure.
617
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  par do
618
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  hif(rst == 0) do
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  # No reset, so can perform the read.
620
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  hif(trig_r == 1) do
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  # The trigger was previously set, read ok.
622
- target <= dbus_r
623
- blk.call if blk
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+ # target <= dbus_r
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+ # blk.call if blk
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+ seq do
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+ # abus_r <= abus_r - 1
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+ target <= dbus_r
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+ blk.call if blk
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+ end
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+ end
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+ helse do
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+ # Prepare the read.
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+ abus_r <= abus_r - 1
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+ trig_r <= 1
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  end
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- # Prepare the read.
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- abus_r <= abus_r - 1
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- trig_r <= 1
628
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  end
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  end
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  end
data/lib/HDLRuby/version.rb CHANGED
@@ -1,3 +1,3 @@
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  module HDLRuby
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- VERSION = "2.3.7"
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+ VERSION = "2.4.9"
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  end
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: HDLRuby
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3
  version: !ruby/object:Gem::Version
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- version: 2.3.7
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+ version: 2.4.9
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  platform: ruby
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  authors:
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  - Lovic Gauthier
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  autorequire:
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  bindir: exe
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  cert_chain: []
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- date: 2020-09-06 00:00:00.000000000 Z
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+ date: 2020-10-15 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: bundler
@@ -75,6 +75,7 @@ files:
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  - lib/HDLRuby/hdr_samples/addsub.rb
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  - lib/HDLRuby/hdr_samples/addsubz.rb
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  - lib/HDLRuby/hdr_samples/alu.rb
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+ - lib/HDLRuby/hdr_samples/bstr_bench.rb
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  - lib/HDLRuby/hdr_samples/calculator.rb
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  - lib/HDLRuby/hdr_samples/counter_bench.rb
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  - lib/HDLRuby/hdr_samples/dff.rb
@@ -88,6 +89,7 @@ files:
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  - lib/HDLRuby/hdr_samples/memory_test.rb
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  - lib/HDLRuby/hdr_samples/multer_gen.rb
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  - lib/HDLRuby/hdr_samples/multer_seq.rb
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+ - lib/HDLRuby/hdr_samples/neg_arith_bench.rb
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  - lib/HDLRuby/hdr_samples/neural/a.rb
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  - lib/HDLRuby/hdr_samples/neural/a_sub.rb
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  - lib/HDLRuby/hdr_samples/neural/bw.rb
@@ -123,6 +125,7 @@ files:
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  - lib/HDLRuby/hdr_samples/with_linear.rb
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  - lib/HDLRuby/hdr_samples/with_loop.rb
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  - lib/HDLRuby/hdr_samples/with_memory.rb
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+ - lib/HDLRuby/hdr_samples/with_multi_channels.rb
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  - lib/HDLRuby/hdr_samples/with_reconf.rb
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  - lib/HDLRuby/hdrcc.rb
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  - lib/HDLRuby/high_samples/_adder_fault.rb
@@ -262,6 +265,7 @@ files:
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  - lib/HDLRuby/sim/hruby_sim_calc.c
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  - lib/HDLRuby/sim/hruby_sim_core.c
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  - lib/HDLRuby/sim/hruby_sim_list.c
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+ - lib/HDLRuby/sim/hruby_sim_vcd.c
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  - lib/HDLRuby/sim/hruby_sim_vizualize.c
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  - lib/HDLRuby/sim/hruby_value_pool.c
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  - lib/HDLRuby/std/channel.rb