HDLRuby 2.3.2 → 2.3.3

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 73fbfcef7b930ac266b56380159ffd3af64f84ce712f937f764559d8abe78ded
-  data.tar.gz: 2c7ad1ac7fac5639f70278f28dce24cdfa4328797b2b031f698421a849ee5141
+  metadata.gz: 6548ba8f8c1572f8aa254b168eab065bc5d0a06ac996d792b4082a9243a2dfc9
+  data.tar.gz: 97891dad52f2454d37755af82cf6d23b2665cccd39a44caff81701921f233931
 SHA512:
-  metadata.gz: 4112497c5716f1dd13ae9f45a4806773ae7f521b586415c2b0be4a735357765a45c2f524d33bff509f0dfc103ed47fc3aceee19e7eea98ec8d0c720d88af3153
-  data.tar.gz: 1852065b8f05fb474f6f392df45cf08269196f2f481a55d84d1a5d20ad66713a5138eb739e0146ce1761fe3f22eccb01bcea06d19e94a19b3693a01dbba4e165
+  metadata.gz: 6df258eebc8a3448824aca9bf39d24ad98c9302728c2584bb34880b8160b42a00f6b7e0fed68a4097403046e0621bf16c8048c43ce95090254f4e9e6e1ebc079
+  data.tar.gz: 73cc373d53e91a756922c8539f15283f793db0ce6e1b3e7c2ae566ae6e2c19691ee62d7dd3ac5ca1f1e19c61a809ab234aba3c790ae207327f8cd2609c76816f

data/README.md

@@ -2815,27 +2815,17 @@ This library provides a unified interface to complex communication protocols thr
 ### Using a channel
 
 A channel is used similarly to a pipe: it has an input where data can be written and an output where data can be read. The ordering of the data and the synchronization depend on the internals of the channel, e.g., a channel can be FIFO or LIFO. The interaction with the channel is done using the following methods:
- 
- * `input <name>`: generate ports in the system for reading from the channel amd associate them to `name`
- * `output <name>`: generate ports in the system for writing to the channel and associate them to `name`
- * `inout <name>`: generate ports in the system for reading and writing to the channel and associate them to `name`
- * `inner <name>`: generates inner signals for accessing directly the channel
-
-__Note__: `input`, `output`, `inout` and `inner` for channels work similarly to the ones of data types for declaring signals. In particular, `input`, `output` and `inout` are to be used in systems that do not include the channel and `inner` is to be used in the system that include the channel.
-
-When the channel ports are declared, they can be accessed using the following methods depending on whether they are writing or reading ports:
 
  * `write(<args>) <block>`: write to the channel and execute `block` when `write` completes. `args` is a list of arguments required for performing the write that depend on the channel.
  * `read(<args>) <block>`: read the channel and execute `block` when the read completes. `args` is a list of arguments required for performing the write that depend on the channel.
 
+
 For example, a system sending successive 8-bit values through a channel can be described as follows:
 
 ```ruby
 system :producer8 do |channel|
     # Inputs of the producer: clock and reset.
     input :clk, :rst
-    # Instantiate the channel ports
-    channel.output :chi
     # Inner 8-bit counter for generating values.
     [8].inner :counter
 
@@ -2843,7 +2833,7 @@ system :producer8 do |channel|
     par(clk.posedge) do
         hif(rst) { counter <= 0 }
         helse do
-            chi.write(counter) { counter <= counter + 1 }
+            channel.write(counter) { counter <= counter + 1 }
         end
     end
 end
@@ -2851,6 +2841,22 @@ end
 
 __Note__: In the code above, the channel is passed as generic argument of the system.
 
+The access points to a channel can also be handled individually by declaring ports using the following methods:
+ 
+ * `input <name>`: declares a port for reading from the channel and associate them to `name` if any
+ * `output <name>`: declares a port for writing to the channel and associate them to `name` if any
+ * `inout <name>`: declares a port for reading and writing to the channel and associate them to `name` if any
+
+Such port can then be accessed using the same `read` and `write` method of a channel, the difference being that they can also be configured for new access procedure using the `wrap` method:
+
+ * `wrap(<args>) <code>`: creates a new port whose read or write procedure has the elements of `<args>` and the ones produced by `<code>` assign to the arguments of the read or write procedure.
+
+For example, assuming `mem` is a channel whose read and write access have as argument the target address and data signals, the following code creates a port for always accessing at address 0:
+
+```ruby
+  addr0 = channel.input.wrap(0) 
+```
+
 ### Channel branches
 
 Some channel may include several branches, they are accessed by name using the following method:
@@ -2894,7 +2900,7 @@ Where `name` is the name of the channel and `block` is a procedure block describ
  The first argument of the block must be the following:
    - `blk`: the block to execute when the write completes.
  Other arguments can be freely defined, and will be required by the `write` command.
- * `brancher(name) <block>`: defines branch named +name+ described in `block`. The content of block can be any content valid for a channel, with the additional possiblity to access the internals of the upper channel.
+ * `brancher(name) <block>`: defines branch named +name+ described in `block`. The content of block can be any content valid for a channel, with the additional possibility to access the internals of the upper channel.
 
 For example, a channel implemented by a simple register of generic type `typ`, that can be set to 0 using the `reset` command can be described as follows:
 

data/lib/HDLRuby/hdr_samples/with_channel.rb

@@ -63,12 +63,13 @@ end
 
 
 # A system writing indefinitely to a channel.
+# Checking usage of channel without declaring a port.
 system :producer8 do |channel|
-    # puts "channel=#{channel}"
+    # puts "channel=#{channel}, channel methods=#{channel.methods}"
     # Inputs of the producer: clock and reset.
     input :clk, :rst
-    # Instantiate the channel ports
-    channel.output :ch
+    # # Instantiate the channel ports
+    # channel.output :ch
     # Inner 8-bit counter for generating values.
     [8].inner :counter
 
@@ -76,7 +77,8 @@ system :producer8 do |channel|
     par(clk.posedge) do
         hif(rst) { counter <= 0 }
         helse do
-            ch.write(counter) { counter <= counter + 1 }
+            # ch.write(counter) { counter <= counter + 1 }
+            channel.write(counter) { counter <= counter + 1 }
         end
     end
 end
@@ -96,20 +98,59 @@ system :consummer8 do |channel|
     end
 end
 
+# A system reading indefinitely from a channel.
+# Version without port declaration.
+system :consummer16 do |channel|
+    # Input of the consummer: a clock is enough.
+    input :clk
+    # # Instantiate the channel ports
+    # channel.input :ch
+    # Inner buffer for storing the cunsummed value.
+    [16].inner :buf
+
+    # The value consumption process
+    par(clk.posedge) do
+        # ch.read(buf)
+        channel.read(buf)
+    end
+end
+
 
 # A system testing the handshaker.
 system :hs_test do
     input :clk,:rst
 
-    # Declares the handshaker
-    handshaker([8]).(:hs)
+    # Declares two handshakers
+    handshaker([8]).(:hs0)
+    handshaker([16]).(:hs1)
 
     # # Sets the reset.
     # par(rst.posedge) { hs.reset }
+    
+    # For the first handshake
 
     # Instantiate the producer.
-    producer8(hs).(:producerI).(clk,rst)
+    producer8(hs0).(:producerI).(clk,rst)
 
     # Instantiate the consummer.
-    consummer8(hs).(:consummerI).(clk)
+    consummer8(hs0).(:consummerI).(clk)
+
+    # For the second handshaker
+    
+    # Instantiatethe consummer.
+    consummer16(hs1).(:consummer2I).(clk)
+
+    # Produce from within.
+    [16].inner :counter
+
+    # hs1.output :port
+
+    par(clk.posedge) do
+       hif(rst) { counter <= 0 }
+        helse do
+            # port.write(counter) { counter <= counter + 1 }
+            hs1.write(counter) { counter <= counter + 1 }
+        end
+    end
+
 end

data/lib/HDLRuby/hdr_samples/with_linear.rb

@@ -22,23 +22,29 @@ system :testmat do
     mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL1)
     mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memR)
     # Access ports.
-    memL0.branch(:rinc).inner :readL0
-    memL1.branch(:rinc).inner :readL1
-    memR.branch(:rinc).inner :readR
+    # # memL0.branch(:rinc).inner :readL0
+    # # memL1.branch(:rinc).inner :readL1
+    # # memR.branch(:rinc).inner :readR
+    # memL0.branch(:rinc).input :readL0
+    # memL1.branch(:rinc).input :readL1
+    # memR.branch(:rinc).input :readR
 
     # Prepares the left and acc arrays.
-    lefts = [readL0, readL1]
+    # lefts = [readL0, readL1]
+    lefts = [memL0.branch(:rinc), memL1.branch(:rinc)]
 
     # Accumulators memory.
     mem_file([8],2,clk,rst,rinc: :rst).(:memAcc)
-    memAcc.branch(:anum).inner :accs
+    # # memAcc.branch(:anum).inner :accs
+    memAcc.branch(:anum).inout :accs
     accs_out = [accs.wrap(0), accs.wrap(1)]
 
     # Layer 0 ack.
     inner :ack0
     
     # Instantiate the matrix product.
-    mac_n1([8],clk,req,ack0,lefts,readR,accs_out)
+    # mac_n1([8],clk,req,ack0,lefts,readR,accs_out)
+    mac_n1([8],clk,req,ack0,lefts,memR.branch(:rinc),accs_out)
 
     # Translation.
     # Translation memory.
@@ -46,10 +52,12 @@ system :testmat do
     # Tarnslation result
     mem_file([8],2,clk,rst,rinc: :rst).(:memF)
     # Access ports.
-    memT.branch(:anum).inner :readT
-    memF.branch(:anum).inner :writeF
+    # # memT.branch(:anum).inner :readT
+    # # memF.branch(:anum).inner :writeF
+    memT.branch(:anum).input :readT
+    memF.branch(:anum).output :writeF
     regRs = [ readT.wrap(0), readT.wrap(1) ]
-    regLs = [ accs.wrap(0), accs.wrap(1) ]
+    regLs = accs_out
     regs =  [ writeF.wrap(0), writeF.wrap(1) ]
 
     # Translater ack.
@@ -64,9 +72,10 @@ system :testmat do
     # Input memories.
     mem_dual([8],2,clk,rst, rinc: :rst,winc: :rst).(:mem2L0)
     # Access ports.
-    mem2L0.branch(:rinc).inner :read2L0
-    # memAcc.branch(:rinc).inner :accsR
-    memF.branch(:rinc).inner :readF
+    # # mem2L0.branch(:rinc).inner :read2L0
+    # # memF.branch(:rinc).inner :readF
+    # mem2L0.branch(:rinc).input :read2L0
+    # memF.branch(:rinc).input :readF
 
     # Second layer ack.
     inner :ack1
@@ -76,29 +85,40 @@ system :testmat do
 
     sub do
         # Instantiate the second matrix product.
-        # mac([8],clk,req,read2L0,accsR,res)
-        mac([8],clk,ackT,ack1,read2L0,readF,channel_port(res))
+        # mac([8],clk,ackT,ack1,read2L0,readF,channel_port(res))
+        mac([8],clk,ackT,ack1,mem2L0.branch(:rinc),memF.branch(:rinc),
+            channel_port(res))
     end
 
 
 
     # The memory initializer.
-    memL0.branch(:winc).inner :writeL0
-    memL1.branch(:winc).inner :writeL1
-    memR.branch(:winc).inner :writeR
-    memT.branch(:winc).inner :writeT
-    mem2L0.branch(:winc).inner :write2L0
+    # # memL0.branch(:winc).inner :writeL0
+    # # memL1.branch(:winc).inner :writeL1
+    # # memR.branch(:winc).inner :writeR
+    # # memT.branch(:winc).inner :writeT
+    # # mem2L0.branch(:winc).inner :write2L0
+    # memL0.branch(:winc).output :writeL0
+    # memL1.branch(:winc).output :writeL1
+    # memR.branch(:winc).output :writeR
+    # mem2L0.branch(:winc).output :write2L0
+    # memT.branch(:winc).output :writeT
     inner :fill, :fill2
     [8].inner :val
     par(clk.posedge) do
         hif(fill) do
-            writeL0.write(val)
-            writeL1.write(val+1)
-            writeR.write(val+1)
+            # writeL0.write(val)
+            # writeL1.write(val+1)
+            # writeR.write(val+1)
+            memL0.branch(:winc).write(val)
+            memL1.branch(:winc).write(val+1)
+            memR.branch(:winc).write(val+1)
         end
         hif(fill2) do
-            write2L0.write(val+2)
-            writeT.write(val+2)
+            # write2L0.write(val+2)
+            # writeT.write(val+2)
+            mem2L0.branch(:winc).write(val+2)
+            memT.branch(:winc).write(val+2)
         end
     end
 

data/lib/HDLRuby/hdrcc.rb

@@ -241,7 +241,7 @@ include HDLRuby
 # Process the command line options
 $options = {}
 $optparse = OptionParser.new do |opts|
-    opts.banner = "Usage: hdrcc.rb [options] <input file> [<output file>]"
+    opts.banner = "Usage: hdrcc.rb [options] <input file> [<output directory or file>]"
 
     opts.separator ""
     opts.separator "Where:"
@@ -323,18 +323,17 @@ $optparse = OptionParser.new do |opts|
     opts.separator ""
     opts.separator "Notice:"
     opts.separator "* If no output option is given, simply checks the input file"
-    opts.separator "* If no output file is given, the result is given through the standard output."
     opts.separator "* If no top system is given, it will be automatically searched in the input file."
     opts.separator ""
     opts.separator "Examples:"
     opts.separator "* Compile system named `adder` from `adder.rb` input file and generate `adder.yaml` low-level YAML description:"
     opts.separator "   hdrcc.rb --yaml --top adder adder.rb adder.yaml"
-    opts.separator "* Compile `adder.rb` input file and generate `adder.vhd` low-level VHDL description:"
-    opts.separator "   hdrcc.rb --vhdl adder.rb adder.vhd"
+    opts.separator "* Compile `adder.rb` input file and generate low-level VHDL description files in `adder_vhd` directory:"
+    opts.separator "   hdrcc.rb --vhdl adder.rb adder_vhd"
     opts.separator "* Check the validity of `adder.rb` input file:"
     opts.separator "   hdrcc.rb adder.rb"
-    opts.separator "* Compile system `adder` whose bit width is generic from `adder_gen.rb` input file to a 16-bit circuit whose low-level Verilog HDL description is dumped to the standard output:"
-    opts.separator "   hdrcc -v -t adder --param 16 adder_gen.rb"
+    opts.separator "* Compile system `adder` whose bit width is generic from `adder_gen.rb` input file to a 16-bit circuit whose low-level Verilog HDL description files are put in `adder_gen_v` directory:"
+    opts.separator "   hdrcc -v -t adder --param 16 adder_gen.rb adder_gen_v"
     opts.separator "* Compile system `multer` with inputs and output bit width is generic from `multer_gen.rb` input file to a 16x16->32 bit cicruit whose low-level YAML description is saved to output file `multer_gen.yaml`"
     opts.separator "hdrcc -y -t multer -p 16,16,32 multer_gen.rb multer_gen.yaml"
 

data/lib/HDLRuby/hruby_low.rb

@@ -1123,6 +1123,10 @@ module HDLRuby::Low
             return self.parent.is_a?(SystemT) ? self : self.parent.top_scope
         end
 
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
 
     end
 
@@ -2132,6 +2136,11 @@ module HDLRuby::Low
         def top_scope
             return parent.top_scope
         end
+
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
     end
 
 
@@ -2619,6 +2628,11 @@ module HDLRuby::Low
         def top_scope
             return self.scope.top_scope
         end
+
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
     end
 
 
@@ -3717,6 +3731,11 @@ module HDLRuby::Low
         def top_scope
             return self.parent.is_a?(Scope) ? self.parent : self.parent.top_scope
         end
+
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
     end
 
 

data/lib/HDLRuby/sim/hruby_sim_core.c

@@ -365,6 +365,7 @@ void* behavior_run(void* arg) {
  *  @note create a thread per timed behavior. */
 void hruby_sim_start_timed_behaviors() {
     int i;
+    pthread_mutex_lock(&hruby_sim_mutex);
     /* Sets the end flags to 0. */
     sim_end_flag = 0;
     /* Create and start the threads. */
@@ -375,6 +376,7 @@ void hruby_sim_start_timed_behaviors() {
         pthread_create(&timed_behaviors[i]->thread,NULL,
                        &behavior_run,timed_behaviors[i]);
     }
+    pthread_mutex_unlock(&hruby_sim_mutex);
 }
 
 /** Ends waiting all the threads properly terminates. */

data/lib/HDLRuby/std/channel.rb

@@ -96,6 +96,9 @@ module HDLRuby::High::Std
         def wrap(*args)
             return ChannelPortB.new(self,*args)
         end
+
+        # The scope the port has been declared in.
+        attr_reader :scope
     end
 
 
@@ -113,6 +116,7 @@ module HDLRuby::High::Std
             @namespace = namespace
             @reader_proc = reader_proc.to_proc
             @rester_proc = reseter_proc ? reseter_proc.to_proc : proc {}
+            @scope = HDLRuby::High.cur_scope
         end
 
         ## Performs a read on the channel using +args+ and +ruby_block+
@@ -157,6 +161,7 @@ module HDLRuby::High::Std
             @namespace = namespace
             @writer_proc = writer_proc.to_proc
             @reseter_proc = reseter_proc ? reseter_proc.to_proc : proc {}
+            @scope = HDLRuby::High.cur_scope
         end
 
         ## Performs a write on the channel using +args+ and +ruby_block+
@@ -206,6 +211,7 @@ module HDLRuby::High::Std
             @reader_proc  = reader_proc ? reader_proc.to_proc : proc { }
             @writer_proc  = writer_proc ? writer_proc.to_proc : proc { }
             @reseter_proc = reseter_proc ? reseter_proc.to_proc : proc {}
+            @scope = HDLRuby::High.cur_scope
         end
 
         ## Performs a read on the channel using +args+ and +ruby_block+
@@ -281,6 +287,8 @@ module HDLRuby::High::Std
                 @args_write = args.clone
                 @args_access = args.clone
             end
+
+            @scope = @port.scope
         end
 
         ## Performs a read on the channel using +args+ and +ruby_block+
@@ -332,6 +340,12 @@ module HDLRuby::High::Std
         # building a channel.
         attr_reader :namespace
 
+        # The read port if any.
+        attr_reader :read_port
+
+        # The write port if any.
+        attr_reader :write_port
+
         ## Creates a new channel instance with +name+ built from +ruby_block+.
         def initialize(name,&ruby_block)
             # Check and set the name of the channel.
@@ -346,6 +360,10 @@ module HDLRuby::High::Std
             # Keep access to self.
             obj = self
 
+            # At first there no read nor write port.
+            @read_port = nil
+            @write_port = nil
+
             # The reader input ports by name.
             @reader_inputs = {}
             # The reader output ports by name.
@@ -367,11 +385,6 @@ module HDLRuby::High::Std
             # The accesser inout ports by name.
             @accesser_inouts = {}
 
-            # # The default reset procedures (reseters), by default do nothing.
-            # @input_reseter_proc  = proc {}
-            # @output_reseter_proc = proc {}
-            # @inout_reseter_proc  = proc {}
-
             # The branch channels
             @branches = {}
 
@@ -427,6 +440,11 @@ module HDLRuby::High::Std
             HDLRuby::High.space_reg(@name) { obj }
         end
 
+        # Get the parent system.
+        def parent_system
+            return self.scope.parent_system
+        end
+
         # The methods for defining the channel
         
         # For the channel itself
@@ -606,6 +624,12 @@ module HDLRuby::High::Std
                    @writer_inouts.values
         end
 
+        ## Tells if the channel support inout port.
+        def inout?
+            return @accesser_inputs.any? || @accesser_outputs.any? ||
+                   @accesser_inouts.any?
+        end
+
         # Defines a branch in the channel named +name+ built executing
         # +ruby_block+.
         # Alternatively, a ready channel instance can be passed as argument
@@ -620,8 +644,7 @@ module HDLRuby::High::Std
                 @branches[name] = channelI
                 return self
             end
-            # No, create the branch.
-            # channelI = HDLRuby::High.channel_instance(name, &ruby_block)
+            # Now, create the branch.
             channelI = HDLRuby::High::Std.channel_instance(name, &ruby_block)
             @branches[name] = channelI
             return self
@@ -644,54 +667,83 @@ module HDLRuby::High::Std
 
         # Reader, writer and accesser side.
 
-        ## Declares the ports for the reader and assigned them to +name+.
-        def input(name)
+        ## Declares the reader port as and assigned them to +name+.
+        def input(name = nil)
             # Ensure name is a symbol.
+            name = HDLRuby.uniq_name unless name
             name = name.to_sym
+            # Ensure the port is not already existing.
+            if @read_port then
+                raise "Read port already declared for channel instance: " +
+                    self.name
+            end
+
             # Access the ports
-            loc_inputs  = @reader_inputs
-            loc_outputs = @reader_outputs
-            loc_inouts  = @reader_inouts
+            # loc_inputs  = @reader_inputs
+            # loc_outputs = @reader_outputs
+            # loc_inouts  = @reader_inouts
+            loc_inputs  = @reader_inputs.merge(@accesser_inputs)
+            loc_outputs = @reader_outputs.merge(@accesser_outputs)
+            loc_inouts  = @reader_inouts.merge(@accesser_inouts)
+            locs = loc_inputs.merge(loc_outputs).merge(loc_inouts)
             # The generated port with corresponding channel port pairs.
             port_pairs = []
-            # Add them to the current system.
-            HDLRuby::High.cur_system.open do
-                # The inputs
-                loc_inputs.each  do |name,sig|
-                    # puts "name=#{name} sig.name=#{sig.name}"
-                    port_pairs << [sig, sig.type.input(name)]
+            if HDLRuby::High.cur_system == self.parent_system then
+                # Port in same system as the channel case.
+                # Add them to the current system.
+                HDLRuby::High.cur_system.open do
+                    locs.each  do |name,sig|
+                        port_pairs << [sig, sig.type.inner(name)]
+                    end
                 end
-                # The outputs
-                loc_outputs.each do |name,sig| 
-                    port_pairs << [sig, sig.type.output(name)]
+                obj = self
+                # Make the inner connection
+                port_pairs.each do |sig, port|
+                    sig.parent.open do
+                        port.to_ref <= sig
+                    end
                 end
-                # The inouts
-                loc_inouts.each  do |name,sig| 
-                    port_pairs << [sig, sig.type.inout(name)]
+            else
+                # Port in different system as the channel case.
+                # Add them to the current system.
+                HDLRuby::High.cur_system.open do
+                    # The inputs
+                    loc_inputs.each  do |name,sig|
+                        # puts "name=#{name} sig.name=#{sig.name}"
+                        port_pairs << [sig, sig.type.input(name)]
+                    end
+                    # The outputs
+                    loc_outputs.each do |name,sig| 
+                        port_pairs << [sig, sig.type.output(name)]
+                    end
+                    # The inouts
+                    loc_inouts.each  do |name,sig| 
+                        port_pairs << [sig, sig.type.inout(name)]
+                    end
                 end
-            end
-            obj = self
-            # Make the connection of the instance.
-            HDLRuby::High.cur_system.on_instance do |inst|
-                obj.scope.open do
-                    port_pairs.each do |sig, port|
-                        RefObject.new(inst,port.to_ref) <= sig
+                obj = self
+                # Make the connection of the instance.
+                HDLRuby::High.cur_system.on_instance do |inst|
+                    obj.scope.open do
+                        port_pairs.each do |sig, port|
+                            RefObject.new(inst,port.to_ref) <= sig
+                        end
                     end
                 end
             end
 
             # Fill the reader namespace with the access to the reader signals.
-            @reader_inputs.each do |name,sig|
+            loc_inputs.each do |name,sig|
                 @reader_namespace.add_method(sig.name) do
                     HDLRuby::High.top_user.send(name)
                 end
             end
-            @reader_outputs.each do |name,sig|
+            loc_outputs.each do |name,sig|
                 @reader_namespace.add_method(sig.name) do
                     HDLRuby::High.top_user.send(name)
                 end
             end
-            @reader_inouts.each do |name,sig|
+            loc_inouts.each do |name,sig|
                 @reader_namespace.add_method(sig.name) do
                     HDLRuby::High.top_user.send(name)
                 end
@@ -701,56 +753,88 @@ module HDLRuby::High::Std
             # NOTE: for now, simply associate the channel to name.
             chp = ChannelPortR.new(@reader_namespace,@reader_proc,@input_reseter_proc)
             HDLRuby::High.space_reg(name) { chp }
+            # Save the port in the channe to avoid conflicting declaration.
+            @read_port = chp
             return chp
         end
 
         ## Declares the ports for the writer and assigned them to +name+.
-        def output(name)
+        def output(name = nil)
             # Ensure name is a symbol.
+            name = HDLRuby.uniq_name unless name
             name = name.to_sym
+            # Ensure the port is not already existing.
+            if @write_port then
+                raise "Write port already declared for channel instance: " +
+                    self.name
+            end
             # Access the ports
-            loc_inputs  = @writer_inputs
-            loc_outputs = @writer_outputs
-            loc_inouts  = @writer_inouts
+            # loc_inputs  = @writer_inputs
+            # loc_outputs = @writer_outputs
+            # loc_inouts  = @writer_inouts
+            loc_inputs  = @writer_inputs.merge(@accesser_inputs)
+            loc_outputs = @writer_outputs.merge(@accesser_outputs)
+            loc_inouts  = @writer_inouts.merge(@accesser_inouts)
+            locs = loc_inputs.merge(loc_outputs).merge(loc_inouts)
             # The generated port with corresponding channel port pairs.
             port_pairs = []
-            # Add them to the current system.
-            HDLRuby::High.cur_system.open do
-                # The inputs
-                loc_inputs.each  do |name,sig|
-                    port_pairs << [sig, sig.type.input(name)]
+            # puts "cur_system=#{HDLRuby::High.cur_system} self.parent_system=#{self.parent_system}"
+            if HDLRuby::High.cur_system == self.parent_system then
+                # puts "Inner found!"
+                # Port in same system as the channel case.
+                # Add them to the current system.
+                HDLRuby::High.cur_system.open do
+                    locs.each  do |name,sig|
+                        port_pairs << [sig, sig.type.inner(name)]
+                    end
                 end
-                # The outputs
-                loc_outputs.each do |name,sig| 
-                    port_pairs << [sig, sig.type.output(name)]
+                obj = self
+                # Make the inner connection
+                port_pairs.each do |sig, port|
+                    sig.parent.open do
+                        port.to_ref <= sig
+                    end
                 end
-                # The inouts
-                loc_inouts.each  do |name,sig| 
-                    port_pairs << [sig, sig.type.inout(name)]
+            else
+                # Portds in different system as the channel's case.
+                # Add them to the current system.
+                HDLRuby::High.cur_system.open do
+                    # The inputs
+                    loc_inputs.each  do |name,sig|
+                        port_pairs << [sig, sig.type.input(name)]
+                    end
+                    # The outputs
+                    loc_outputs.each do |name,sig| 
+                        port_pairs << [sig, sig.type.output(name)]
+                    end
+                    # The inouts
+                    loc_inouts.each  do |name,sig| 
+                        port_pairs << [sig, sig.type.inout(name)]
+                    end
                 end
-            end
-            obj = self
-            # Make the connection of the instance.
-            HDLRuby::High.cur_system.on_instance do |inst|
-                obj.scope.open do
-                    port_pairs.each do |sig, port|
-                        RefObject.new(inst,port.to_ref) <= sig
+                obj = self
+                # Make the connection of the instance.
+                HDLRuby::High.cur_system.on_instance do |inst|
+                    obj.scope.open do
+                        port_pairs.each do |sig, port|
+                            RefObject.new(inst,port.to_ref) <= sig
+                        end
                     end
                 end
             end
 
             # Fill the writer namespace with the access to the writer signals.
-            @writer_inputs.each do |name,sig|
+            loc_inputs.each do |name,sig|
                 @writer_namespace.add_method(sig.name) do
                     HDLRuby::High.top_user.send(name)
                 end
             end
-            @writer_outputs.each do |name,sig|
+            loc_outputs.each do |name,sig|
                 @writer_namespace.add_method(sig.name) do
                     HDLRuby::High.top_user.send(name)
                 end
             end
-            @writer_inouts.each do |name,sig|
+            loc_inouts.each do |name,sig|
                 @writer_namespace.add_method(sig.name) do
                     HDLRuby::High.top_user.send(name)
                 end
@@ -760,73 +844,28 @@ module HDLRuby::High::Std
             # NOTE: for now, simply associate the channel to name.
             chp = ChannelPortW.new(@writer_namespace,@writer_proc,@output_reseter_proc)
             HDLRuby::High.space_reg(name) { chp }
+            # Save the port in the channe to avoid conflicting declaration.
+            @write_port = chp
             return chp
         end
 
-        ## Declares the ports for the accesser and assigned them to +name+.
-        def inout(name)
+
+        ## Declares the accesser port and assigned them to +name+.
+        def inout(name = nil)
             # Ensure name is a symbol.
+            name = HDLRuby.uniq_name unless name
             name = name.to_sym
-            # Access the ports
-            loc_inputs  = @accesser_inputs
-            loc_outputs = @accesser_outputs
-            loc_inouts  = @accesser_inouts
-            # The generated port with corresponding channel port pairs.
-            port_pairs = []
-            # Add them to the current system.
-            HDLRuby::High.cur_system.open do
-                # The inputs
-                loc_inputs.each  do |name,sig|
-                    port_pairs << [sig, sig.type.input(name)]
-                end
-                # The outputs
-                loc_outputs.each do |name,sig| 
-                    port_pairs << [sig, sig.type.output(name)]
-                end
-                # The inouts
-                loc_inouts.each  do |name,sig| 
-                    port_pairs << [sig, sig.type.inout(name)]
-                end
-            end
-            obj = self
-            # Make the connection of the instance.
-            HDLRuby::High.cur_system.on_instance do |inst|
-                obj.scope.open do
-                    port_pairs.each do |sig, port|
-                        RefObject.new(inst,port.to_ref) <= sig
-                    end
-                end
+            # Ensure the port is not already existing.
+            if @read_port then
+                raise "Read port already declared for channel instance: " +
+                    self.name
             end
 
-            # Set ups the accesser's namespace
-            @accesser_inputs.each do |name,sig|
-                @accesser_namespace.add_method(sig.name) do
-                    HDLRuby::High.top_user.send(name)
-                end
+            if @write_port then
+                raise "Write port already declared for channel instance: " +
+                    self.name
             end
-            @accesser_outputs.each do |name,sig|
-                @accesser_namespace.add_method(sig.name) do
-                    HDLRuby::High.top_user.send(name)
-                end
-            end
-            @accesser_inouts.each do |name,sig|
-                @accesser_namespace.add_method(sig.name) do
-                    HDLRuby::High.top_user.send(name)
-                end
-            end
-
-            # Give access to the ports through name.
-            # NOTE: for now, simply associate the channel to name.
-            chp = ChannelPortA.new(@accesser_namespace,@reader_proc,@writer_proc,@inout_reseter_proc)
-            HDLRuby::High.space_reg(name) { chp }
-            return chp
-        end
 
-        ## Declares the ports for accessing the channel as an inner component
-        #  and assigned them to +name+.
-        def inner(name)
-            # Ensure name is a symbol.
-            name = name.to_sym
             # Access the ports
             loc_inputs  = @accesser_inputs.merge(@reader_inputs).
                 merge(@writer_inputs)
@@ -837,21 +876,51 @@ module HDLRuby::High::Std
             locs = loc_inputs.merge(loc_outputs).merge(loc_inouts)
             # The generated port with corresponding channel port pairs.
             port_pairs = []
-            # Add them to the current system.
-            HDLRuby::High.cur_system.open do
-                locs.each  do |name,sig|
-                    port_pairs << [sig, sig.type.inner(name)]
+            if HDLRuby::High.cur_system == self.parent_system then
+                # Port in same system as the channel case.
+                # Add them to the current system.
+                HDLRuby::High.cur_system.open do
+                    locs.each  do |name,sig|
+                        port_pairs << [sig, sig.type.inner(name)]
+                    end
                 end
-            end
-            obj = self
-            # Make the inner connection
-            port_pairs.each do |sig, port|
-                sig.parent.open do
-                    port.to_ref <= sig
+                obj = self
+                # Make the inner connection
+                port_pairs.each do |sig, port|
+                    sig.parent.open do
+                        port.to_ref <= sig
+                    end
+                end
+            else
+                # Port in different system as the channel case.
+                # Add them to the current system.
+                HDLRuby::High.cur_system.open do
+                    # The inputs
+                    loc_inputs.each  do |name,sig|
+                        # puts "name=#{name} sig.name=#{sig.name}"
+                        port_pairs << [sig, sig.type.input(name)]
+                    end
+                    # The outputs
+                    loc_outputs.each do |name,sig| 
+                        port_pairs << [sig, sig.type.output(name)]
+                    end
+                    # The inouts
+                    loc_inouts.each  do |name,sig| 
+                        port_pairs << [sig, sig.type.inout(name)]
+                    end
+                end
+                obj = self
+                # Make the connection of the instance.
+                HDLRuby::High.cur_system.on_instance do |inst|
+                    obj.scope.open do
+                        port_pairs.each do |sig, port|
+                            RefObject.new(inst,port.to_ref) <= sig
+                        end
+                    end
                 end
             end
 
-            # Set ups the accesser's namespace
+            # Fill the reader namespace with the access to the reader signals.
             loc_inputs.each do |name,sig|
                 @accesser_namespace.add_method(sig.name) do
                     HDLRuby::High.top_user.send(name)
@@ -872,37 +941,121 @@ module HDLRuby::High::Std
             # NOTE: for now, simply associate the channel to name.
             chp = ChannelPortA.new(@accesser_namespace,@reader_proc,@writer_proc,@inout_reseter_proc)
             HDLRuby::High.space_reg(name) { chp }
+            # Save the port in the channe to avoid conflicting declaration.
+            @read_port = chp
+            @write_port = chp
             return chp
         end
 
+        # ## Declares the ports for accessing the channel as an inner component
+        # #  and assigned them to +name+.
+        # def inner(name)
+        #     # Ensure name is a symbol.
+        #     name = name.to_sym
+        #     # Access the ports
+        #     loc_inputs  = @accesser_inputs.merge(@reader_inputs).
+        #         merge(@writer_inputs)
+        #     loc_outputs = @accesser_outputs.merge(@reader_outputs).
+        #         merge(@writer_outputs)
+        #     loc_inouts  = @accesser_inouts.merge(@reader_inouts).
+        #         merge(@writer_inouts)
+        #     locs = loc_inputs.merge(loc_outputs).merge(loc_inouts)
+        #     # The generated port with corresponding channel port pairs.
+        #     port_pairs = []
+        #     # Add them to the current system.
+        #     HDLRuby::High.cur_system.open do
+        #         locs.each  do |name,sig|
+        #             port_pairs << [sig, sig.type.inner(name)]
+        #         end
+        #     end
+        #     obj = self
+        #     # Make the inner connection
+        #     port_pairs.each do |sig, port|
+        #         sig.parent.open do
+        #             port.to_ref <= sig
+        #         end
+        #     end
+
+        #     # Set ups the accesser's namespace
+        #     loc_inputs.each do |name,sig|
+        #         @accesser_namespace.add_method(sig.name) do
+        #             HDLRuby::High.top_user.send(name)
+        #         end
+        #     end
+        #     loc_outputs.each do |name,sig|
+        #         @accesser_namespace.add_method(sig.name) do
+        #             HDLRuby::High.top_user.send(name)
+        #         end
+        #     end
+        #     loc_inouts.each do |name,sig|
+        #         @accesser_namespace.add_method(sig.name) do
+        #             HDLRuby::High.top_user.send(name)
+        #         end
+        #     end
+
+        #     # Give access to the ports through name.
+        #     # NOTE: for now, simply associate the channel to name.
+        #     chp = ChannelPortA.new(@accesser_namespace,@reader_proc,@writer_proc,@inout_reseter_proc)
+        #     HDLRuby::High.space_reg(name) { chp }
+        #     return chp
+        # end
+
+
         
         ## Performs a read on the channel using +args+ and +ruby_block+
         #  as arguments.
+        #  NOTE:
+        #  * Will generate a port if not present.
+        #  * Will generate an error if a read is tempted while the read
+        #    port has been declared within another system.
         def read(*args,&ruby_block)
-            # Gain access to the reader as local variable.
-            reader_proc = @reader_proc
-            # # The context is the one of the reader.
-            # Execute the code generating the reader in context.
-            HDLRuby::High.space_push(@namespace)
-            HDLRuby::High.cur_block.open do
-                instance_exec(ruby_block,*args,&reader_proc)
+            # Is there a port to read?
+            unless self.read_port then
+                # No, generate a new one.
+                # Is it possible to be inout?
+                if self.inout? then
+                    # Yes, create an inout port.
+                    self.inout(HDLRuby.uniq_name)
+                else
+                    # No, create an input port.
+                    self.input(HDLRuby.uniq_name)
+                end
             end
-            HDLRuby::High.space_pop
+            # Ensure the read port is within current system.
+            unless self.read_port.scope.system != HDLRuby::High.cur_system then
+                raise "Cannot read from a port external of current system for channel " + self.name
+            end
+            # Performs the read.
+            self.read_port.read(*args,&ruby_block)
         end
         
         ## Performs a write on the channel using +args+ and +ruby_block+
         #  as arguments.
+        #  NOTE:
+        #  * Will generate a port if not present.
+        #  * Will generate an error if a read is tempted while the read
+        #    port has been declared within another system.
         def write(*args,&ruby_block)
-            # Gain access to the writer as local variable.
-            writer_proc = @writer_proc
-            # # The context is the one of the writer.
-            # Execute the code generating the writer in context.
-            HDLRuby::High.space_push(@namespace)
-            HDLRuby::High.cur_block.open do
-                instance_exec(ruby_block,*args,&writer_proc)
+            # Is there a port to write?
+            unless self.write_port then
+                # No, generate a new one.
+                # Is it possible to be inout?
+                if self.inout? then
+                    # Yes, create an inout port.
+                    self.inout(HDLRuby.uniq_name)
+                else
+                    # No, create an output port.
+                    self.output(HDLRuby.uniq_name)
+                end
             end
-            HDLRuby::High.space_pop
+            # Ensure the write port is within current system.
+            unless self.write_port.scope.system != HDLRuby::High.cur_system then
+                raise "Cannot write from a port external of current system for channel " + self.name
+            end
+            # Performs the write.
+            self.write_port.write(*args,&ruby_block)
         end
+        
 
         ## Performs a reset on the channel using +args+ and +ruby_block+
         #  as arguments.
@@ -925,6 +1078,8 @@ module HDLRuby::High::Std
         # Create a new object wrapper for +obj+.
         def initialize(obj)
             @obj = obj
+
+            @scope = HDLRuby::High.cur_scope
         end
 
         # Port read with arguments +args+ executing +ruby_block+ in

data/lib/HDLRuby/std/memory.rb

@@ -889,11 +889,11 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             rst_name = br_rsts[:winc].to_sym
         else
             rst_name = rst.name
-            reader_input rst_name
+            writer_input rst_name
         end
         # Declares the address counter.
         [size.width-1].inner :abus_w
-        reader_inout :abus_w
+        writer_inout :abus_w
 
         # Defines the write procedure at address +addr+
         # using +target+ as target of access result.

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.3.2"
+  VERSION = "2.3.3"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.3.2
+  version: 2.3.3
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-07-30 00:00:00.000000000 Z
+date: 2020-08-09 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler