HDLRuby 2.2.3 → 2.2.5

checksums.yaml

@@ -1,7 +1,7 @@
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data/lib/HDLRuby/hruby_high.rb

@@ -2045,11 +2045,11 @@ module HDLRuby::High
             # return If.new(condition) { self }
             # Remove self from the current block.
             obj = self
-            High.cur_block.delete_statement!(obj)
+            ::HDLRuby::High.cur_block.delete_statement!(obj)
             # Creates the if statement.
             stmnt = If.new(condition) { add_statement(obj) }
             # Add it to the current block.
-            High.cur_block.add_statement(stmnt)
+            ::HDLRuby::High.cur_block.add_statement(stmnt)
             # Returns the result.
             return stmnt
         end

data/lib/HDLRuby/hruby_low.rb

@@ -3340,7 +3340,7 @@ module HDLRuby::Low
 
         # Clones the TimeRepeat (deeply)
         def clone
-            return TimeRepeat(@statement.clone,@delay.clone)
+            return TimeRepeat.new(@statement.clone,@delay.clone)
         end
 
         # Iterates over the expression children if any.

data/lib/HDLRuby/hruby_low2c.rb

@@ -620,8 +620,9 @@ module HDLRuby::Low
 
             # Is it a clocked behavior?
             events = self.each_event.to_a
-            if events.empty? then
+            if events.empty? && !self.is_a?(TimeBehavior) then
                 # No events, this is not a clock behavior.
+                # And it is not a time behavior neigther.
                 # Generate the events list from the right values.
                 # First get the references.
                 refs = self.block.each_node_deep.select do |node|
@@ -1429,10 +1430,15 @@ module HDLRuby::Low
 
             # Declares the data.
             # Create the bit string.
-            str = self.content.is_a?(BitString) ?
-                self.content.to_s : self.content.to_s(2).rjust(32,"0")
-            # Sign extend.
-            str = str.rjust(self.type.width, self.type.signed ? str[-1] : "0")
+            # str = self.content.is_a?(BitString) ?
+            #     self.content.to_s : self.content.to_s(2).rjust(32,"0")
+            if self.content.is_a?(BitString) then
+                str = self.content.is_a?(BitString) ?
+                    self.content.to_s : self.content.to_s(2).rjust(32,"0")
+            else
+                sign = self.content>=0 ? "0" : "1"
+                str = self.content.abs.to_s(2).rjust(width,sign).upcase
+            end
             # Is it a fully defined number?
             if str =~ /^[01]+$/ then
                 # Yes, generate a numeral value.

data/lib/HDLRuby/hruby_low2vhd.rb

@@ -727,11 +727,20 @@ module HDLRuby::Low
             # It is assumed that the inners are all in declared in the
             # direct sub block and that they represent variables, i.e.,
             # Low::to_upper_space! and Low::with_var! has been called.
-            vars = self.block.each_inner.to_a 
+            vars = self.block.each_inner.to_a
 
             # The resulting string.
-            res = " " * (level*3)
+            res = ""
+
+            # Generate the TimeRepeat as different processes if any.
+            self.block.each_statement_deep do |stmnt|
+                if stmnt.is_a?(TimeRepeat) then
+                    res << stmnt.process_to_vhdl(vars,level)
+                end
+            end
+
             # Generate the header.
+            res << " " * (level*3)
             unless  self.block.name.empty? then
                 res << Low2VHDL.vhdl_name(self.block.name) << ": "
             end
@@ -797,6 +806,11 @@ module HDLRuby::Low
                 # Generate the body directly.
                 res << self.block.to_vhdl(vars,level+1)
             end
+            # Insert an infinite wait is the top block is a timed block.
+            if self.block.is_a?(TimeBlock) then
+                res << " " * ((level+1)*3)
+                res << "wait;\n"
+            end
             # Close the process.
             res << " " * (level*3)
             res << "end process;\n\n"
@@ -990,12 +1004,41 @@ module HDLRuby::Low
 
     ## Extends the TimeRepeat class with generation of HDLRuby::High text.
     class TimeRepeat
-
         # Generates the text of the equivalent HDLRuby::High code.
         # +vars+ is the list of the variables and
         # +level+ is the hierachical level of the object.
         def to_vhdl(vars,level = 0)
-            raise AnyError, "Internal error: TimeRepeat not supported yet for conversion to VHDL."
+            # Nothing to do, see process_to_vhdl
+            return ""
+        end
+
+        # Generates the text of the equivalent HDLRuby::High code as a new
+        # process.
+        # +vars+ is the list of the variables and
+        # +level+ is the hierachical level of the object.
+        def process_to_vhdl(vars,level = 0)
+            # Generate a separate process for the repeated statement with
+            # a wait.
+            # The resulting string.
+            res = " " * (level*3)
+            # Generate the header.
+            unless  self.block.name.empty? then
+                res << Low2VHDL.vhdl_name(self.block.name) << ": "
+            end
+            res << "process \n"
+            # Generate the content.
+            res << " " * (level*3)
+            res << "begin\n"
+            # Adds the wait.
+            res << " " * ((level+1)*3)
+            res << "wait for " << self.delay.to_vhdl(level) << ";\n" 
+            # Generate the remaining of the body.
+            res << self.statement.to_vhdl(vars,level+1)
+            # Close the process.
+            res << " " * (level*3)
+            res << "end process;\n\n"
+            # Return the result.
+            return res
         end
     end
 
@@ -1107,7 +1150,8 @@ module HDLRuby::Low
                     /[01]/ =~ self.content[-1] ? "0" : self.content[-1]
                 return '"' + self.content.to_s.rjust(width,sign).upcase + '"'
             else
-                sign = self.type.signed? ? (self.content>=0 ? "0" : "1") : "0"
+                # sign = self.type.signed? ? (self.content>=0 ? "0" : "1") : "0"
+                sign = self.content>=0 ? "0" : "1"
                 return '"' + self.content.abs.to_s(2).rjust(width,sign).upcase + '"'
             end
         end

data/lib/HDLRuby/hruby_low_bool2select.rb

@@ -129,6 +129,17 @@ module HDLRuby::Low
         end
     end
 
+    ## Extends the TimeRepeat class with functionality for converting booleans
+    #  in assignments to setlect operators.
+    class TimeRepeat
+        # Converts booleans in assignments to select operators.
+        def boolean_in_assign2select!
+            # Simply recurse on the stamtement.
+            self.statement.boolean_in_assign2select!
+            return self
+        end
+    end
+
 
     ## Extends the Block class with functionality for converting booleans
     #  in assignments to select operators.

data/lib/HDLRuby/hruby_low_mutable.rb

@@ -436,7 +436,7 @@ module HDLRuby::Low
             # Assign the replaced nodes.
             node2rep_done.each do |node,rep|
                 reassign = node2reassign[node][1].clone
-                self.parent.
+                self.parent.parent.
                     add_connection(Connection.new(reassign,node.clone))
             end
         end

data/lib/HDLRuby/hruby_low_without_select.rb

@@ -108,6 +108,20 @@ module HDLRuby::Low
     end
 
 
+    ## Extends the TimeRepeat class with functionality for converting booleans
+    #  in assignments to select operators.
+    class TimeRepeat
+        # Extract the Select expressions.
+        def extract_selects!
+            # Simply recruse on the statement.
+            if self.statement.is_a?(Block) then
+                return []
+            else
+                return self.statement.extract_selects!
+            end
+        end
+    end
+
 
     ## Extends the Block class with functionality for converting select
     #  expressions to case statements.

data/lib/HDLRuby/hruby_verilog.rb

@@ -113,6 +113,65 @@ class Block
         puts "Block to_verilog not found" # For debugging
     end
 
+    # Extract and convert to verilog the TimeRepeat statements.
+    # NOTE: work only on the current level of the block (should be called
+    # through each_block_deep).
+    def repeat_to_verilog!
+        code = ""
+        # Gather the TimeRepeat statements.
+        repeats = self.each_statement.find_all { |st| st.is_a?(TimeRepeat) }
+        # Remove them from the block.
+        repeats.each { |st| self.delete_statement!(st) }
+        # Generate them separately in timed always processes.
+        repeats.each do |st|
+            code << "   always #{st.delay.to_verilog} begin\n"
+
+            # Perform "scheduling" using the method "flatten".
+            block = st.statement.flatten(st.statement.mode.to_s)
+
+            # Declaration of "inner" part within "always".
+            block.each_inner do |inner|
+                # if regs.include?(inner.name) then
+                if regs.include?(inner.to_verilog) then
+                    code << "      reg"
+                else
+                    code << "      wire"
+                end
+
+                # Variable has "base", but if there is width etc, it is not in "base".
+                # It is determined by an if.
+                if inner.type.base? 
+                    if inner.type.base.base? 
+                        # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+                        code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
+                    else
+                        # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+                        code << "#{inner.type.to_verilog} #{inner.to_verilog}"
+                    end
+                else
+                    # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
+                    code << " #{inner.type.to_verilog}#{inner.to_verilog}"
+                end
+                if inner.value then
+                    # There is an initial value.
+                    code << " = #{inner.value.to_verilog}"
+                end
+                code << ";\n"
+            end
+
+            # Translate the block that finished scheduling.
+            block.each_statement do |statement|
+                code  << "\n      #{statement.to_verilog(block.mode.to_s)}"
+            end
+
+            $fm.fm_par.clear()
+
+            code << "\n   end\n\n"
+        end
+        return code
+    end
+
+
     # Process top layer of Block.
     # Determine whether there is a block under block and convert it.
     def flatten(mode = nil)
@@ -1587,20 +1646,20 @@ end
 # One of two people, TimeWait and Delay.
 class TimeWait
     def to_verilog(mode=nil)
-        return self.delay.to_verilog
+        return self.delay.to_verilog + "\n"
     end
 end
 class Delay
     def to_verilog
         time = self.value.to_s
         if(self.unit.to_s == "ps") then
-            return "##{time}\n"
+            return "##{time}"
         elsif(self.unit.to_s == "ns")
-            return "##{time}000\n"
+            return "##{time}000"
         elsif(self.unit.to_s == "us")
-            return "##{time}000000\n"
+            return "##{time}000000"
         elsif(self.unit.to_s == "ms")
-            return "##{time}000000000\n"
+            return "##{time}000000000"
         end
     end
 end
@@ -1691,7 +1750,10 @@ class SystemT
         end
         # When only input is used, it is necessary to close (), so it branches with if.
         if outputs.empty? && inout.empty? then
-            code << " #{inputs.last.to_verilog} ); \n" unless inputs.empty?
+            # code << " #{inputs.last.to_verilog} ); \n" unless inputs.empty?
+            if (inputs.empty?)
+                code << " ); \n"
+            end
         else
             code << " #{inputs.last.to_verilog}," unless inputs.empty?
         end
@@ -1896,8 +1958,14 @@ class SystemT
         # Translation of behavior part (always).
         self.each_behavior do |behavior|
             if behavior.block.is_a?(TimeBlock) then
+                # Extract and translate the TimeRepeat separately.
+                behavior.each_block_deep do |blk|
+                    code << blk.repeat_to_verilog!
+                end
+                # And generate an initial block.
                 code << "   initial begin\n"
             else
+                # Generate a standard process.
                 code << "   always @( "
                 # If there is no "always" condition, it is always @("*").
                 if behavior.each_event.to_a.empty? then

data/lib/HDLRuby/sim/hruby_sim.h

@@ -143,6 +143,13 @@ extern Value add_value(Value src0, Value src1, Value dst);
  *  @return dst */
 extern Value sub_value(Value src0, Value src1, Value dst);
 
+/** Computes the multiplication of two general values.
+ *  @param src0 the first source value of the addition
+ *  @param src1 the second source value of the addition
+ *  @param dst the destination value
+ *  @return dst */
+extern Value mul_value(Value src0, Value src1, Value dst);
+
 /** Computes the not of a value.
  *  @param src the source value of the not
  *  @param dst the destination value

data/lib/HDLRuby/sim/hruby_sim_calc.c

@@ -238,9 +238,9 @@ void resize_value(Value value, int size) {
  *  @param data the source data */
 void set_value(Value value, int numeric, void* data) {
     value->numeric = numeric;
-    if (numeric)
+    if (numeric) {
         value->data_int = *((unsigned long long*)data);
-    else  {
+    } else  {
         memcpy(value->data_str,data,type_width(value->type)*sizeof(char));
     }
 }
@@ -359,7 +359,7 @@ static Value set_bitstring_value(Value src, Value dst) {
     unsigned long long i;
     /* Resize dst to match the width. */
     resize_value(dst,width);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = src->type;
     dst->numeric = 0;
 
@@ -379,6 +379,29 @@ static Value set_bitstring_value(Value src, Value dst) {
 }
 
 
+/** Sets a value to undefined.
+ *  @param dst the destination value
+ *  @return the destination value */
+static Value set_undefined_bitstring(Value dst) {
+    /* Compute the width of the result in bits. */
+    unsigned long long width = type_width(dst->type);
+
+    /* set the type and size of the destination. */
+    dst->numeric = 0;
+
+    /* Get access to the destination data. */
+    char* dst_data = dst->data_str;
+
+    /* undefine the destination. */
+    unsigned long long count;
+    for(count = 0; count < width; ++count) {
+        dst_data[count] = 'x';
+    }
+    /* Return the destination. */
+    return dst;
+}
+
+
 /** Computes the neg of a bitstring value.
  *  @param src the source value of the not
  *  @param dst the destination value
@@ -389,7 +412,7 @@ static Value neg_value_bitstring(Value src, Value dst) {
 
     /* Update the destination capacity if required. */
     resize_value(dst,width);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = src->type;
     dst->numeric = 0;
 
@@ -434,7 +457,7 @@ static Value add_value_bitstring(Value src0, Value src1, Value dst) {
 
     /* Update the destination capacity if required. */
     resize_value(dst,width0);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = src0->type;
     dst->numeric = 0;
 
@@ -503,7 +526,7 @@ static Value sub_value_bitstring(Value src0, Value src1, Value dst) {
 
     /* Update the destination capacity if required. */
     resize_value(dst,width0);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = src0->type;
     dst->numeric = 0;
 
@@ -572,7 +595,7 @@ static Value not_value_bitstring(Value src, Value dst) {
 
     /* Update the destination capacity if required. */
     resize_value(dst,width);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = src->type;
     dst->numeric = 0;
 
@@ -611,7 +634,7 @@ static Value and_value_bitstring(Value src0, Value src1, Value dst) {
 
     /* Update the destination capacity if required. */
     resize_value(dst,width0);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = src0->type;
     dst->numeric = 0;
 
@@ -680,7 +703,7 @@ static Value or_value_bitstring(Value src0, Value src1, Value dst) {
 
     /* Update the destination capacity if required. */
     resize_value(dst,width0);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = src0->type;
     dst->numeric = 0;
 
@@ -749,7 +772,7 @@ static Value xor_value_bitstring(Value src0, Value src1, Value dst) {
 
     /* Update the destination capacity if required. */
     resize_value(dst,width0);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = src0->type;
     dst->numeric = 0;
 
@@ -953,7 +976,7 @@ static Value equal_value_bitstring(Value src0, Value src1, Value dst) {
 
     /* Update the destination capacity if required. */
     resize_value(dst,width0);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = src0->type;
     dst->numeric = 0;
 
@@ -1026,7 +1049,7 @@ static Value select_value_bitstring(Value cond, Value dst, unsigned int num,
 
     /* Update the destination capacity if required. */
     resize_value(dst,width);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = src->type;
     dst->numeric = 0;
     char *dst_data = dst->data_str;
@@ -1098,7 +1121,7 @@ static Value cast_value_bitstring(Value src, Type type, Value dst) {
 
     /* Update the destination capacity if required. */
     resize_value(dst,width);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = type;
     dst->numeric = 0;
 
@@ -1221,7 +1244,7 @@ Value read_range_bitstring(Value src, long long first, long long last,
 
     /* Update the destination capacity if required. */
     resize_value(dst,length);
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = make_type_vector(get_type_bit(),length);
     dst->numeric = 0;
 
@@ -1249,6 +1272,7 @@ Value write_range_bitstring(Value src, long long first, long long last,
         last = first;
         first = tmp;
     }
+    // printf("Initially first=%lld, last=%lld\n",first,last);
     /* Get the widths of the source and the desintation. */
     unsigned long long src_width = type_width(src->type);
     unsigned long long dst_width = type_width(dst->type);
@@ -1256,6 +1280,8 @@ Value write_range_bitstring(Value src, long long first, long long last,
     unsigned long long bw = dst->type->base;
     first *= bw;
     last *=  bw;
+    last += bw-1;
+    // printf("bw=%lld, first=%lld, last=%lld\n",bw,first,last);
     /* Access the source and destination bitstring data. */
     char* dst_data = dst->data_str;
     char* src_data = src->data_str;
@@ -1354,6 +1380,22 @@ static Value sub_value_numeric(Value src0, Value src1, Value dst) {
 }
 
 
+/** Computes the multiplication of two numeric values.
+ *  @param src0 the first source value of the addition
+ *  @param src1 the second source value of the addition
+ *  @param dst the destination value
+ *  @return dst */
+static Value mul_value_numeric(Value src0, Value src1, Value dst) {
+    /* Sets state of the destination using the first source. */
+    dst->type = src0->type;
+    dst->numeric = 1;
+
+    /* Perform the addition. */
+    dst->data_int = src0->data_int * src1->data_int;
+    return dst;
+}
+
+
 /** Computes the NOT of a numeric value.
  *  @param src the source value of the not
  *  @param dst the destination value
@@ -1605,7 +1647,7 @@ Value read_range_numeric(Value value, long long first, long long last,
     length *= bw;
     // printf("first=%lld last=%lld bw=%llu length=%lld\n",first,last,bw,length);
 
-    /* set the type and size of the destination the the type of the source. */
+    /* Set the type and size of the destination from the type of the source.*/
     dst->type = make_type_vector(get_type_bit(),length);
     dst->numeric = 1;
 
@@ -1748,6 +1790,27 @@ Value sub_value(Value src0, Value src1, Value dst) {
 }
 
 
+/** Computes the multiplication of two general values.
+ *  @param src0 the first source value of the addition
+ *  @param src1 the second source value of the addition
+ *  @param dst the destination value
+ *  @return dst */
+Value mul_value(Value src0, Value src1, Value dst) {
+    /* Might allocate a new value so save the current pool state. */
+    unsigned int pos = get_value_pos();
+    /* Do a numeric computation if possible, otherwise fallback to bitstring
+     * computation. */
+    if (src0->numeric && src1->numeric) {
+        /* Both sources are numeric. */
+        return mul_value_numeric(src0,src1,dst);
+    } else {
+        /* Cannot compute (for now), simply undefines the destination. */
+        set_undefined_bitstring(dst);
+    }
+    return dst;
+}
+
+
 /** Computes the NOT of a general value.
  *  @param src the source value of the not
  *  @param dst the destination value
@@ -2199,14 +2262,14 @@ RefRangeS make_ref_rangeS(SignalI signal, unsigned long long first,
  *  @param value the value to convert
  *  @return the resulting int. */
 unsigned long long value2integer(Value value) {
+    unsigned long long width = type_width(value->type);
     /* If the value is numeric, just return its data as is. */
     if (value->numeric) {
-        return value->data_int;
+        return value->data_int & ~((unsigned long long)(-1LL) << width);
     }
     /* Otherwise convert the bitstring to an integer if possible,
      * but return 0 in case of failure. */
     /* Gets the width of the value. */
-    unsigned long long width = type_width(value->type);
     unsigned long long res = 0;
     unsigned long long i;
     char bit;

data/lib/HDLRuby/sim/hruby_sim_core.c

@@ -496,7 +496,7 @@ void transmit_to_signal_range(Value value, RefRangeS ref) {
     SignalI signal = ref.signal;
     unsigned long long first = ref.first;
     unsigned long long last = ref.last;
-    // printf("Tansmit to signal range: %s(%p)\n",signal->name,signal);
+    // printf("Tansmit to signal range: %s(%p) [%lld:%lld]\n",signal->name,signal,first,last);
     /* Can transmit, copy the content. */
     if (signal->fading)
         signal->f_value = write_range(value,first,last,signal->f_value);

data/lib/HDLRuby/std/channel.rb

@@ -747,7 +747,9 @@ module HDLRuby::High::Std
             obj = self
             # Make the inner connection
             port_pairs.each do |sig, port|
-                port.to_ref <= sig
+                sig.parent.open do
+                    port.to_ref <= sig
+                end
             end
 
             # Set ups the accesser's namespace

data/lib/HDLRuby/std/memory.rb

@@ -47,7 +47,7 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
         inner          :"rwb_#{p}"  # Read/!Write
     end
     # Declare the memory content.
-    typ[awidth].inner :mem
+    typ[-size].inner :mem
 
     # Defines the ports of the memory as branchs of the channel.
     n.times do |p|
@@ -241,7 +241,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
     [awidth].inner :abus_r_reg
 
     # Declare the memory content.
-    typ[awidth].inner :mem
+    typ[-size].inner :mem
 
     # Processes handling the memory access.
     par(clk.posedge) do
@@ -339,9 +339,14 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
         # using +target+ as target of access result.
         reader do |blk,target|
             # By default the read trigger is 0.
-            top_block.unshift { trig_r <= 0 }
-            # The read procedure.
             rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst==1) { abus_r <= -1 }
+                # Reset so switch of the access trigger.
+                trig_r <= 0
+            end
+            # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
@@ -354,10 +359,6 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     abus_r <= abus_r + 1
                     trig_r <= 1
                 end
-                helse do
-                    # Initialize the address to -1
-                    abus_r <= -1
-                end
             end
         end
     end
@@ -378,24 +379,26 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
         # using +target+ as target of access result.
         writer do |blk,target|
             # By default the read trigger is 0.
-            top_block.unshift { trig_w <= 0 }
-            # The write procedure.
             rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst == 1) { abus_w <= -1 }
+                # Reset so switch of the access trigger.
+                trig_w <= 0
+            end
+            # The write procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the write.
                     hif(trig_w == 1) do
                         # The trigger was previously set, write ok.
-                        blk.call if blk
-                    end
+                        blk.call
+                    end if blk
                     # Prepare the write.
                     abus_w <= abus_w + 1
                     trig_w <= 1
                     dbus_w <= target
                 end
-                helse do
-                    abus_w <= -1
-                end
             end
         end
     end

data/lib/HDLRuby/test_hruby_high.rb

@@ -273,20 +273,23 @@ begin
     if systemI1Statements.size != 4 then
         puts "Error: invalid number of statements, got #{systemI1Statements.size} but expecting 4."
         success = false
-    elsif !systemI1Statements[0].is_a?(Transmit) then
-        puts "Error: invalid first statement, got #{systemI1Statements[0].class} but expecting Transmit."
+    elsif !systemI1Statements[0].is_a?(If) then
+        puts "Error: invalid first statement, got #{systemI1Statements[0].class} but expecting If."
         success = false
-    elsif systemI1Statements[0].left.object.name != :o1 then
-        puts "Error: invalid first statement left, got #{systemI1Statements[0].left.object.name} but expecting o1."
+    elsif !systemI1Statements[0].yes.last_statement.is_a?(Transmit) then
+        puts "Error: invalid content of first if statement, got #{systemI1Statements[0].yes.class} but expecting Transmit."
         success = false
-    elsif systemI1Statements[0].right.operator != :* then
-        puts "Error: invalid first statement right operator, got #{systemI1Statements[0].right.operator} but expecting *."
+    elsif systemI1Statements[0].yes.last_statement.left.object.name != :o1 then
+        puts "Error: invalid content of first if statement left, got #{systemI1Statements[0].left.object.name} but expecting o1."
         success = false
-    elsif systemI1Statements[0].right.left.object.name != :i0 then
-        puts "Error: invalid first statement right left, got #{systemI1Statements[0].right.left.object.name} but expecting i0."
+    elsif systemI1Statements[0].yes.last_statement.right.operator != :* then
+        puts "Error: invalid content of first if statement right operator, got #{systemI1Statements[0].right.operator} but expecting *."
         success = false
-    elsif systemI1Statements[0].right.right.object.name != :i1 then
-        puts "Error: invalid first statement right right, got #{systemI1Statements[0].right.left.object.name} but expecting i1."
+    elsif systemI1Statements[0].yes.last_statement.right.left.object.name != :i0 then
+        puts "Error: invalid content of first first if statement right left, got #{systemI1Statements[0].right.left.object.name} but expecting i0."
+        success = false
+    elsif systemI1Statements[0].yes.last_statement.right.right.object.name != :i1 then
+        puts "Error: invalid content of first if statement right right, got #{systemI1Statements[0].right.left.object.name} but expecting i1."
         success = false
     elsif !systemI1Statements[2].is_a?(If) then
         puts "Error: invalid third statement, got #{systemI1Statements[2].class} but expecting If."

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.2.3"
+  VERSION = "2.2.5"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.2.3
+  version: 2.2.5
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-03-10 00:00:00.000000000 Z
+date: 2020-03-11 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler