HDLRuby 2.2.2 → 2.2.3

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: ce1d3b652bf8a3590f023acab0e74ec08d6062df5ccbc38fb1e1cbeb2cd41028
4
- data.tar.gz: 52461928e01080214a4fb6ce0f1f852c6403d26bfd152579755e6b2990c396d2
3
+ metadata.gz: 7c97f2a40be4ad9b440b2a76fbb993c28c8a1ff3ca6d33b3fb6ea134361489ca
4
+ data.tar.gz: 5a7909585987b60e481ac58f14d631bf1bfe60c538233a1709751bd5cf23faa9
5
5
  SHA512:
6
- metadata.gz: 193afd5d38ef5159a89630f9f44be2e43c95925f9d6f0d037616e26fb9dc5538fce721be53ebfc7c08ce303e6937f7eddf6bf6493cb741c485ec878c538c28a6
7
- data.tar.gz: d666fca088c1c737f81cccbbc58982e194ee0cff2fcd801e2ac9f13d504de04f3be4f3dae66dd6408af1c9d079b3f9c7dad0334c08bd77ad20daaae513058f92
6
+ metadata.gz: '0958174494199a7c5b65e5ac5d6e2657969310615b4dd078ac31f52e144228d6450a9bcb437fa54d5c8403e34244a09fb8e4226ed3972b35df677f15748b3287'
7
+ data.tar.gz: 156e11a28ab129b92f27ce205fb5cde89109b70120233da58fb14753cc893af842729eb970713aa5131bb8935f157c37bc67b0ff6c1d3add7c4fd2a389a7f458
@@ -2041,8 +2041,17 @@ module HDLRuby::High
2041
2041
  #
2042
2042
  # NOTE: the else part is defined through the helse method.
2043
2043
  def hif(condition)
2044
+ # # Creates the if statement.
2045
+ # return If.new(condition) { self }
2046
+ # Remove self from the current block.
2047
+ obj = self
2048
+ High.cur_block.delete_statement!(obj)
2044
2049
  # Creates the if statement.
2045
- return If.new(condition) { self }
2050
+ stmnt = If.new(condition) { add_statement(obj) }
2051
+ # Add it to the current block.
2052
+ High.cur_block.add_statement(stmnt)
2053
+ # Returns the result.
2054
+ return stmnt
2046
2055
  end
2047
2056
  end
2048
2057
 
@@ -1108,7 +1108,7 @@ module HDLRuby::Low
1108
1108
  return '"' + self.content.to_s.rjust(width,sign).upcase + '"'
1109
1109
  else
1110
1110
  sign = self.type.signed? ? (self.content>=0 ? "0" : "1") : "0"
1111
- return '"' + self.content.to_s(2).rjust(width,sign).upcase + '"'
1111
+ return '"' + self.content.abs.to_s(2).rjust(width,sign).upcase + '"'
1112
1112
  end
1113
1113
  end
1114
1114
  end
@@ -189,5 +189,16 @@ module HDLRuby::Low
189
189
  end
190
190
  end
191
191
 
192
+ ## Extends the TimeBlock class with functionality for breaking assingments
193
+ # to concats.
194
+ class TimeBlock
195
+
196
+ # Removes the signals and corresponding assignments whose name is not
197
+ # in +keep+.
198
+ def delete_unless!(keep)
199
+ # Nothing to cleanup.
200
+ end
201
+ end
202
+
192
203
 
193
204
  end
@@ -86,13 +86,13 @@ module HDLRuby::High::Std
86
86
 
87
87
  # Creates a new channel reader running in +namespace+ and
88
88
  # reading using +reader_proc+ and reseting using +reseter_proc+.
89
- def initialize(namespace,reader_proc,reseter_proc)
89
+ def initialize(namespace,reader_proc,reseter_proc = nil)
90
90
  unless namespace.is_a?(Namespace)
91
91
  raise "Invalid class for a namespace: #{namespace.class}"
92
92
  end
93
93
  @namespace = namespace
94
94
  @reader_proc = reader_proc.to_proc
95
- @rester_proc = reseter_proc.to_proc
95
+ @rester_proc = reseter_proc ? reseter_proc.to_proc : proc {}
96
96
  end
97
97
 
98
98
  ## Performs a read on the channel using +args+ and +ruby_block+
@@ -129,13 +129,13 @@ module HDLRuby::High::Std
129
129
 
130
130
  # Creates a new channel writer running in +namespace+ and
131
131
  # writing using +writer_proc+ and reseting using +reseter_proc+.
132
- def initialize(namespace,writer_proc,reseter_proc)
132
+ def initialize(namespace,writer_proc,reseter_proc = nil)
133
133
  unless namespace.is_a?(Namespace)
134
134
  raise "Invalid class for a namespace: #{namespace.class}"
135
135
  end
136
136
  @namespace = namespace
137
137
  @writer_proc = writer_proc.to_proc
138
- @reseter_proc = reseter_proc.to_proc
138
+ @reseter_proc = reseter_proc ? reseter_proc.to_proc : proc {}
139
139
  end
140
140
 
141
141
  ## Performs a write on the channel using +args+ and +ruby_block+
@@ -174,14 +174,17 @@ module HDLRuby::High::Std
174
174
  # Creates a new channel accesser running in +namespace+
175
175
  # and reading using +reader_proc+, writing using +writer_proc+,
176
176
  # and reseting using +reseter_proc+.
177
- def initialize(namespace,reader_proc,writer_proc,reseter_proc)
177
+ def initialize(namespace,reader_proc,writer_proc,reseter_proc = nil)
178
178
  unless namespace.is_a?(Namespace)
179
179
  raise "Invalid class for a namespace: #{namespace.class}"
180
180
  end
181
181
  @namespace = namespace
182
- @reader_proc = reader_proc.to_proc
183
- @writer_proc = writer_proc.to_proc
184
- @reseter_proc = reseter_proc.to_proc
182
+ unless reader_proc || writer_proc then
183
+ raise "An accesser must have at least a reading or a writing procedure."
184
+ end
185
+ @reader_proc = reader_proc ? reader_proc.to_proc : proc { }
186
+ @writer_proc = writer_proc ? writer_proc.to_proc : proc { }
187
+ @reseter_proc = reseter_proc ? reseter_proc.to_proc : proc {}
185
188
  end
186
189
 
187
190
  ## Performs a read on the channel using +args+ and +ruby_block+
@@ -276,10 +279,10 @@ module HDLRuby::High::Std
276
279
  # The accesser inout ports by name.
277
280
  @accesser_inouts = {}
278
281
 
279
- # The default reset procedures (reseters), by default do nothing.
280
- @input_reseter_proc = proc {}
281
- @output_reseter_proc = proc {}
282
- @inout_reseter_proc = proc {}
282
+ # # The default reset procedures (reseters), by default do nothing.
283
+ # @input_reseter_proc = proc {}
284
+ # @output_reseter_proc = proc {}
285
+ # @inout_reseter_proc = proc {}
283
286
 
284
287
  # The branch channels
285
288
  @branches = {}
@@ -748,17 +751,17 @@ module HDLRuby::High::Std
748
751
  end
749
752
 
750
753
  # Set ups the accesser's namespace
751
- @accesser_inputs.each do |name,sig|
754
+ loc_inputs.each do |name,sig|
752
755
  @accesser_namespace.add_method(sig.name) do
753
756
  HDLRuby::High.top_user.send(name)
754
757
  end
755
758
  end
756
- @accesser_outputs.each do |name,sig|
759
+ loc_outputs.each do |name,sig|
757
760
  @accesser_namespace.add_method(sig.name) do
758
761
  HDLRuby::High.top_user.send(name)
759
762
  end
760
763
  end
761
- @accesser_inouts.each do |name,sig|
764
+ loc_inouts.each do |name,sig|
762
765
  @accesser_namespace.add_method(sig.name) do
763
766
  HDLRuby::High.top_user.send(name)
764
767
  end
@@ -277,7 +277,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
277
277
  hif(trig_r == 1) do
278
278
  # The trigger was previously set, read ok.
279
279
  target <= dbus_r
280
- blk.call
280
+ blk.call if blk
281
281
  end
282
282
  # Prepare the read.
283
283
  abus_r <= addr
@@ -311,7 +311,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
311
311
  # No reset, so can perform the write.
312
312
  hif(trig_w == 1) do
313
313
  # The trigger was previously set, write ok.
314
- blk.call
314
+ blk.call if blk
315
315
  end
316
316
  # Prepare the write.
317
317
  abus_w <= addr
@@ -322,6 +322,84 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
322
322
  end
323
323
  end
324
324
 
325
+
326
+ # The increment branches.
327
+ # Read with increment
328
+ brancher(:rinc) do
329
+ reader_output :trig_r, :abus_r
330
+ reader_input :dbus_r
331
+ if br_rsts[:rinc] then
332
+ rst_name = br_rsts[:rinc].to_sym
333
+ else
334
+ rst_name = rst.name
335
+ reader_input rst_name
336
+ end
337
+
338
+ # Defines the read procedure at address +addr+
339
+ # using +target+ as target of access result.
340
+ reader do |blk,target|
341
+ # By default the read trigger is 0.
342
+ top_block.unshift { trig_r <= 0 }
343
+ # The read procedure.
344
+ rst = send(rst_name)
345
+ par do
346
+ hif(rst == 0) do
347
+ # No reset, so can perform the read.
348
+ hif(trig_r == 1) do
349
+ # The trigger was previously set, read ok.
350
+ target <= dbus_r
351
+ blk.call if blk
352
+ end
353
+ # Prepare the read.
354
+ abus_r <= abus_r + 1
355
+ trig_r <= 1
356
+ end
357
+ helse do
358
+ # Initialize the address to -1
359
+ abus_r <= -1
360
+ end
361
+ end
362
+ end
363
+ end
364
+
365
+ # Write with address
366
+ brancher(:winc) do
367
+ writer_output :trig_w, :abus_w, :dbus_w
368
+ if br_rsts[:winc] then
369
+ rst_name = br_rsts[:winc].to_sym
370
+ else
371
+ rst_name = rst.name
372
+ writer_input rst_name
373
+ end
374
+ # puts "br_rsts=#{br_rsts}"
375
+ # puts "rst_name=#{rst_name}"
376
+
377
+ # Defines the read procedure at address +addr+
378
+ # using +target+ as target of access result.
379
+ writer do |blk,target|
380
+ # By default the read trigger is 0.
381
+ top_block.unshift { trig_w <= 0 }
382
+ # The write procedure.
383
+ rst = send(rst_name)
384
+ par do
385
+ hif(rst == 0) do
386
+ # No reset, so can perform the write.
387
+ hif(trig_w == 1) do
388
+ # The trigger was previously set, write ok.
389
+ blk.call if blk
390
+ end
391
+ # Prepare the write.
392
+ abus_w <= abus_w + 1
393
+ trig_w <= 1
394
+ dbus_w <= target
395
+ end
396
+ helse do
397
+ abus_w <= -1
398
+ end
399
+ end
400
+ end
401
+ end
402
+
325
403
  end
326
404
 
327
405
 
@@ -1,3 +1,3 @@
1
1
  module HDLRuby
2
- VERSION = "2.2.2"
2
+ VERSION = "2.2.3"
3
3
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: HDLRuby
3
3
  version: !ruby/object:Gem::Version
4
- version: 2.2.2
4
+ version: 2.2.3
5
5
  platform: ruby
6
6
  authors:
7
7
  - Lovic Gauthier
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2020-03-09 00:00:00.000000000 Z
11
+ date: 2020-03-10 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler