HDLRuby 2.2.16 → 2.3.3

data/lib/HDLRuby/hdr_samples/with_loop.rb

@@ -0,0 +1,69 @@
+require 'std/loop.rb'
+
+include HDLRuby::High::Std
+
+system :with_loop do
+
+    # The clock and reset
+    inner :clk, :rst
+    # The running signals.
+    inner :doit0, :doit1
+    # The signal to check for finishing.
+    inner :over
+
+    # A counter.
+    [8].inner :count, :count2
+
+    # The first loop: basic while.
+    lp0 = while_loop(clk, proc{count<=0}, count<15) { count <= count + 1 }
+
+    # The second loop: 10 times.
+    lp1 = times_loop(clk,10) { count2 <= count2+2 }
+    # Control it using doit1 as req and over as ack.
+    rst_req_ack(clk.posedge,rst,doit1,over,lp1)
+
+    par(clk.posedge) do
+        doit1 <= 0
+        hif(rst) do
+            lp0.reset()
+            # lp1.reset()
+            # doit1 <= 0
+            count2 <= 0
+            over <= 0
+        end
+        helse do
+            hif(doit0) { lp0.run }
+            lp0.finish { doit0 <= 0; doit1 <= 1 }# ; lp1.run }
+            hif(doit1) { lp1.run; lp0.reset() }
+            # lp1.finish { over <= 1; doit1 <= 0 }
+            # Second pass for first loop.
+            hif(over)  { lp0.run }
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        doit0 <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        doit0 <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        64.times do
+            clk <= 0
+            !10.ns
+            clk <= 1
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_memory.rb

@@ -108,16 +108,26 @@ system :mem_test do
     end
 
 
-    [8].inner :sum
+    [8].inner :sum0, :sum1
 
     # Declares a dual edge 8-bit data and address memory.
     mem_dual([8],256,clk,rst, raddr: :rst,waddr: :rst).(:memDI)
 
     # Instantiate the producer to access port waddr of the memory.
-    producer(memDI.branch(:waddr)).(:producerI).(clk,rst)
+    producer(memDI.branch(:waddr)).(:producerI0).(clk,rst)
 
     # Instantiate the producer to access port raddr of the memory.
-    consumer(memDI.branch(:raddr)).(:consumerI).(clk,rst,sum)
+    consumer(memDI.branch(:raddr)).(:consumerI0).(clk,rst,sum0)
+
+
+    # Declares a 4-bank 8-bit data and address memory.
+    mem_bank([8],4,256/4,clk,rst, raddr: :rst, waddr: :rst).(:memBI)
+
+    # Instantiate the producer to access port waddr of the memory.
+    producer(memBI.branch(:waddr)).(:producerI1).(clk,rst)
+
+    # Instantiate the producer to access port raddr of the memory.
+    consumer(memBI.branch(:raddr)).(:consumerI1).(clk,rst,sum1)
 
 
 end

data/lib/HDLRuby/hdrcc.rb

@@ -113,12 +113,9 @@ module HDLRuby
                 return
             end
             # Get its required files.
-            requires = @checks[-1].get_all_requires
+            requires = @checks[-1].get_all_requires +
+                       @checks[-1].get_all_require_relatives
             requires.each do |file|
-                # if file != "HDLRuby" &&
-                #         !@std_files.find { |std| std.include?(file) } then
-                #     read_all(file)
-                # end
                 read_all(file)
             end
             @requires += requires
@@ -244,7 +241,7 @@ include HDLRuby
 # Process the command line options
 $options = {}
 $optparse = OptionParser.new do |opts|
-    opts.banner = "Usage: hdrcc.rb [options] <input file> [<output file>]"
+    opts.banner = "Usage: hdrcc.rb [options] <input file> [<output directory or file>]"
 
     opts.separator ""
     opts.separator "Where:"
@@ -326,18 +323,17 @@ $optparse = OptionParser.new do |opts|
     opts.separator ""
     opts.separator "Notice:"
     opts.separator "* If no output option is given, simply checks the input file"
-    opts.separator "* If no output file is given, the result is given through the standard output."
     opts.separator "* If no top system is given, it will be automatically searched in the input file."
     opts.separator ""
     opts.separator "Examples:"
     opts.separator "* Compile system named `adder` from `adder.rb` input file and generate `adder.yaml` low-level YAML description:"
     opts.separator "   hdrcc.rb --yaml --top adder adder.rb adder.yaml"
-    opts.separator "* Compile `adder.rb` input file and generate `adder.vhd` low-level VHDL description:"
-    opts.separator "   hdrcc.rb --vhdl adder.rb adder.vhd"
+    opts.separator "* Compile `adder.rb` input file and generate low-level VHDL description files in `adder_vhd` directory:"
+    opts.separator "   hdrcc.rb --vhdl adder.rb adder_vhd"
     opts.separator "* Check the validity of `adder.rb` input file:"
     opts.separator "   hdrcc.rb adder.rb"
-    opts.separator "* Compile system `adder` whose bit width is generic from `adder_gen.rb` input file to a 16-bit circuit whose low-level Verilog HDL description is dumped to the standard output:"
-    opts.separator "   hdrcc -v -t adder --param 16 adder_gen.rb"
+    opts.separator "* Compile system `adder` whose bit width is generic from `adder_gen.rb` input file to a 16-bit circuit whose low-level Verilog HDL description files are put in `adder_gen_v` directory:"
+    opts.separator "   hdrcc -v -t adder --param 16 adder_gen.rb adder_gen_v"
     opts.separator "* Compile system `multer` with inputs and output bit width is generic from `multer_gen.rb` input file to a 16x16->32 bit cicruit whose low-level YAML description is saved to output file `multer_gen.yaml`"
     opts.separator "hdrcc -y -t multer -p 16,16,32 multer_gen.rb multer_gen.yaml"
 
@@ -563,7 +559,7 @@ elsif $options[:clang] then
         end
         Dir.chdir($output)
         # Kernel.system("make -s")
-        Kernel.system("cc -o3 -o hruby_simulator *.c")
+        Kernel.system("cc -o3 -o hruby_simulator *.c -lpthread")
         Kernel.system("./hruby_simulator")
     end
 elsif $options[:verilog] then

data/lib/HDLRuby/hruby_check.rb

@@ -45,11 +45,20 @@ module HDLRuby
                    (code[1][1] == "require")
         end
 
+        # Tells if +code+ is require_relative description.
+        def is_require_relative?(code)
+            # return code[0] && (code[0][0] == :command) &&
+            #        (code[0][1][1] == "require_relative")
+            return code && (code[0] == :command) &&
+                   (code[1][1] == "require_relative")
+        end
+
         # Gets the required file from +code+.
         def get_require(code)
             # return (code[0][2][1][0][1][1][1])
             return (code[2][1][0][1][1][1])
         end
+        alias_method :get_require_relative, :get_require
 
         # Gets all the required files of  +code+.
         def get_all_requires(code = @code)
@@ -66,6 +75,21 @@ module HDLRuby
             end
         end
 
+        # Gets all the require_relative files of  +code+.
+        def get_all_require_relatives(code = @code)
+            if code.is_a?(Array) then
+                require_relatives = (code.select { |sub| is_require_relative?(sub) }).map! do |sub|
+                    get_require_relative(sub)
+                end
+                code.each do |sub|
+                    require_relatives += get_all_require_relatives(sub)
+                end
+                return require_relatives
+            else
+                return []
+            end
+        end
+
         # Tells if +code+ is a system description.
         def is_system?(code)
             return code.is_a?(Array) && (code[0] == :command) &&
@@ -77,7 +101,7 @@ module HDLRuby
             return code[2][1][0][1][1][1]
         end
 
-        # Gets all the required files of  +code+.
+        # Gets all the systems of  +code+.
         def get_all_systems(code = @code)
             return [] unless code.is_a?(Array)
             return code.reduce([]) {|ar,sub| ar + get_all_systems(sub) } +

data/lib/HDLRuby/hruby_high.rb

@@ -1308,6 +1308,12 @@ module HDLRuby::High
             return true
         end
 
+        # Converts to a type.
+        # Returns self since it is already a type.
+        def to_type
+            return self
+        end
+
         # Sets the +name+.
         #
         # NOTE: can only be done if the name is not already set.

data/lib/HDLRuby/hruby_low.rb

@@ -1123,6 +1123,10 @@ module HDLRuby::Low
             return self.parent.is_a?(SystemT) ? self : self.parent.top_scope
         end
 
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
 
     end
 
@@ -1385,7 +1389,8 @@ module HDLRuby::Low
     # NOTE: type definition are actually type with a name refering to another
     #       type (and equivalent to it).
     class TypeDef < Type
-        extend Forwardable
+        # Moved to constructor
+        # extend Forwardable
 
         # The definition of the type.
         attr_reader :def
@@ -1402,6 +1407,19 @@ module HDLRuby::Low
             end
             # Set the referened type.
             @def = type
+
+            # Sets the delegations
+            self.extend Forwardable
+            [ :signed?, :unsigned?, :fixed?, :float?, :leaf?,
+              :width, :range?, :range, :base?, :base, :types?,
+              :get_all_types, :get_type, :each, :each_type, 
+              :regular?,
+              :each_name,
+              :equivalent? ].each do |meth|
+                  if @def.respond_to?(meth)
+                      self.def_delegator :@def, meth
+                  end
+              end
         end
 
         # Comparison for hash: structural comparison.
@@ -1429,14 +1447,15 @@ module HDLRuby::Low
             @def.each_type_deep(&ruby_block)
         end
 
-        # Delegate the type methods to the ref.
-        def_delegators :@def,
-                       :signed?, :unsigned?, :fixed?, :float?, :leaf?,
-                       :width, :range?, :range, :base?, :base, :types?,
-                       :get_all_types, :get_type, :each, :each_type, 
-                       :regular?,
-                       :each_name,
-                       :equivalent?
+        # Moved to constructor
+        # # Delegate the type methods to the ref.
+        # def_delegators :@def,
+        #                :signed?, :unsigned?, :fixed?, :float?, :leaf?,
+        #                :width, :range?, :range, :base?, :base, :types?,
+        #                :get_all_types, :get_type, :each, :each_type, 
+        #                :regular?,
+        #                :each_name,
+        #                :equivalent?
     end
 
 
@@ -2117,6 +2136,11 @@ module HDLRuby::Low
         def top_scope
             return parent.top_scope
         end
+
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
     end
 
 
@@ -2604,6 +2628,11 @@ module HDLRuby::Low
         def top_scope
             return self.scope.top_scope
         end
+
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
     end
 
 
@@ -3702,6 +3731,11 @@ module HDLRuby::Low
         def top_scope
             return self.parent.is_a?(Scope) ? self.parent : self.parent.top_scope
         end
+
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
     end
 
 

data/lib/HDLRuby/hruby_low2c.rb

@@ -546,9 +546,10 @@ module HDLRuby::Low
         #
         # NOTE: type tuples are converted to bit vector of their contents.
         def to_c(level = 0)
-            return "get_type_tuple(#{self.each.join(",") do |type|
-               type.to_c(level+1)
-            end})"
+            # return "get_type_tuple(#{self.each.to_a.join(",") do |type|
+            #    type.to_c(level+1)
+            # end})"
+            return self.to_vector.to_c(level)
         end
     end
 
@@ -1872,7 +1873,8 @@ module HDLRuby::Low
             res << "idx = value2integer(#{self.index.to_c(level+2)});\n"
             # Make the access.
             res << (" " * ((level+1)*3))
-            res << "dst = read_range(ref,idx,idx,#{self.ref.type.base.to_c(level)},dst);\n"
+            # res << "dst = read_range(ref,idx,idx,#{self.ref.type.base.to_c(level)},dst);\n"
+            res << "dst = read_range(ref,idx,idx,#{self.type.to_c(level)},dst);\n"
             # Restore the state of the value pool.
             res << (" " * ((level+1)*3))
             res << "set_value_pos(pool_state);\n"
@@ -1930,7 +1932,9 @@ module HDLRuby::Low
             res << "last = value2integer(#{self.range.last.to_c(level+2)});\n"
             # Make the access.
             res << (" " * ((level+1)*3))
-            res << "dst = #{command}_range(ref,first,last,#{self.ref.type.base.to_c(level)},dst);\n"
+            # res << "dst = #{command}_range(ref,first,last,#{self.ref.type.base.to_c(level)},dst);\n"
+            # puts "will read_range for #{self.ref.name} with width=#{self.ref.type.width} with base width=#{self.ref.type.base.width} with range=#{self.ref.type.range} with range=#{self.range.first.content}..#{self.range.last.content}"
+            res << "dst = #{command}_range(ref,first,last,#{self.type.base.to_c(level)},dst);\n"
             # Restore the state of the value pool.
             res << (" " * ((level+1)*3))
             res << "set_value_pos(pool_state);\n"

data/lib/HDLRuby/hruby_low2high.rb

@@ -566,7 +566,7 @@ module HDLRuby::Low
         # +level+ is the hierachical level of the object.
         def to_high(level = 0)
             return self.child.to_high(level) + 
-                ".cast(" + self.type.to_high(level) + ")"
+                ".as(" + self.type.to_high(level) + ")"
         end
     end
 

data/lib/HDLRuby/hruby_low2vhd.rb

@@ -345,31 +345,34 @@ module HDLRuby::Low
             res << " " * (level*3)
             res << "entity #{Low2VHDL.entity_name(self.name)} is\n"
             # The ports
-            res << " " * ((level+1)*3)
-            res << "port (\n"
-            # Inputs
-            self.each_input do |input|
-                res << " " * ((level+2)*3)
-                res << Low2VHDL.vhdl_name(input.name) << ": in " 
-                res << input.type.to_vhdl << ";\n"
-            end
-            # Outputs
-            self.each_output do |output|
-                res << " " * ((level+2)*3)
-                res << Low2VHDL.vhdl_name(output.name) << ": out " 
-                res << output.type.to_vhdl << ";\n"
-            end
-            # Inouts
-            self.each_inout do |inout|
-                res << " " * ((level+2)*3)
-                res << Low2VHDL.vhdl_name(inout.name) << ": inout " 
-                res << inout.type.to_vhdl << ";\n"
+            if self.each_input.any? || self.each_output.any? ||
+                   self.each_inout.any? then
+                res << " " * ((level+1)*3)
+                res << "port (\n"
+                # Inputs
+                self.each_input do |input|
+                    res << " " * ((level+2)*3)
+                    res << Low2VHDL.vhdl_name(input.name) << ": in " 
+                    res << input.type.to_vhdl << ";\n"
+                end
+                # Outputs
+                self.each_output do |output|
+                    res << " " * ((level+2)*3)
+                    res << Low2VHDL.vhdl_name(output.name) << ": out " 
+                    res << output.type.to_vhdl << ";\n"
+                end
+                # Inouts
+                self.each_inout do |inout|
+                    res << " " * ((level+2)*3)
+                    res << Low2VHDL.vhdl_name(inout.name) << ": inout " 
+                    res << inout.type.to_vhdl << ";\n"
+                end
+                # Remove the last ";" for conforming with VHDL syntax.
+                res[-2..-1] = "\n" if res[-2] == ";"
+                res << " " * ((level+1)*3)
+                # Close the port declaration.
+                res << ");\n"
             end
-            # Remove the last ";" for conforming with VHDL syntax.
-            res[-2..-1] = "\n" if res[-2] == ";"
-            res << " " * ((level+1)*3)
-            # Close the port declaration.
-            res << ");\n"
             # Close the entity
             res << " " * (level*3)
             res << "end #{Low2VHDL.entity_name(self.name)};\n\n"
@@ -617,7 +620,17 @@ module HDLRuby::Low
             # # Simply generates the redefined type.
             # return self.def.to_vhdl(level)
             # Simply use the name of the type.
-            return Low2VHDL.vhdl_name(self.name)
+            # Is it a composite type?
+            if (self.def.is_a?(TypeStruct) ||
+              (self.def.is_a?(TypeVector) && 
+                    (self.def.base.is_a?(TypeVector) || 
+                     self.def.base.is_a?(TypeStruct))))
+                # Yes, generate a VHDL type definition.
+                return Low2VHDL.vhdl_name(self.name)
+            else
+                # No, generates the defined type.
+                return self.def.to_vhdl(level)
+            end
         end
     end
 
@@ -745,29 +758,31 @@ module HDLRuby::Low
                 res << Low2VHDL.vhdl_name(self.block.name) << ": "
             end
             res << "process "
-            # Generate the senitivity list.
-            if self.each_event.any? then
-                # If there is a clock.
-                res << "("
-                res << self.each_event.map do |event|
-                    event.ref.to_vhdl(level)
-                end.join(", ")
-                res << ")"
-            else
-                # If no clock, generate the sensitivity list from the right
-                # values.
-                list = self.block.each_node_deep.select do |node|
-                    node.is_a?(RefName) && !node.leftvalue? && 
-                        !node.parent.is_a?(RefName) &&
-                        # Also skip the variables
-                        !vars.find {|var| var.name == node.name }
-                end.to_a
-                # Keep only one ref per signal.
-                list.uniq! { |node| node.name }
-                # Generate the sensitivity list from it.
-                res << "("
-                res << list.map {|node| node.to_vhdl(level) }.join(", ")
-                res << ")"
+            # Generate the senitivity list if not a timed block.
+            unless self.block.is_a?(TimeBlock) then
+                if self.each_event.any? then
+                    # If there is a clock.
+                    res << "("
+                    res << self.each_event.map do |event|
+                        event.ref.to_vhdl(level)
+                    end.join(", ")
+                    res << ")"
+                else
+                    # If no clock, generate the sensitivity list from the right
+                    # values.
+                    list = self.block.each_node_deep.select do |node|
+                        node.is_a?(RefName) && !node.leftvalue? && 
+                            !node.parent.is_a?(RefName) &&
+                            # Also skip the variables
+                            !vars.find {|var| var.name == node.name }
+                    end.to_a
+                    # Keep only one ref per signal.
+                    list.uniq! { |node| node.name }
+                    # Generate the sensitivity list from it.
+                    res << "("
+                    res << list.map {|node| node.to_vhdl(level) }.join(", ")
+                    res << ")"
+                end
             end
             res << "\n"
             # Generate the variables.