HDLRuby 2.2.16 → 2.3.3
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.md +33 -21
- data/lib/HDLRuby/hdr_samples/rom.rb +2 -2
- data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +96 -0
- data/lib/HDLRuby/hdr_samples/with_channel.rb +49 -8
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +3 -2
- data/lib/HDLRuby/hdr_samples/with_linear.rb +48 -25
- data/lib/HDLRuby/hdr_samples/with_loop.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_memory.rb +13 -3
- data/lib/HDLRuby/hdrcc.rb +8 -12
- data/lib/HDLRuby/hruby_check.rb +25 -1
- data/lib/HDLRuby/hruby_high.rb +6 -0
- data/lib/HDLRuby/hruby_low.rb +43 -9
- data/lib/HDLRuby/hruby_low2c.rb +9 -5
- data/lib/HDLRuby/hruby_low2high.rb +1 -1
- data/lib/HDLRuby/hruby_low2vhd.rb +63 -48
- data/lib/HDLRuby/hruby_low_fix_types.rb +6 -2
- data/lib/HDLRuby/hruby_low_resolve.rb +5 -3
- data/lib/HDLRuby/hruby_low_without_concat.rb +8 -4
- data/lib/HDLRuby/hruby_types.rb +82 -72
- data/lib/HDLRuby/hruby_verilog.rb +9 -1
- data/lib/HDLRuby/sim/hruby_sim.h +7 -0
- data/lib/HDLRuby/sim/hruby_sim_calc.c +83 -6
- data/lib/HDLRuby/sim/hruby_sim_core.c +2 -0
- data/lib/HDLRuby/std/channel.rb +336 -158
- data/lib/HDLRuby/std/fixpoint.rb +50 -39
- data/lib/HDLRuby/std/linear.rb +68 -0
- data/lib/HDLRuby/std/loop.rb +101 -0
- data/lib/HDLRuby/std/memory.rb +1002 -32
- data/lib/HDLRuby/std/task.rb +850 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +6 -2
@@ -0,0 +1,69 @@
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require 'std/loop.rb'
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include HDLRuby::High::Std
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system :with_loop do
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# The clock and reset
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inner :clk, :rst
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# The running signals.
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inner :doit0, :doit1
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# The signal to check for finishing.
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inner :over
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# A counter.
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[8].inner :count, :count2
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# The first loop: basic while.
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lp0 = while_loop(clk, proc{count<=0}, count<15) { count <= count + 1 }
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# The second loop: 10 times.
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lp1 = times_loop(clk,10) { count2 <= count2+2 }
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# Control it using doit1 as req and over as ack.
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rst_req_ack(clk.posedge,rst,doit1,over,lp1)
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par(clk.posedge) do
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doit1 <= 0
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hif(rst) do
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lp0.reset()
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# lp1.reset()
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# doit1 <= 0
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count2 <= 0
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over <= 0
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end
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helse do
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hif(doit0) { lp0.run }
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lp0.finish { doit0 <= 0; doit1 <= 1 }# ; lp1.run }
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hif(doit1) { lp1.run; lp0.reset() }
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# lp1.finish { over <= 1; doit1 <= 0 }
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# Second pass for first loop.
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hif(over) { lp0.run }
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end
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end
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timed do
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clk <= 0
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rst <= 0
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doit0 <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 1
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 0
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doit0 <= 1
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!10.ns
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clk <= 1
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!10.ns
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64.times do
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clk <= 0
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!10.ns
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clk <= 1
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!10.ns
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end
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end
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end
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@@ -108,16 +108,26 @@ system :mem_test do
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end
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[8].inner :
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[8].inner :sum0, :sum1
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# Declares a dual edge 8-bit data and address memory.
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mem_dual([8],256,clk,rst, raddr: :rst,waddr: :rst).(:memDI)
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# Instantiate the producer to access port waddr of the memory.
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-
producer(memDI.branch(:waddr)).(:
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producer(memDI.branch(:waddr)).(:producerI0).(clk,rst)
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# Instantiate the producer to access port raddr of the memory.
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consumer(memDI.branch(:raddr)).(:
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consumer(memDI.branch(:raddr)).(:consumerI0).(clk,rst,sum0)
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# Declares a 4-bank 8-bit data and address memory.
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mem_bank([8],4,256/4,clk,rst, raddr: :rst, waddr: :rst).(:memBI)
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# Instantiate the producer to access port waddr of the memory.
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producer(memBI.branch(:waddr)).(:producerI1).(clk,rst)
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# Instantiate the producer to access port raddr of the memory.
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consumer(memBI.branch(:raddr)).(:consumerI1).(clk,rst,sum1)
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end
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data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -113,12 +113,9 @@ module HDLRuby
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return
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end
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# Get its required files.
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-
requires = @checks[-1].get_all_requires
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requires = @checks[-1].get_all_requires +
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@checks[-1].get_all_require_relatives
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requires.each do |file|
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# if file != "HDLRuby" &&
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# !@std_files.find { |std| std.include?(file) } then
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# read_all(file)
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-
# end
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read_all(file)
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end
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@requires += requires
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@@ -244,7 +241,7 @@ include HDLRuby
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# Process the command line options
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$options = {}
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$optparse = OptionParser.new do |opts|
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opts.banner = "Usage: hdrcc.rb [options] <input file> [<output file>]"
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opts.banner = "Usage: hdrcc.rb [options] <input file> [<output directory or file>]"
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opts.separator ""
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opts.separator "Where:"
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@@ -326,18 +323,17 @@ $optparse = OptionParser.new do |opts|
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opts.separator ""
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opts.separator "Notice:"
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opts.separator "* If no output option is given, simply checks the input file"
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opts.separator "* If no output file is given, the result is given through the standard output."
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opts.separator "* If no top system is given, it will be automatically searched in the input file."
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opts.separator ""
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opts.separator "Examples:"
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opts.separator "* Compile system named `adder` from `adder.rb` input file and generate `adder.yaml` low-level YAML description:"
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opts.separator " hdrcc.rb --yaml --top adder adder.rb adder.yaml"
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opts.separator "* Compile `adder.rb` input file and generate
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opts.separator " hdrcc.rb --vhdl adder.rb
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opts.separator "* Compile `adder.rb` input file and generate low-level VHDL description files in `adder_vhd` directory:"
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opts.separator " hdrcc.rb --vhdl adder.rb adder_vhd"
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opts.separator "* Check the validity of `adder.rb` input file:"
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opts.separator " hdrcc.rb adder.rb"
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opts.separator "* Compile system `adder` whose bit width is generic from `adder_gen.rb` input file to a 16-bit circuit whose low-level Verilog HDL description
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opts.separator " hdrcc -v -t adder --param 16 adder_gen.rb"
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opts.separator "* Compile system `adder` whose bit width is generic from `adder_gen.rb` input file to a 16-bit circuit whose low-level Verilog HDL description files are put in `adder_gen_v` directory:"
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opts.separator " hdrcc -v -t adder --param 16 adder_gen.rb adder_gen_v"
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opts.separator "* Compile system `multer` with inputs and output bit width is generic from `multer_gen.rb` input file to a 16x16->32 bit cicruit whose low-level YAML description is saved to output file `multer_gen.yaml`"
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opts.separator "hdrcc -y -t multer -p 16,16,32 multer_gen.rb multer_gen.yaml"
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@@ -563,7 +559,7 @@ elsif $options[:clang] then
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end
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Dir.chdir($output)
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# Kernel.system("make -s")
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Kernel.system("cc -o3 -o hruby_simulator *.c")
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Kernel.system("cc -o3 -o hruby_simulator *.c -lpthread")
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Kernel.system("./hruby_simulator")
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end
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elsif $options[:verilog] then
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data/lib/HDLRuby/hruby_check.rb
CHANGED
@@ -45,11 +45,20 @@ module HDLRuby
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(code[1][1] == "require")
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end
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# Tells if +code+ is require_relative description.
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def is_require_relative?(code)
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# return code[0] && (code[0][0] == :command) &&
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# (code[0][1][1] == "require_relative")
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return code && (code[0] == :command) &&
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(code[1][1] == "require_relative")
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end
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# Gets the required file from +code+.
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def get_require(code)
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# return (code[0][2][1][0][1][1][1])
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return (code[2][1][0][1][1][1])
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end
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alias_method :get_require_relative, :get_require
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# Gets all the required files of +code+.
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def get_all_requires(code = @code)
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end
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end
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# Gets all the require_relative files of +code+.
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def get_all_require_relatives(code = @code)
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if code.is_a?(Array) then
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require_relatives = (code.select { |sub| is_require_relative?(sub) }).map! do |sub|
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get_require_relative(sub)
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end
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code.each do |sub|
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require_relatives += get_all_require_relatives(sub)
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end
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return require_relatives
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else
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return []
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end
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end
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# Tells if +code+ is a system description.
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def is_system?(code)
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return code.is_a?(Array) && (code[0] == :command) &&
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return code[2][1][0][1][1][1]
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end
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# Gets all the
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# Gets all the systems of +code+.
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def get_all_systems(code = @code)
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return [] unless code.is_a?(Array)
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return code.reduce([]) {|ar,sub| ar + get_all_systems(sub) } +
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data/lib/HDLRuby/hruby_high.rb
CHANGED
@@ -1308,6 +1308,12 @@ module HDLRuby::High
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return true
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end
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# Converts to a type.
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# Returns self since it is already a type.
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def to_type
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return self
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end
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# Sets the +name+.
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#
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# NOTE: can only be done if the name is not already set.
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data/lib/HDLRuby/hruby_low.rb
CHANGED
@@ -1123,6 +1123,10 @@ module HDLRuby::Low
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return self.parent.is_a?(SystemT) ? self : self.parent.top_scope
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end
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# Gets the parent system, i.e., the parent of the top scope.
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def parent_system
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return self.top_scope.parent
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end
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end
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@@ -1385,7 +1389,8 @@ module HDLRuby::Low
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# NOTE: type definition are actually type with a name refering to another
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# type (and equivalent to it).
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class TypeDef < Type
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# Moved to constructor
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# extend Forwardable
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# The definition of the type.
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attr_reader :def
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end
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# Set the referened type.
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@def = type
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# Sets the delegations
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self.extend Forwardable
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[ :signed?, :unsigned?, :fixed?, :float?, :leaf?,
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:width, :range?, :range, :base?, :base, :types?,
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:get_all_types, :get_type, :each, :each_type,
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:regular?,
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:each_name,
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:equivalent? ].each do |meth|
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if @def.respond_to?(meth)
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self.def_delegator :@def, meth
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end
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end
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end
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# Comparison for hash: structural comparison.
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@def.each_type_deep(&ruby_block)
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end
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#
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# Moved to constructor
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# # Delegate the type methods to the ref.
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# def_delegators :@def,
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# :signed?, :unsigned?, :fixed?, :float?, :leaf?,
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# :width, :range?, :range, :base?, :base, :types?,
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# :get_all_types, :get_type, :each, :each_type,
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# :regular?,
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# :each_name,
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# :equivalent?
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end
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@@ -2117,6 +2136,11 @@ module HDLRuby::Low
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def top_scope
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return parent.top_scope
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end
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+
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# Gets the parent system, i.e., the parent of the top scope.
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def parent_system
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return self.top_scope.parent
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end
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end
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@@ -2604,6 +2628,11 @@ module HDLRuby::Low
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def top_scope
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return self.scope.top_scope
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end
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+
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# Gets the parent system, i.e., the parent of the top scope.
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def parent_system
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return self.top_scope.parent
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end
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end
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@@ -3702,6 +3731,11 @@ module HDLRuby::Low
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def top_scope
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return self.parent.is_a?(Scope) ? self.parent : self.parent.top_scope
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end
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+
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# Gets the parent system, i.e., the parent of the top scope.
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def parent_system
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return self.top_scope.parent
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end
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end
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data/lib/HDLRuby/hruby_low2c.rb
CHANGED
@@ -546,9 +546,10 @@ module HDLRuby::Low
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#
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547
547
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# NOTE: type tuples are converted to bit vector of their contents.
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548
548
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def to_c(level = 0)
|
549
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-
return "get_type_tuple(#{self.each.join(",") do |type|
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550
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-
|
551
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-
end})"
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# return "get_type_tuple(#{self.each.to_a.join(",") do |type|
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# type.to_c(level+1)
|
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# end})"
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|
+
return self.to_vector.to_c(level)
|
552
553
|
end
|
553
554
|
end
|
554
555
|
|
@@ -1872,7 +1873,8 @@ module HDLRuby::Low
|
|
1872
1873
|
res << "idx = value2integer(#{self.index.to_c(level+2)});\n"
|
1873
1874
|
# Make the access.
|
1874
1875
|
res << (" " * ((level+1)*3))
|
1875
|
-
res << "dst = read_range(ref,idx,idx,#{self.ref.type.base.to_c(level)},dst);\n"
|
1876
|
+
# res << "dst = read_range(ref,idx,idx,#{self.ref.type.base.to_c(level)},dst);\n"
|
1877
|
+
res << "dst = read_range(ref,idx,idx,#{self.type.to_c(level)},dst);\n"
|
1876
1878
|
# Restore the state of the value pool.
|
1877
1879
|
res << (" " * ((level+1)*3))
|
1878
1880
|
res << "set_value_pos(pool_state);\n"
|
@@ -1930,7 +1932,9 @@ module HDLRuby::Low
|
|
1930
1932
|
res << "last = value2integer(#{self.range.last.to_c(level+2)});\n"
|
1931
1933
|
# Make the access.
|
1932
1934
|
res << (" " * ((level+1)*3))
|
1933
|
-
res << "dst = #{command}_range(ref,first,last,#{self.ref.type.base.to_c(level)},dst);\n"
|
1935
|
+
# res << "dst = #{command}_range(ref,first,last,#{self.ref.type.base.to_c(level)},dst);\n"
|
1936
|
+
# puts "will read_range for #{self.ref.name} with width=#{self.ref.type.width} with base width=#{self.ref.type.base.width} with range=#{self.ref.type.range} with range=#{self.range.first.content}..#{self.range.last.content}"
|
1937
|
+
res << "dst = #{command}_range(ref,first,last,#{self.type.base.to_c(level)},dst);\n"
|
1934
1938
|
# Restore the state of the value pool.
|
1935
1939
|
res << (" " * ((level+1)*3))
|
1936
1940
|
res << "set_value_pos(pool_state);\n"
|
@@ -345,31 +345,34 @@ module HDLRuby::Low
|
|
345
345
|
res << " " * (level*3)
|
346
346
|
res << "entity #{Low2VHDL.entity_name(self.name)} is\n"
|
347
347
|
# The ports
|
348
|
-
|
349
|
-
|
350
|
-
|
351
|
-
|
352
|
-
|
353
|
-
|
354
|
-
|
355
|
-
|
356
|
-
|
357
|
-
|
358
|
-
|
359
|
-
|
360
|
-
|
361
|
-
|
362
|
-
|
363
|
-
|
364
|
-
|
365
|
-
|
366
|
-
|
348
|
+
if self.each_input.any? || self.each_output.any? ||
|
349
|
+
self.each_inout.any? then
|
350
|
+
res << " " * ((level+1)*3)
|
351
|
+
res << "port (\n"
|
352
|
+
# Inputs
|
353
|
+
self.each_input do |input|
|
354
|
+
res << " " * ((level+2)*3)
|
355
|
+
res << Low2VHDL.vhdl_name(input.name) << ": in "
|
356
|
+
res << input.type.to_vhdl << ";\n"
|
357
|
+
end
|
358
|
+
# Outputs
|
359
|
+
self.each_output do |output|
|
360
|
+
res << " " * ((level+2)*3)
|
361
|
+
res << Low2VHDL.vhdl_name(output.name) << ": out "
|
362
|
+
res << output.type.to_vhdl << ";\n"
|
363
|
+
end
|
364
|
+
# Inouts
|
365
|
+
self.each_inout do |inout|
|
366
|
+
res << " " * ((level+2)*3)
|
367
|
+
res << Low2VHDL.vhdl_name(inout.name) << ": inout "
|
368
|
+
res << inout.type.to_vhdl << ";\n"
|
369
|
+
end
|
370
|
+
# Remove the last ";" for conforming with VHDL syntax.
|
371
|
+
res[-2..-1] = "\n" if res[-2] == ";"
|
372
|
+
res << " " * ((level+1)*3)
|
373
|
+
# Close the port declaration.
|
374
|
+
res << ");\n"
|
367
375
|
end
|
368
|
-
# Remove the last ";" for conforming with VHDL syntax.
|
369
|
-
res[-2..-1] = "\n" if res[-2] == ";"
|
370
|
-
res << " " * ((level+1)*3)
|
371
|
-
# Close the port declaration.
|
372
|
-
res << ");\n"
|
373
376
|
# Close the entity
|
374
377
|
res << " " * (level*3)
|
375
378
|
res << "end #{Low2VHDL.entity_name(self.name)};\n\n"
|
@@ -617,7 +620,17 @@ module HDLRuby::Low
|
|
617
620
|
# # Simply generates the redefined type.
|
618
621
|
# return self.def.to_vhdl(level)
|
619
622
|
# Simply use the name of the type.
|
620
|
-
|
623
|
+
# Is it a composite type?
|
624
|
+
if (self.def.is_a?(TypeStruct) ||
|
625
|
+
(self.def.is_a?(TypeVector) &&
|
626
|
+
(self.def.base.is_a?(TypeVector) ||
|
627
|
+
self.def.base.is_a?(TypeStruct))))
|
628
|
+
# Yes, generate a VHDL type definition.
|
629
|
+
return Low2VHDL.vhdl_name(self.name)
|
630
|
+
else
|
631
|
+
# No, generates the defined type.
|
632
|
+
return self.def.to_vhdl(level)
|
633
|
+
end
|
621
634
|
end
|
622
635
|
end
|
623
636
|
|
@@ -745,29 +758,31 @@ module HDLRuby::Low
|
|
745
758
|
res << Low2VHDL.vhdl_name(self.block.name) << ": "
|
746
759
|
end
|
747
760
|
res << "process "
|
748
|
-
# Generate the senitivity list.
|
749
|
-
|
750
|
-
|
751
|
-
|
752
|
-
|
753
|
-
|
754
|
-
|
755
|
-
|
756
|
-
|
757
|
-
|
758
|
-
|
759
|
-
|
760
|
-
|
761
|
-
|
762
|
-
|
763
|
-
|
764
|
-
|
765
|
-
|
766
|
-
|
767
|
-
|
768
|
-
|
769
|
-
|
770
|
-
|
761
|
+
# Generate the senitivity list if not a timed block.
|
762
|
+
unless self.block.is_a?(TimeBlock) then
|
763
|
+
if self.each_event.any? then
|
764
|
+
# If there is a clock.
|
765
|
+
res << "("
|
766
|
+
res << self.each_event.map do |event|
|
767
|
+
event.ref.to_vhdl(level)
|
768
|
+
end.join(", ")
|
769
|
+
res << ")"
|
770
|
+
else
|
771
|
+
# If no clock, generate the sensitivity list from the right
|
772
|
+
# values.
|
773
|
+
list = self.block.each_node_deep.select do |node|
|
774
|
+
node.is_a?(RefName) && !node.leftvalue? &&
|
775
|
+
!node.parent.is_a?(RefName) &&
|
776
|
+
# Also skip the variables
|
777
|
+
!vars.find {|var| var.name == node.name }
|
778
|
+
end.to_a
|
779
|
+
# Keep only one ref per signal.
|
780
|
+
list.uniq! { |node| node.name }
|
781
|
+
# Generate the sensitivity list from it.
|
782
|
+
res << "("
|
783
|
+
res << list.map {|node| node.to_vhdl(level) }.join(", ")
|
784
|
+
res << ")"
|
785
|
+
end
|
771
786
|
end
|
772
787
|
res << "\n"
|
773
788
|
# Generate the variables.
|