HDLRuby 2.2.13 → 2.2.14

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 4c52cf9ff8c35896992dd4e79059490544c3d41047235a31660badec7a5773ed
-  data.tar.gz: 2ec8819e1dfa58be1e73ac35475de83973987627dc87b601820853c0926b8c3b
+  metadata.gz: a6a6e334b6e55bdc8f7947f92f4dd8a9de83fc0f90725bad5bfafedc27a8ca2e
+  data.tar.gz: a6f43c383176d02af9e8491c6b2425b5e1e8ca3c339464842dbf288fbe91dc26
 SHA512:
-  metadata.gz: '0782e49ba89bacc5316f5bd1ab232b70740f33f51d9381ec82cbbd06fc8eaf4042202dbc9723576405594246786d1b0d7c69187f1918116d3af5eea20abea245'
-  data.tar.gz: '000342564298bd2f46167c55f877deeab18e7b0c7282bce4e9a07b0485fde3fe3ea17beb5d0635d66c9ba47270ef3071dc222d58ced18e6f2d203adbe0d0dba1'
+  metadata.gz: 50a46ad334407428425912ec7b1fbd745d1de686e8792548524f23d4ca10f6252368b589f5fc77b201b07f1becf86aa7c234c77443b1014caad341c1fa0fa966
+  data.tar.gz: c8defb6937e32d43ddd0c56f49a2a608a8444a8ca0eef10f387fb1fc89597dc13871ce086223e8d1892799d1518d9a5cf915142e500cf4c74937bdfbfff68514

data/lib/HDLRuby/hdr_samples/memory_test.rb

@@ -0,0 +1,272 @@
+require 'std/memory.rb'
+
+include HDLRuby::High::Std
+
+
+# Sample code for testing the memory library.
+
+system :memory_test do
+    
+    # The test step counter.
+    [8].inner :step
+    # The success counter.
+    [4].inner :yay
+
+    # The clock and reset.
+    inner :clk, :rst
+
+    # The memory address.
+    [3].inner :address
+    # The value to write to memories.
+    [8].inner :value
+    # The general result register.
+    [8].inner :result
+    # The specific result registers.
+    [8].inner :res0, :res1, :res2, :res3, :res4, :res5, :res6, :res7
+
+    # Declares a one-ports synchronous memory.
+    mem_sync(1,[8],8,clk.negedge,rst,[:rst]).(:mem_sync_1I)
+    # And the corresponding access ports.
+    mem_sync_1I.branch(0).inner :mem_sync_1P
+
+    # Declares a dual-edge memory for address-based accesses.
+    mem_dual([8],8,clk,rst,raddr: :rst, waddr: :rst).(:mem_dual0I)
+    # And the corresponding access ports.
+    mem_dual0I.branch(:raddr).inner :mem_dual_raddrP
+    mem_dual0I.branch(:waddr).inner :mem_dual_waddrP
+
+    # Declares a second dual-edge memory for incremeted accesses.
+    mem_dual([8],8,clk,rst, rinc:  :rst, winc:  :rst).(:mem_dual1I)
+    # And the corresponding access ports.
+    mem_dual1I.branch(:rinc).inner :mem_dual_rincP
+    mem_dual1I.branch(:winc).inner :mem_dual_wincP
+
+    # Declares a thrid dual-edge memory for decremented accesses.
+    mem_dual([8],8,clk,rst, rdec:  :rst, wdec:  :rst).(:mem_dual2I)
+    # And the corresponding access ports.
+    mem_dual2I.branch(:rdec).inner :mem_dual_rdecP
+    mem_dual2I.branch(:wdec).inner :mem_dual_wdecP
+
+    # Declares a first register file for address-based accesses.
+    mem_file([8],8,clk,rst,raddr: :rst, waddr: :rst).(:mem_file0I)
+    # And the corresponding access ports.
+    mem_file0I.branch(:raddr).inner :mem_file_raddrP
+    mem_file0I.branch(:waddr).inner :mem_file_waddrP
+
+    # Declares a second register file for incremeted accesses.
+    mem_file([8],8,clk,rst, rinc:  :rst, winc:  :rst).(:mem_file1I)
+    # And the corresponding access ports.
+    mem_file1I.branch(:rinc).inner :mem_file_rincP
+    mem_file1I.branch(:winc).inner :mem_file_wincP
+
+    # Declares a third register file for decremeted accesses.
+    mem_file([8],8,clk,rst, rdec:  :rst, wdec:  :rst).(:mem_file2I)
+    # And the corresponding access ports.
+    mem_file2I.branch(:rdec).inner :mem_file_rdecP
+    mem_file2I.branch(:wdec).inner :mem_file_wdecP
+
+    # Declares a forth register file for num accesses.
+    mem_file([8],8,clk,rst, anum:  :rst).(:mem_file3I)
+    # And the corresponding access port.
+    mem_file3I.branch(:anum).inner :mem_file_anumP
+
+    # Declares a fifth register file for num accesses.
+    mem_file([8],8,clk,rst, anum:  :rst).(:mem_file4I)
+    # And the corresponding access port: individual accesses.
+    mem_file4I.branch(:anum).inner :mem_file_anum1P
+    mem_file_fixP = [ mem_file_anum1P.wrap(0), mem_file_anum1P.wrap(1),
+                      mem_file_anum1P.wrap(2), mem_file_anum1P.wrap(3),
+                      mem_file_anum1P.wrap(4), mem_file_anum1P.wrap(5),
+                      mem_file_anum1P.wrap(6), mem_file_anum1P.wrap(7) ]
+
+
+    # Tests the accesses to the memories.
+    par(clk.posedge) do
+        # Initial address and value.
+        hif(rst) { address <= 0; value <= 0 }
+
+        # Handles the memory accesses.
+        hcase(step)
+        # Write to mem_sync_1
+        hwhen(1) do
+            mem_sync_1P.write(address,value) do
+                yay <= yay + 1 
+                address <= address + 1
+                value <= value + 1
+            end
+        end
+        # Read from to mem_sync_1
+        hwhen(2) do
+            mem_sync_1P.read(address,result) do
+                yay <= yay + 1 
+                address <= address + 1
+            end
+        end
+        # Write to mem_dual0 with address
+        hwhen(3) do
+            mem_dual_waddrP.write(address,value) do
+                yay <= yay + 1 
+                address <= address + 1
+                value <= value + 1
+            end
+        end
+        # Read from mem_dual0 with address
+        hwhen(4) do
+            mem_dual_raddrP.read(address,result) do
+                yay <= yay + 1 
+                address <= address + 1
+            end
+        end
+        # Write to mem_dual1 with increment
+        hwhen(5) do
+            mem_dual_wincP.write(value) do
+                yay <= yay + 1 
+                value <= value + 1
+            end
+        end
+        # Read from mem_dual1 with increment
+        hwhen(6) do
+            mem_dual_rincP.read(result) do
+                yay <= yay + 1 
+            end
+        end
+        # Write to mem_dual2 with decrement
+        hwhen(7) do
+            mem_dual_wdecP.write(value) do
+                yay <= yay + 1 
+                value <= value + 1
+            end
+        end
+        # Read from mem_dual1 with decrement
+        hwhen(8) do
+            mem_dual_rdecP.read(result) do
+                yay <= yay + 1 
+            end
+        end
+        # Write to mem_file0 with address
+        hwhen(9) do
+            mem_file_waddrP.write(address,value) do
+                yay <= yay + 1 
+                address <= address + 1
+                value <= value + 1
+            end
+        end
+        # Read from mem_file0 with address
+        hwhen(10) do
+            mem_file_raddrP.read(address,result) do
+                yay <= yay + 1 
+                address <= address + 1
+            end
+        end
+        # Write to mem_file1 with increment
+        hwhen(11) do
+            mem_file_wincP.write(value) do
+                yay <= yay + 1 
+                value <= value + 1
+            end
+        end
+        # Read from mem_file1 with increment
+        hwhen(12) do
+            mem_file_rincP.read(result) do
+                yay <= yay + 1 
+            end
+        end
+        # Write to mem_file2 with increment
+        hwhen(13) do
+            mem_file_wdecP.write(value) do
+                yay <= yay + 1 
+                value <= value + 1
+            end
+        end
+        # Read from mem_file2 with increment
+        hwhen(14) do
+            mem_file_rdecP.read(result) do
+                yay <= yay + 1 
+            end
+        end
+        # Write to mem_file3 with num access
+        hwhen(15) do
+            mem_file_anumP.write(0,0)
+            mem_file_anumP.write(1,1)
+            mem_file_anumP.write(2,2)
+            mem_file_anumP.write(3,3)
+            mem_file_anumP.write(4,4)
+            mem_file_anumP.write(5,5)
+            mem_file_anumP.write(6,6)
+            mem_file_anumP.write(7,7) do
+                yay <= 8
+            end
+        end
+        # Read from mem_file3 with num access
+        hwhen(16) do
+            mem_file_anumP.read(0,res0)
+            mem_file_anumP.read(1,res1)
+            mem_file_anumP.read(2,res2)
+            mem_file_anumP.read(3,res3)
+            mem_file_anumP.read(4,res4)
+            mem_file_anumP.read(5,res5)
+            mem_file_anumP.read(6,res6)
+            mem_file_anumP.read(7,res7) do
+                yay <= 8
+            end
+        end
+        # Write to mem_file3 with num access
+        hwhen(17) do
+            mem_file_fixP[0].write(1)
+            mem_file_fixP[1].write(2)
+            mem_file_fixP[2].write(4)
+            mem_file_fixP[3].write(8)
+            mem_file_fixP[4].write(16)
+            mem_file_fixP[5].write(32)
+            mem_file_fixP[6].write(64)
+            mem_file_fixP[7].write(128) do
+                yay <= 8
+            end
+        end
+        # Read from mem_file3 with num access
+        hwhen(18) do
+            mem_file_fixP[0].read(res0)
+            mem_file_fixP[1].read(res1)
+            mem_file_fixP[2].read(res2)
+            mem_file_fixP[3].read(res3)
+            mem_file_fixP[4].read(res4)
+            mem_file_fixP[5].read(res5)
+            mem_file_fixP[6].read(res6)
+            mem_file_fixP[7].read(res7) do
+                yay <= 8
+            end
+        end
+    end
+
+
+    timed do
+        # Initialize everything.
+        clk <= 0
+        rst <= 0
+        step <= 0
+        yay <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        step <= 1
+
+        # Testing the synchronous memories.
+        256.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            hif(yay==8) do
+                step <= step + 1
+                yay <= 0
+            end
+            clk <= 0
+        end
+    end
+end

data/lib/HDLRuby/std/channel.rb

@@ -82,10 +82,10 @@ module HDLRuby::High::Std
 
 
     ##
-    #  Module for boxing channel ports.
-    module ChannelPortBoxing
-        # Box with +args+ arguments.
-        def box(*args)
+    #  Module for wrapping channel ports.
+    module ChannelPortWrapping
+        # Wrap with +args+ arguments.
+        def wrap(*args)
             return ChannelPortB.new(self,*args)
         end
     end
@@ -94,7 +94,7 @@ module HDLRuby::High::Std
     ##
     # Describes a read port to a channel.
     class ChannelPortR
-        include ChannelPortBoxing
+        include ChannelPortWrapping
 
         # Creates a new channel reader running in +namespace+ and
         # reading using +reader_proc+ and reseting using +reseter_proc+.
@@ -138,7 +138,7 @@ module HDLRuby::High::Std
     ##
     # Describes a writer port to a channel.
     class ChannelPortW
-        include ChannelPortBoxing
+        include ChannelPortWrapping
 
         # Creates a new channel writer running in +namespace+ and
         # writing using +writer_proc+ and reseting using +reseter_proc+.
@@ -182,7 +182,7 @@ module HDLRuby::High::Std
     ##
     # Describes an access port to a channel.
     class ChannelPortA
-        include ChannelPortBoxing
+        include ChannelPortWrapping
 
         # Creates a new channel accesser running in +namespace+
         # and reading using +reader_proc+, writing using +writer_proc+,
@@ -242,32 +242,61 @@ module HDLRuby::High::Std
 
 
     ##
-    # Describes port box (wrapper) for fixing arugments.
+    # Describes port wrapper (Box) for fixing arugments.
     class ChannelPortB
-        include ChannelPortBoxing
+        include ChannelPortWrapping
 
         # Creates a new channel box over channel port +port+ fixing +args+
         # as arguments.
+        # +args+ is a list of arguments to apply to all read, write
+        # and access procedure, nil values meaning that the corresponding
+        # argument is not overwritten.
+        # It can also be three lists for seperate read, write and access
+        # procedures using named arguments as:
+        # read: <read arguments>, write: <write arguments>,
+        # access: <access arguments>
         def initialize(port,*args)
             # Ensure port is a channel port.
             unless port.is_a?(ChannelPortR) || port.is_a?(ChannelPortW) ||
-                   port.is_a?(ChannelPortA)
+                    port.is_a?(ChannelPortA) || port.is_a?(ChannelPortB)
                 raise "Invalid class for a channel port: #{port.class}"
             end
             @port = port
-            @args = args
+            # Process the arguments.
+            if args.size == 1 && args[0].is_a?(Hash) then
+                # Read, write and access are separated.
+                @args_read = args[0][:read]
+                @args_write = args[0][:write]
+                @args_access = args[0][:access]
+            else
+                @args_read = args
+                @args_write = args.clone
+                @args_access = args.clone
+            end
         end
 
         ## Performs a read on the channel using +args+ and +ruby_block+
         #  as arguments.
         def read(*args,&ruby_block)
-            @port.read(*@args,*args)
+            # Generate the final arguments: fills the nil with arguments
+            # from args
+            rargs = @args_read.clone
+            rargs.map! { |arg| arg == nil ? args.shift : arg }
+            # And add the remaining at the tail.
+            rargs += args
+            @port.read(*rargs,&ruby_block)
         end
 
         ## Performs a write on the channel using +args+ and +ruby_block+
         #  as arguments.
         def write(*args,&ruby_block)
-            @port.write(*@args,*args)
+            # Generate the final arguments: fills the nil with arguments
+            # from args
+            rargs = @args_write.clone
+            rargs.map! { |arg| arg == nil ? args.shift : arg }
+            # And add the remaining at the tail.
+            rargs += args
+            @port.write(*rargs,&ruby_block)
         end
 
         ## Performs a reset on the channel using +args+ and +ruby_block+

data/lib/HDLRuby/std/memory.rb

@@ -243,23 +243,14 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
     typ.inner :dbus_r, :dbus_w
     # Address buses (or simply registers)
     [awidth].inner :abus_r, :abus_w
-    # # Address buffers
-    # [awidth].inner :abus_r_reg
 
     # Declare the memory content.
     typ[-size].inner :mem
 
-    # # Processes handling the memory access.
-    par(clk.posedge) do
-    #     # # Output memory value for reading at each cycle.
-    #     # dbus_r <= mem[abus_r_reg]
-        # Manage the write to the memory.
-        hif(trig_w) { mem[abus_w] <= dbus_w }
-    end
-    # par(clk.negedge) { abus_r_reg <= abus_r }
+    # Processes handling the memory access.
     par(clk.negedge) do
         dbus_r <= mem[abus_r]
-        # hif(trig_w) { mem[abus_w] <= dbus_w }
+        hif(trig_w) { mem[abus_w] <= dbus_w }
     end
 
     # The address branches.
@@ -403,10 +394,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the write.
-                    hif(trig_w == 1) do
-                        # The trigger was previously set, write ok.
-                        blk.call
-                    end if blk
+                    blk.call if blk
                     # Prepare the write.
                     abus_w <= abus_w + 1
                     trig_w <= 1
@@ -416,6 +404,84 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
         end
     end
 
+
+    # The decrement branches.
+    # Read with increment
+    brancher(:rdec) do
+        reader_output :trig_r, :abus_r
+        reader_input :dbus_r
+        if br_rsts[:rdec] then
+            rst_name = br_rsts[:rdec].to_sym
+        else
+            rst_name = rst.name
+            reader_input rst_name
+        end
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        reader do |blk,target|
+            # By default the read trigger is 0.
+            rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst==1) { abus_r <= 0 }
+                # Reset so switch of the access trigger.
+                trig_r <= 0
+            end
+            # The read procedure.
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the read.
+                    hif(trig_r == 1) do
+                        # The trigger was previously set, read ok.
+                        target <= dbus_r
+                        blk.call if blk
+                    end
+                    # Prepare the read.
+                    abus_r <= abus_r - 1
+                    trig_r <= 1
+                end
+            end
+        end
+    end
+
+    # Write with address
+    brancher(:wdec) do
+        writer_output :trig_w, :abus_w, :dbus_w
+        if br_rsts[:wdec] then
+            rst_name = br_rsts[:wdec].to_sym
+        else
+            rst_name = rst.name
+            writer_input rst_name
+        end
+        # puts "br_rsts=#{br_rsts}"
+        # puts "rst_name=#{rst_name}"
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        writer do |blk,target|
+            # By default the read trigger is 0.
+            rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst == 1) { abus_w <= 0 }
+                # Reset so switch of the access trigger.
+                trig_w <= 0
+            end
+            # The write procedure.
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the write.
+                    blk.call if blk
+                    # Prepare the write.
+                    abus_w <= abus_w - 1
+                    trig_w <= 1
+                    dbus_w <= target
+                end
+            end
+        end
+    end
+
 end
 
 
@@ -436,8 +502,7 @@ end
 #
 # * The following branches are possible (only one read and one write can
 #   be used per channel)
-#   - rnum:    read by register number, the number must be a defined value.
-#   - wnum:    writer by register number, the number must be a defined value.
+#   - anum:    access by register number, the number must be a defined value.
 #   - raddr:   read by address
 #   - waddr:   read by address
 #   - rinc:    read by automatically incremented address.
@@ -536,7 +601,6 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
     # Read with address
     brancher(:raddr) do
         size.times { |i| reader_input :"reg_#{i}" }
-        regs = size.times.map {|i| send(:"reg_#{i}") }
         if br_rsts[:raddr] then
             rst_name = br_rsts[:raddr].to_sym
         else
@@ -547,6 +611,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
         # Defines the read procedure at address +addr+
         # using +target+ as target of access result.
         reader do |blk,addr,target|
+            regs = size.times.map {|i| send(:"reg_#{i}") }
             # The read procedure.
             rst  = send(rst_name)
             par do
@@ -565,7 +630,6 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
     # Write with address
     brancher(:waddr) do
         size.times { |i| writer_output :"reg_#{i}" }
-        regs = size.times.map {|i| send(:"reg_#{i}") }
         if br_rsts[:waddr] then
             rst_name = br_rsts[:waddr].to_sym
         else
@@ -576,6 +640,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
         # Defines the writer procedure at address +addr+
         # using +target+ as target of access.
         writer do |blk,addr,target|
+            regs = size.times.map {|i| send(:"reg_#{i}") }
             # The writer procedure.
             rst  = send(rst_name)
             par do
@@ -672,4 +737,83 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
     end
 
 
+    # The decrement branches.
+    # Read with decrement
+    brancher(:rdec) do
+        size.times { |i| reader_input :"reg_#{i}" }
+        if br_rsts[:rdec] then
+            rst_name = br_rsts[:rdec].to_sym
+        else
+            rst_name = rst.name
+            reader_input rst_name
+        end
+        # Declares the address counter.
+        [size.width-1].inner :abus_r
+        reader_inout :abus_r
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        reader do |blk,target|
+            regs = size.times.map {|i| send(:"reg_#{i}") }
+            # By default the read trigger is 0.
+            rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst==1) { abus_r <= -1 }
+            end
+            # The read procedure.
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the read.
+                    hcase(abus_r)
+                    size.times do |i|
+                        hwhen(i) { target <= regs[i] }
+                    end
+                    blk.call if blk
+                    # Prepare the next read.
+                    abus_r <= abus_r - 1
+                end
+            end
+        end
+    end
+
+    # Write with decrement
+    brancher(:wdec) do
+        size.times { |i| writer_output :"reg_#{i}" }
+        if br_rsts[:wdec] then
+            rst_name = br_rsts[:wdec].to_sym
+        else
+            rst_name = rst.name
+            reader_input rst_name
+        end
+        # Declares the address counter.
+        [size.width-1].inner :abus_w
+        reader_inout :abus_w
+
+        # Defines the write procedure at address +addr+
+        # using +target+ as target of access result.
+        writer do |blk,target|
+            regs = size.times.map {|i| send(:"reg_#{i}") }
+            # By default the read trigger is 0.
+            rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst==1) { abus_w <= -1 }
+            end
+            # The read procedure.
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the read.
+                    hcase(abus_w)
+                    size.times do |i|
+                        hwhen(i) { regs[i] <= target }
+                    end
+                    blk.call if blk
+                    # Prepare the next write.
+                    abus_w <= abus_w - 1
+                end
+            end
+        end
+    end
+
 end

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.2.13"
+  VERSION = "2.2.14"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.2.13
+  version: 2.2.14
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-03-25 00:00:00.000000000 Z
+date: 2020-03-26 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -84,6 +84,7 @@ files:
 - lib/HDLRuby/hdr_samples/instance_open.rb
 - lib/HDLRuby/hdr_samples/mei8.rb
 - lib/HDLRuby/hdr_samples/mei8_bench.rb
+- lib/HDLRuby/hdr_samples/memory_test.rb
 - lib/HDLRuby/hdr_samples/multer_gen.rb
 - lib/HDLRuby/hdr_samples/multer_seq.rb
 - lib/HDLRuby/hdr_samples/neural/a.rb