HDLRuby 2.2.12 → 2.2.13

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -740,6 +740,8 @@ inner :w1
 [1..0].inner :w2
 ```
 
+If the signal is not meant to be changed, in can be declared using the `constant` keyword instead of `inner`.
+
 A connection between signals is done using the arrow operator `<=` as follows:
 
 ```ruby
@@ -828,6 +830,28 @@ system :mem16_16 do
 end
 ```
 
+### Initialization of signals
+<a name="initialization"></a>
+
+Output, inner and constant signals of a system can be initial when declared using the following syntax in place of the usual name of the signal:
+
+```ruby
+<signal name>: <intial value>
+```
+
+For example a single bit inner signal named `sig` can be initialized to 0 as follows:
+
+```ruby
+inner sig: 0
+```
+
+As an other example, a 8-bit 8-word ROM could be declared and initialized as follows:
+
+```ruby
+bit[8][-8] rom: [ 0,1,2,3,4,5,6,7 ]
+```
+
+
 ### Scope in a system
 
 #### General scopes
@@ -2757,6 +2781,26 @@ fsm(clk.posedge,rst,:sync) do
 end
 ```
 
+
+## Fixed-point (fixpoint)
+<a name="fixpoint"></a>
+
+This library provides a new fixed point set of data types. These new data types can be bit vectors, unsigned or signed value and are declared respectively as follows:
+
+```ruby
+bit[<integer part range>,<fractional part range>]
+unsigned[<integer part range>,<fractional part range>]
+signed[<integer part range>,<fractional part range>]
+```
+
+For example a signed 4-bit integer part 4-bit fractional part fixed point inner signal named `sig` can be declared as follows:
+
+```ruby
+bit[4,4].inner :sig
+```
+
+When performing computation with fixed point types, HDLRuby ensures that the result's decimal point position is correct.
+
 ## Channel
 <a name="channel"></a>
 

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -0,0 +1,25 @@
+require "std/fixpoint.rb"
+
+include HDLRuby::High::Std
+
+
+
+# System for testing the fixed point library.
+system :fix_test do
+
+    # Declare three 4-bit integer part 4-bit fractional part
+    bit[3..0,3..0].inner :x,:y,:z
+
+    # Performs calculation between then
+    timed do
+        x <= _00110011
+        y <= _01000000
+        !10.ns
+        z <= x + y
+        !10.ns
+        z <= x * y
+        !10.ns
+        z <= z / x
+        !10.ns
+    end
+end

data/lib/HDLRuby/hruby_low2c.rb

@@ -519,8 +519,10 @@ module HDLRuby::Low
         # Generates the C text of the equivalent HDLRuby::High code.
         # +level+ is the hierachical level of the object.
         def to_c(level = 0)
-            # Simply use the name of the type.
-            return Low2C.type_name(self.name) + "()"
+            # # Simply use the name of the type.
+            # return Low2C.type_name(self.name) + "()"
+            # Simply return the defined type.
+            return self.def.to_c(level)
         end
     end
 

data/lib/HDLRuby/sim/hruby_sim.h

@@ -150,6 +150,13 @@ extern Value sub_value(Value src0, Value src1, Value dst);
  *  @return dst */
 extern Value mul_value(Value src0, Value src1, Value dst);
 
+/** Computes the division of two general values.
+ *  @param src0 the first source value of the addition
+ *  @param src1 the second source value of the addition
+ *  @param dst the destination value
+ *  @return dst */
+extern Value div_value(Value src0, Value src1, Value dst);
+
 /** Computes the not of a value.
  *  @param src the source value of the not
  *  @param dst the destination value

data/lib/HDLRuby/sim/hruby_sim_calc.c

@@ -601,6 +601,22 @@ static Value mul_value_defined_bitstring(Value src0, Value src1, Value dst) {
 }
 
 
+/** Computes the division of two defined bitstring values.
+ *  @param src0 the first source value of the addition
+ *  @param src1 the second source value of the addition
+ *  @param dst the destination value
+ *  @return dst */
+static Value div_value_defined_bitstring(Value src0, Value src1, Value dst) {
+    /* Sets state of the destination using the first source. */
+    dst->type = src0->type;
+    dst->numeric = 1;
+
+    /* Perform the addition. */
+    dst->data_int = value2integer(src0) / value2integer(src1);
+    return dst;
+}
+
+
 /** Computes the NOT of a bitstring value.
  *  @param src the source value of the not
  *  @param dst the destination value
@@ -1412,6 +1428,22 @@ static Value mul_value_numeric(Value src0, Value src1, Value dst) {
 }
 
 
+/** Computes the division of two numeric values.
+ *  @param src0 the first source value of the addition
+ *  @param src1 the second source value of the addition
+ *  @param dst the destination value
+ *  @return dst */
+static Value div_value_numeric(Value src0, Value src1, Value dst) {
+    /* Sets state of the destination using the first source. */
+    dst->type = src0->type;
+    dst->numeric = 1;
+
+    /* Perform the addition. */
+    dst->data_int = src0->data_int / src1->data_int;
+    return dst;
+}
+
+
 /** Computes the NOT of a numeric value.
  *  @param src the source value of the not
  *  @param dst the destination value
@@ -1833,6 +1865,33 @@ Value mul_value(Value src0, Value src1, Value dst) {
 }
 
 
+/** Computes the division of two general values.
+ *  @param src0 the first source value of the addition
+ *  @param src1 the second source value of the addition
+ *  @param dst the destination value
+ *  @return dst */
+Value div_value(Value src0, Value src1, Value dst) {
+    /* Might allocate a new value so save the current pool state. */
+    unsigned int pos = get_value_pos();
+    /* Do a numeric computation if possible, otherwise fallback to bitstring
+     * computation. */
+    if (src0->numeric && src1->numeric) {
+        /* Both sources are numeric. */
+        return div_value_numeric(src0,src1,dst);
+    } else if (is_defined_value(src0) && is_defined_value(src1)) {
+        /* Both sources can be converted to numeric values. */
+        return div_value_defined_bitstring(src0,src1,dst);
+    } else {
+        /* Cannot compute (for now), simply undefines the destination. */
+        /* First ensure dst has the right shape. */
+        copy_value(src0,dst);
+        /* Then make it undefined. */
+        set_undefined_bitstring(dst);
+    }
+    return dst;
+}
+
+
 /** Computes the NOT of a general value.
  *  @param src the source value of the not
  *  @param dst the destination value

data/lib/HDLRuby/sim/hruby_sim_core.c

@@ -91,9 +91,10 @@ void register_signal(SignalI signal) {
             all_signals = calloc(sizeof(SignalI),cap_all_signals);
         } else {
             /* Need to increase the capacity. */
-            Behavior* behaviors = calloc(sizeof(Behavior),cap_all_signals*2);
-            memcpy(all_signals,behaviors,sizeof(Behavior)*cap_all_signals);
+            SignalI* new_signals = calloc(sizeof(SignalI),cap_all_signals*2);
+            memcpy(new_signals,all_signals,sizeof(SignalI)*cap_all_signals);
             cap_all_signals *= 2;
+            all_signals=new_signals;
         }
     }
     /* Add the behavior. */

data/lib/HDLRuby/std/channel.rb

@@ -70,7 +70,8 @@ module HDLRuby::High::Std
     ## Creates directly an instance of channel named +name+ using
     #  +ruby_block+ built with +args+.
     def self.channel_instance(name,*args,&ruby_block)
-        return ChannelT.new(:"",&ruby_block).instantiate(name,*args)
+        # return ChannelT.new(:"",&ruby_block).instantiate(name,*args)
+        return self.channel(:"",&ruby_block).instantiate(name,*args)
     end
 
     ## Creates directly an instance of channel named +name+ using
@@ -80,9 +81,20 @@ module HDLRuby::High::Std
     end
 
 
+    ##
+    #  Module for boxing channel ports.
+    module ChannelPortBoxing
+        # Box with +args+ arguments.
+        def box(*args)
+            return ChannelPortB.new(self,*args)
+        end
+    end
+
+
     ##
     # Describes a read port to a channel.
     class ChannelPortR
+        include ChannelPortBoxing
 
         # Creates a new channel reader running in +namespace+ and
         # reading using +reader_proc+ and reseting using +reseter_proc+.
@@ -126,6 +138,7 @@ module HDLRuby::High::Std
     ##
     # Describes a writer port to a channel.
     class ChannelPortW
+        include ChannelPortBoxing
 
         # Creates a new channel writer running in +namespace+ and
         # writing using +writer_proc+ and reseting using +reseter_proc+.
@@ -166,10 +179,10 @@ module HDLRuby::High::Std
     end
 
 
-
     ##
     # Describes an access port to a channel.
     class ChannelPortA
+        include ChannelPortBoxing
 
         # Creates a new channel accesser running in +namespace+
         # and reading using +reader_proc+, writing using +writer_proc+,
@@ -228,6 +241,44 @@ module HDLRuby::High::Std
     end
 
 
+    ##
+    # Describes port box (wrapper) for fixing arugments.
+    class ChannelPortB
+        include ChannelPortBoxing
+
+        # Creates a new channel box over channel port +port+ fixing +args+
+        # as arguments.
+        def initialize(port,*args)
+            # Ensure port is a channel port.
+            unless port.is_a?(ChannelPortR) || port.is_a?(ChannelPortW) ||
+                   port.is_a?(ChannelPortA)
+                raise "Invalid class for a channel port: #{port.class}"
+            end
+            @port = port
+            @args = args
+        end
+
+        ## Performs a read on the channel using +args+ and +ruby_block+
+        #  as arguments.
+        def read(*args,&ruby_block)
+            @port.read(*@args,*args)
+        end
+
+        ## Performs a write on the channel using +args+ and +ruby_block+
+        #  as arguments.
+        def write(*args,&ruby_block)
+            @port.write(*@args,*args)
+        end
+
+        ## Performs a reset on the channel using +args+ and +ruby_block+
+        #  as arguments.
+        def reset(*args,&ruby_block)
+            @port.reset(*@args,*args)
+        end
+    end
+
+
+
     ## 
     # Describes a high-level channel instance.
     class ChannelI
@@ -520,12 +571,12 @@ module HDLRuby::High::Std
 
         # Defines a branch in the channel named +name+ built executing
         # +ruby_block+.
-        def brancher(name,*args,&ruby_block)
+        def brancher(name,&ruby_block)
             # Ensure name is a symbol.
             name = name.to_s unless name.respond_to?(:to_sym)
             name = name.to_sym
             # Create the branch.
-            channelI = HDLRuby::High.channel_instance(name,*args,&ruby_block)
+            channelI = HDLRuby::High.channel_instance(name, &ruby_block)
             @branches[name] = channelI
         end
 
@@ -534,7 +585,7 @@ module HDLRuby::High::Std
         
         # Gets branch channel +name+.
         # NOTE: +name+ can be of any type on purpose.
-        def branch(name)
+        def branch(name,*args)
             # Ensure name is a symbol.
             name = name.to_s unless name.respond_to?(:to_sym)
             name = name.to_sym

data/lib/HDLRuby/std/fixpoint.rb

@@ -0,0 +1,67 @@
+module HDLRuby::High::Std
+
+##
+# Standard HDLRuby::High library: fixed point types.
+# 
+########################################################################
+
+    # Save the former included.
+    class << self
+        alias_method :_included_fixpoint, :included
+    end
+
+    # Redefines the include to add fixed point generation through the Type
+    # class.
+    def self.included(base)
+        # Performs the previous included
+        res = self.send(:_included_fixpoint,base)
+        # Now modify the Type class
+        ::HDLRuby::High::Type.class_eval do
+            # Saves the former type generation method.
+            alias_method :"_[]_fixpoint", :[]
+
+            # Redefine the type generation method for supporting fixed point
+            # type generation.
+            def [](*args)
+                if args.size == 1 then
+                    return self.send(:"_[]_fixpoint",*args)
+                else
+                    # Handle the arguments.
+                    arg0,arg1 = *args
+                    if arg0.respond_to?(:to_i) then
+                        arg0 = (arg0.to_i.abs-1)..0
+                    end
+                    if arg1.respond_to?(:to_i) then
+                        arg1 = (arg1.to_i.abs-1)..0
+                    end
+                    # Compute the fix point sizes.
+                    isize = (arg0.first-arg0.last).abs+1
+                    fsize = (arg1.first-arg1.last).abs+1
+                    # Build the type.
+                    case(self.name)
+                    when :bit
+                        typ = bit[isize+fsize].typedef(::HDLRuby.uniq_name)
+                    when :unsigned
+                        typ = unsigned[isize+fsize].typedef(::HDLRuby.uniq_name)
+                    when :signed
+                        typ = signed[isize+fsize].typedef(::HDLRuby.uniq_name)
+                    else
+                        raise "Invalid type for generating a fixed point type: #{self.name}"
+                    end
+                    # Redefine the multiplication and division for fixed point.
+                    typ.define_operator(:*) do |left,right|
+                        (left.as([isize+fsize*2])*right) >> fsize
+                    end
+                    typ.define_operator(:/) do |left,right|
+                        (left.as([isize+fsize*2]) << fsize) / right
+                    end
+                    typ
+                end
+            end
+            return res
+        end
+    end
+
+
+
+end

data/lib/HDLRuby/std/memory.rb

@@ -71,13 +71,15 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
                 rwb  = send(:"rwb_#{p}")
                 rst  = send(rst_name)
                 # Use it to make the access.
-                hif (rst) do
-                    # Reset case
-                    cs <= 0
-                    abus <= 0
-                    rwb <= 0
+                top_block.unshift do
+                    hif (rst) do
+                        # Reset case
+                        cs <= 0
+                        abus <= 0
+                        rwb <= 0
+                    end
                 end
-                helsif (cs == 0) do
+                hif(cs == 0) do
                     # Start the access.
                     cs <= 1
                     rwb <= 1
@@ -101,13 +103,15 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
                 rwb  = send(:"rwb_#{p}")
                 rst  = send(rst_name)
                 # Use it to make the access.
-                hif (rst) do
-                    # Reset case
-                    cs <= 0
-                    abus <= 0
-                    rwb <= 0
+                top_block.unshift do
+                    hif (rst) do
+                        # Reset case
+                        cs <= 0
+                        abus <= 0
+                        rwb <= 0
+                    end
                 end
-                helsif (cs == 0) do
+                hif(cs == 0) do
                     # Start the access.
                     cs <= 1
                     rwb <= 0
@@ -119,6 +123,8 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
                     cs <= 0
                     rwb <= 0
                     dbus <= "z" * typ.width
+                    # Execute the blk.
+                    blk.call if blk
                 end
             end
         end
@@ -237,20 +243,24 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
     typ.inner :dbus_r, :dbus_w
     # Address buses (or simply registers)
     [awidth].inner :abus_r, :abus_w
-    # Address buffers
-    [awidth].inner :abus_r_reg
+    # # Address buffers
+    # [awidth].inner :abus_r_reg
 
     # Declare the memory content.
     typ[-size].inner :mem
 
-    # Processes handling the memory access.
+    # # Processes handling the memory access.
     par(clk.posedge) do
-        # Output memory value for reading at each cycle.
-        dbus_r <= mem[abus_r_reg]
+    #     # # Output memory value for reading at each cycle.
+    #     # dbus_r <= mem[abus_r_reg]
         # Manage the write to the memory.
         hif(trig_w) { mem[abus_w] <= dbus_w }
     end
-    par(clk.negedge) { abus_r_reg <= abus_r }
+    # par(clk.negedge) { abus_r_reg <= abus_r }
+    par(clk.negedge) do
+        dbus_r <= mem[abus_r]
+        # hif(trig_w) { mem[abus_w] <= dbus_w }
+    end
 
     # The address branches.
     # Read with address
@@ -277,11 +287,14 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
                         target <= dbus_r
+                        trig_r <= 0
                         blk.call if blk
                     end
-                    # Prepare the read.
-                    abus_r <= addr
-                    trig_r <= 1
+                    helse do
+                        # Prepare the read.
+                        abus_r <= addr
+                        trig_r <= 1
+                    end
                 end
             end
         end
@@ -499,6 +512,23 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                 blk.call if blk
             end
         end
+
+        # Defines a conversion to array as list of fixed inner accessers.
+        define_singleton_method(:inners) do |name|
+            # The resulting array.
+            chbs = []
+            # Declare the fixed inners with uniq names, box them and
+            # add the result to the resulting array.
+            size.times do |i|
+                port = inner HDLRuby.uniq_name
+                chbs << port.box(i)
+            end
+            # Register the array as name.
+            HDLRuby::High.space_reg(name) { chbs }
+            # Return it.
+            return chbs
+        end
+
     end
 
     

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.2.12"
+  VERSION = "2.2.13"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.2.12
+  version: 2.2.13
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-03-20 00:00:00.000000000 Z
+date: 2020-03-25 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -115,6 +115,7 @@ files:
 - lib/HDLRuby/hdr_samples/with_channel.rb
 - lib/HDLRuby/hdr_samples/with_class.rb
 - lib/HDLRuby/hdr_samples/with_decoder.rb
+- lib/HDLRuby/hdr_samples/with_fixpoint.rb
 - lib/HDLRuby/hdr_samples/with_fsm.rb
 - lib/HDLRuby/hdr_samples/with_memory.rb
 - lib/HDLRuby/hdr_samples/with_reconf.rb
@@ -262,6 +263,7 @@ files:
 - lib/HDLRuby/std/clocks.rb
 - lib/HDLRuby/std/counters.rb
 - lib/HDLRuby/std/decoder.rb
+- lib/HDLRuby/std/fixpoint.rb
 - lib/HDLRuby/std/fsm.rb
 - lib/HDLRuby/std/memory.rb
 - lib/HDLRuby/std/pipeline.rb