HDLRuby 2.2.0 → 2.2.2
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- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/adder_kadai.rb +7 -0
- data/lib/HDLRuby/hruby_low.rb +10 -0
- data/lib/HDLRuby/hruby_low_without_concat.rb +87 -1
- data/lib/HDLRuby/hruby_verilog.rb +8 -1
- data/lib/HDLRuby/version.rb +1 -1
- metadata +3 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: ce1d3b652bf8a3590f023acab0e74ec08d6062df5ccbc38fb1e1cbeb2cd41028
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4
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data.tar.gz: 52461928e01080214a4fb6ce0f1f852c6403d26bfd152579755e6b2990c396d2
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 193afd5d38ef5159a89630f9f44be2e43c95925f9d6f0d037616e26fb9dc5538fce721be53ebfc7c08ce303e6937f7eddf6bf6493cb741c485ec878c538c28a6
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data.tar.gz: d666fca088c1c737f81cccbbc58982e194ee0cff2fcd801e2ac9f13d504de04f3be4f3dae66dd6408af1c9d079b3f9c7dad0334c08bd77ad20daaae513058f92
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data/lib/HDLRuby/hruby_low.rb
CHANGED
@@ -3696,6 +3696,16 @@ module HDLRuby::Low
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3696
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def hash
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return super
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end
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3699
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3700
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# Gets the top block, i.e. the first block of the current behavior.
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def top_block
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raise AnyError, "Connections are not within blocks."
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end
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# Gets the top scope, i.e. the first scope of the current system.
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3706
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def top_scope
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3707
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return self.parent.is_a?(Scope) ? self.parent : self.parent.top_scope
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3708
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end
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end
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@@ -41,7 +41,8 @@ module HDLRuby::Low
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if nconnection.is_a?(Block) then
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# The connection has been broken, remove the former
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# version and add the generated block as a behavior.
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-
self.remove_connection(connection)
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# self.remove_connection(connection)
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self.delete_connection!(connection)
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self.add_behavior(Behavior.new(nconnection))
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end
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end
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@@ -159,4 +160,89 @@ module HDLRuby::Low
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return self
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end
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end
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+
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## Extends the Connection class with functionality for breaking assingments
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# to concats.
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class Connection
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# Break the assignments to concats.
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#
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# NOTE: when breaking generates a new Block containing the broken
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# assignments.
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def break_concat_assigns
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# puts "break_concat_assigns with self=#{self}"
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# Is the left value a RefConcat?
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self.left.each_node_deep do |node|
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if node.is_a?(RefConcat) then
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# Yes, must break. Create the resulting sequential
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# block that will contain the new assignements.
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block = Block.new(:seq)
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# Create an intermediate signal for storing the
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# right value. Put it in the top scope.
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top_scope = self.top_scope
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aux = top_scope.add_inner(
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SignalI.new(HDLRuby.uniq_name,self.right.type) )
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# puts "new signal: #{aux.name}"
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aux = RefName.new(aux.type,RefThis.new,aux.name)
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# Set a default value to avoid latch generation.
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block.insert_statement!(0,
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Transmit.new(aux.clone,Value.new(aux.type,0)))
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# Replace the concat in the copy of the left value.
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if left.eql?(node) then
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# node was the top of left, replace here.
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nleft = aux
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else
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# node was inside left, replace within left.
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nleft = self.left.clone
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nleft.each_node_deep do |ref|
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ref.map_nodes! do |sub|
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sub.eql?(node) ? aux.clone : sub
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end
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end
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end
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# Recreate the transmit and add it to the block.
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block.add_statement(
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Transmit.new(nleft,self.right.clone) )
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# And assign its part to each reference of the
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# concat.
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pos = 0
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node.each_ref.reverse_each do |ref|
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# Compute the range to assign.
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range = ref.type.width-1+pos .. pos
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# Single or multi-bit range?
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sbit = range.first == range.last
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# Convert the range to an HDLRuby range for
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# using is the resulting statement.
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# Create and add the statement.
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if sbit then
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# Single bit.
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# Generate the index.
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idx = Value.new(Integer,range.first)
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# Generate the assignment.
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222
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block.add_statement(
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223
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Transmit.new(ref.clone,
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RefIndex.new(aux.type.base, aux.clone, idx)))
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else
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# Multi-bits.
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# Compute the type of the right value.
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rtype = TypeVector.new(:"",aux.type.base,range)
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# Generate the range.
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range = Value.new(Integer,range.first) ..
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Value.new(Integer,range.last)
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# Generate the assignment.
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block.add_statement(
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Transmit.new(ref.clone,
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RefRange.new(rtype, aux.clone, range)))
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end
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pos += ref.type.width
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end
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# puts "Resulting block=#{block.to_vhdl}"
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# Return the resulting block
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241
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return block
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end
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end
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# No, nothing to do.
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return self
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end
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end
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end
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@@ -1537,8 +1537,15 @@ end
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# Used when casting expressions.
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class Cast
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# Converts the system to Verilog code.
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# NOTE: the cast is rounded up size bit-width cast is not supported
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# by traditional verilog.
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def to_verilog
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1541
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-
return "#{self.type.to_verilog}'(#{self.child.to_verilog})"
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# return "#{self.type.to_verilog}'(#{self.child.to_verilog})"
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1544
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if self.type.signed? then
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1545
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return "$signed(#{self.child.to_verilog})"
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1546
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else
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1547
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return "$unsigned(#{self.child.to_verilog})"
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end
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end
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end
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data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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2
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name: HDLRuby
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version: !ruby/object:Gem::Version
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-
version: 2.2.
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version: 2.2.2
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platform: ruby
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authors:
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- Lovic Gauthier
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autorequire:
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bindir: exe
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cert_chain: []
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-
date: 2020-03-
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date: 2020-03-09 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: bundler
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@@ -70,6 +70,7 @@ files:
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70
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- lib/HDLRuby/hdr_samples/adder_assign_error.rb
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71
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- lib/HDLRuby/hdr_samples/adder_bench.rb
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- lib/HDLRuby/hdr_samples/adder_gen.rb
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73
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+
- lib/HDLRuby/hdr_samples/adder_kadai.rb
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- lib/HDLRuby/hdr_samples/adder_nodef_error.rb
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- lib/HDLRuby/hdr_samples/addsub.rb
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- lib/HDLRuby/hdr_samples/addsubz.rb
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