HDLRuby 2.11.7 → 2.11.9

checksums.yaml

@@ -1,7 +1,7 @@
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data/ext/hruby_sim/hruby_sim.h

@@ -1111,7 +1111,7 @@ extern Value binary(Value (*oper)(Value,Value,Value));
  *  @param num the number of values to select from.
  *  @return the destination.
  **/
-extern Value select(unsigned int num);
+extern Value hselect(unsigned int num);
 
 /** Cast calculation.
  *  @param typ the type to cast to.

data/ext/hruby_sim/hruby_sim_stack_calc.c

@@ -108,7 +108,7 @@ Value binary(Value (*oper)(Value,Value,Value)) {
 
 /** Selection calculation.
  * @param num the number of choices to select within. */
-Value select(unsigned int num) {
+Value hselect(unsigned int num) {
     Value* vals = alloca(num*sizeof(Value));
     int i;
     /* Get the values to concat from the stack. */

data/lib/HDLRuby/hdrcc.rb

@@ -641,23 +641,23 @@ elsif $options[:clang] then
     # top_system = $top_system
     # Preprocess the HW description for valid C generation.
     $top_system.each_systemT_deep do |systemT|
-        HDLRuby.show "seq2seq step..."
+        HDLRuby.show? "seq2seq step..."
         # Coverts the par blocks in seq blocks to seq blocks to match
         # the simulation engine.
         systemT.par_in_seq2seq!
-        HDLRuby.show "#{Time.now}#{show_mem}"
-        HDLRuby.show "connections_to_behaviors step..."
+        HDLRuby.show? "#{Time.now}#{show_mem}"
+        HDLRuby.show? "connections_to_behaviors step..."
         # Converts the connections to behaviors.
         systemT.connections_to_behaviors!
-        HDLRuby.show "#{Time.now}#{show_mem}"
+        HDLRuby.show? "#{Time.now}#{show_mem}"
         # Break the RefConcat.
-        HDLRuby.show "concat_assigns step..."
+        HDLRuby.show? "concat_assigns step..."
         systemT.break_concat_assigns! 
-        HDLRuby.show "#{Time.now}#{show_mem}"
+        HDLRuby.show? "#{Time.now}#{show_mem}"
         # Explicits the types.
-        HDLRuby.show "explicit_types step..."
+        HDLRuby.show? "explicit_types step..."
         systemT.explicit_types!
-        HDLRuby.show "#{Time.now}#{show_mem}"
+        HDLRuby.show? "#{Time.now}#{show_mem}"
     end
     # Generate the C.
     if $options[:multiple] then
@@ -788,8 +788,12 @@ elsif $options[:clang] then
                 "   Then execute:\n   hruby_simulator"
         end
         # Use it.
+        HDLRuby.show "Compiling C code of the simulator..."
         Kernel.system("#{cc_cmd} -o3 -o hruby_simulator *.c -lpthread")
+        HDLRuby.show "#{Time.now}#{show_mem}"
+        HDLRuby.show "Executing the simulator..."
         Kernel.system("./hruby_simulator")
+        HDLRuby.show "#{Time.now}#{show_mem}"
     end
 elsif $options[:verilog] then
     # warn("Verilog HDL output is not available yet... but it will be soon, promise!")
@@ -800,25 +804,25 @@ elsif $options[:verilog] then
         # HDLRuby.show "casts_without_expression! step..."
         # systemT.casts_without_expression!
         # HDLRuby.show Time.now
-        HDLRuby.show "to_upper_space! step..."
+        HDLRuby.show? "to_upper_space! step..."
         systemT.to_upper_space!
-        HDLRuby.show "#{Time.now}#{show_mem}"
+        HDLRuby.show? "#{Time.now}#{show_mem}"
     end
-    HDLRuby.show "to_global_space! step (global)..."
+    HDLRuby.show? "to_global_space! step (global)..."
     $top_system.to_global_systemTs!
-    HDLRuby.show "#{Time.now}#{show_mem}"
+    HDLRuby.show? "#{Time.now}#{show_mem}"
     $top_system.each_systemT_deep do |systemT|
         ## systemT.break_types!
         ## systemT.expand_types!
-        HDLRuby.show "par_in_seq2seq! step..."
+        HDLRuby.show? "par_in_seq2seq! step..."
         systemT.par_in_seq2seq!
-        HDLRuby.show "#{Time.now}#{show_mem}"
-        HDLRuby.show "initial_concat_to_timed! step..."
+        HDLRuby.show? "#{Time.now}#{show_mem}"
+        HDLRuby.show? "initial_concat_to_timed! step..."
         systemT.initial_concat_to_timed!
-        HDLRuby.show "#{Time.now}#{show_mem}"
-        HDLRuby.show "with_port! step..."
+        HDLRuby.show? "#{Time.now}#{show_mem}"
+        HDLRuby.show? "with_port! step..."
         systemT.with_port!
-        HDLRuby.show "#{Time.now}#{show_mem}"
+        HDLRuby.show? "#{Time.now}#{show_mem}"
     end
     # # Verilog generation
     # $output << top_system.to_verilog

data/lib/HDLRuby/hruby_low2c.rb

@@ -2630,7 +2630,7 @@ module HDLRuby::Low
             end
             # Compute the resulting selection.
             res << (" " * (level*3))
-            res << "select(#{expressions.size});\n"
+            res << "hselect(#{expressions.size});\n"
             # Restore the value pool state.
             res << (" " * (level*3)) << "RV;\n"
             return res

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.11.7"
+  VERSION = "2.11.9"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.11.7
+  version: 2.11.9
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire:
 bindir: exe
 cert_chain: []
-date: 2022-11-10 00:00:00.000000000 Z
+date: 2022-11-11 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler