HDLRuby 2.11.5 → 2.11.8
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- checksums.yaml +4 -4
- data/ext/hruby_sim/hruby_rcsim_build.c +84 -48
- data/ext/hruby_sim/hruby_sim.h +65 -1
- data/ext/hruby_sim/hruby_sim_calc.c +211 -28
- data/ext/hruby_sim/hruby_sim_core.c +58 -4
- data/ext/hruby_sim/hruby_sim_mute.c +65 -0
- data/ext/hruby_sim/hruby_sim_stack_calc.c +10 -0
- data/ext/hruby_sim/hruby_sim_tree_calc.c +36 -9
- data/ext/hruby_sim/hruby_sim_vcd.c +18 -14
- data/lib/HDLRuby/hdr_samples/arith_bench.rb +92 -0
- data/lib/HDLRuby/hdr_samples/constant_prop_bench.rb +58 -0
- data/lib/HDLRuby/hdrcc.rb +15 -6
- data/lib/HDLRuby/hruby_bstr.rb +15 -3
- data/lib/HDLRuby/hruby_high.rb +8 -4
- data/lib/HDLRuby/hruby_low.rb +14 -5
- data/lib/HDLRuby/hruby_low2c.rb +180 -69
- data/lib/HDLRuby/hruby_low_without_connection.rb +6 -2
- data/lib/HDLRuby/hruby_rcsim.rb +25 -15
- data/lib/HDLRuby/hruby_rsim.rb +63 -13
- data/lib/HDLRuby/hruby_rsim_mute.rb +35 -0
- data/lib/HDLRuby/hruby_rsim_vcd.rb +3 -3
- data/lib/HDLRuby/hruby_values.rb +19 -2
- data/lib/HDLRuby/hruby_verilog.rb +67 -17
- data/lib/HDLRuby/std/fsm.rb +3 -3
- data/lib/HDLRuby/version.rb +1 -1
- metadata +6 -2
@@ -0,0 +1,35 @@
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1
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+
require "HDLRuby/hruby_rsim"
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2
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+
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3
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+
##
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4
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# Library for enhancing the Ruby simulator with VCD support
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5
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#
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6
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########################################################################
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7
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module HDLRuby::High
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8
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9
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##
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10
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+
# Enhance the system type class with VCD support.
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11
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+
class SystemT
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12
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+
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13
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+
## Initializes the displayer for generating a vcd on +vcdout+
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14
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def show_init(vcdout)
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15
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end
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16
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+
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17
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## Displays the time.
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18
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def show_time
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19
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end
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20
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+
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21
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## Displays the value of signal +sig+.
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22
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def show_signal(sig)
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23
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end
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+
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25
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## Displays value +val+.
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26
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# NOTE: for now displays on the standard output and NOT the vcd.
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27
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def show_value(val)
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28
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end
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29
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+
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## Displays string +str+.
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def show_string(str)
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32
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end
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end
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+
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35
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end
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@@ -440,7 +440,7 @@ module HDLRuby::High
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440
440
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w.statement.show_hierarchy(vcdout)
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441
441
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end
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442
442
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# Recurse on the default if any.
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443
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-
self.default.show_hierarchy(vcdout)
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443
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+
self.default.show_hierarchy(vcdout) if self.default
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444
444
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end
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445
445
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446
446
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## Gets the VCD variables with their long name.
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@@ -450,7 +450,7 @@ module HDLRuby::High
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450
450
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w.statement.get_vars_with_fullname(vars_with_fullname)
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451
451
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end
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452
452
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# Recurse on the default if any.
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453
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-
self.default.get_vars_with_fullname(vars_with_fullname)
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453
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+
self.default.get_vars_with_fullname(vars_with_fullname) if self.default
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454
454
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return vars_with_fullname
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455
455
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end
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456
456
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@@ -461,7 +461,7 @@ module HDLRuby::High
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461
461
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w.statement.get_vars_with_idstr(vars_with_idstr)
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462
462
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end
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463
463
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# Recurse on the default if any.
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464
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-
self.default.get_vars_with_idstr(vars_with_idstr)
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464
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+
self.default.get_vars_with_idstr(vars_with_idstr) if self.default
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465
465
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return vars_with_idstr
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466
466
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end
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467
467
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end
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data/lib/HDLRuby/hruby_values.rb
CHANGED
@@ -34,7 +34,6 @@ module HDLRuby
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34
34
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:==, :!=, :<, :>, :<=, :>=, :<=> ].
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35
35
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each do |op|
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36
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define_method(op) do |val|
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37
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-
# puts "op=#{op} value=#{value}"
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38
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# Ensures val is computable.
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39
38
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unless val.to_value? then
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40
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# Not computable, use the former method that generates
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@@ -45,6 +44,7 @@ module HDLRuby
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45
44
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if self.content.is_a?(Numeric) && val.content.is_a?(BitString)
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46
45
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if val.content.specified? then
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47
46
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res_content = self.content.send(op,val.content.to_i)
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47
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+
# puts "op=#{op} self.content=#{self.content} val.content=#{val.content.to_i} res_content=#{res_content}"
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48
48
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else
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49
49
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res_content =
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50
50
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BitString.new(self.content).send(op,val.content)
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@@ -52,7 +52,7 @@ module HDLRuby
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52
52
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else
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53
53
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# Generate the resulting content.
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54
54
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res_content = self.content.send(op,val.content)
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55
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-
# puts "op=#{op} self.content=#{self.content} (#{self.content.
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55
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+
# puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})" if op == :^
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56
56
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end
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57
57
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res_type = self.type.resolve(val.type)
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58
58
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# # Adjust the result content size.
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@@ -374,6 +374,23 @@ module HDLRuby
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374
374
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return other,self.content
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375
375
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end
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376
376
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377
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+
# Hash-map comparison of values.
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378
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+
# Also use in simulation engines to know if a signal changed.
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379
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+
def eql?(val)
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380
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+
if self.content.is_a?(Numeric) then
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381
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+
return self.content == val if val.is_a?(Numeric)
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382
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+
return self.content == val.content if val.content.is_a?(Numeric)
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383
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+
return false unless val.content.specified?
|
384
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+
return self.content == val.content.to_i
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385
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+
else
|
386
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+
return self.content.to_i == val if val.is_a?(Numeric)
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387
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+
return self.content.eql?(val.content) unless val.content.is_a?(Numeric)
|
388
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+
return false if self.content.specified?
|
389
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+
return self.content.to_i == val.content
|
390
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+
end
|
391
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+
end
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392
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+
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393
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+
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377
394
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# Tell if the value is zero.
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378
395
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def zero?
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379
396
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return false unless @content
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@@ -1524,7 +1524,14 @@ module HDLRuby::Low
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1524
1524
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# Converts the system to Verilog code.
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1525
1525
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def to_verilog
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1526
1526
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# Outputs the first and second choices (choice (0) and choice (1)).
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1527
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-
return "#{self.select.to_verilog} == 1 #{self.operator} #{self.get_choice(0).to_verilog} : #{self.get_choice(1).to_verilog}"
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1527
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+
# return "#{self.select.to_verilog} == 1 #{self.operator} #{self.get_choice(0).to_verilog} : #{self.get_choice(1).to_verilog}"
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1528
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+
res = ""
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1529
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+
sels = self.select.to_verilog
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1530
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+
@choices[0..-2].each_with_index do |choice,i|
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1531
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res << "#{sels} == #{i} ? #{choice.to_verilog} : "
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1532
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+
end
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1533
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+
res << @choices[-1].to_verilog
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1534
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+
return res
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1528
1535
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end
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1529
1536
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end
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1530
1537
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@@ -1534,18 +1541,36 @@ module HDLRuby::Low
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1534
1541
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# Converts the system to Verilog code.
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1535
1542
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# If it is bit, it is b, and if it is int, it is represented by d. (Example: 4'b0000, 32'd1)
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1536
1543
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def to_verilog(unknown = nil)
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1537
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-
if self.type.base.name.to_s == "bit"
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1538
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-
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1539
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-
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1540
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-
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1541
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-
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1542
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-
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1543
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-
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1544
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+
# if self.type.base.name.to_s == "bit"
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1545
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+
# if self.type.unsigned? then
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1546
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+
# # return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
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1547
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+
# return "#{self.type.width}'b#{self.content.to_verilog}"
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1548
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+
# elsif self.type.name.to_s == "integer"
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1549
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+
# str = self.content.to_verilog
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1550
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+
# if str[0] == "-" then
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1551
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# # Negative value.
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1552
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# return "-#{self.type.range.first + 1}'d#{str[1..-1]}"
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1553
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+
# else
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1554
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+
# return "#{self.type.range.first + 1}'d#{str}"
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1555
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+
# end
|
1556
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+
# end
|
1557
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+
# return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
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1558
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+
if self.content.is_a?(Numeric) then
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1559
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+
if self.content < 0 then
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1560
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# str = (2**self.type.width + self.content).to_s(2)
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1561
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str = self.content.to_s(2)
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1562
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+
str = "0" * (self.type.width-str.length+1) + str[1..-1]
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1563
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return "-#{self.type.width}'b#{str}"
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else
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1545
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-
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1565
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+
str = self.content.to_s(2)
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1566
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str = "0" * (self.type.width-str.length) + str
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1567
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return "#{self.type.width}'b#{str}"
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1546
1568
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end
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1569
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# return "#{self.type.width}'b#{str}"
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1570
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else
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1571
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+
str = self.content.to_verilog
|
1572
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+
return "#{str.length}'b#{str}"
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1547
1573
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end
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1548
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-
return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
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1549
1574
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end
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1550
1575
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# How to use when simply obtaining the width
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1551
1576
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def to_getrange
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@@ -1602,7 +1627,6 @@ module HDLRuby::Low
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1602
1627
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1603
1628
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result = " " * spc # Indented based on space_count.
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1604
1629
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|
1605
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-
result = ""
|
1606
1630
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result << "case(#{self.value.to_verilog})\n"
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1607
1631
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1608
1632
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# n the case statement, each branch is partitioned by when. Process each time when.
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@@ -1611,18 +1635,19 @@ module HDLRuby::Low
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1611
1635
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result << " " * (spc+3) + "#{whens.match.to_verilog}: "
|
1612
1636
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|
1613
1637
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if whens.statement.each_statement.count >= 1 then
|
1614
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-
result << whens.statement.to_verilog(spc+3)
|
1638
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+
result << whens.statement.to_verilog(spc+3) << "\n"
|
1615
1639
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else
|
1616
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-
result << "
|
1640
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+
result << ";\n"
|
1617
1641
|
end
|
1618
1642
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end
|
1619
1643
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if self.default then
|
1644
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+
result << " " * (spc+3) + "default: "
|
1620
1645
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if self.default.each_statement.count >= 1 then
|
1621
1646
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result << self.default.each_statement.map do |stmnt|
|
1622
1647
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stmnt.to_verilog(spc+3)
|
1623
|
-
end.join("\n")
|
1648
|
+
end.join("\n") << "\n"
|
1624
1649
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else
|
1625
|
-
result << "
|
1650
|
+
result << ";\n"
|
1626
1651
|
end
|
1627
1652
|
end
|
1628
1653
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result << " " * spc + "endcase\n" # Conclusion.
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@@ -2032,6 +2057,9 @@ module HDLRuby::Low
|
|
2032
2057
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# Generate content code.
|
2033
2058
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codeC = ""
|
2034
2059
|
|
2060
|
+
# Arrays to initialize.
|
2061
|
+
arrays_to_init = []
|
2062
|
+
|
2035
2063
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# Declare "inner".
|
2036
2064
|
self.each_inner do |inner|
|
2037
2065
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if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
|
@@ -2050,8 +2078,14 @@ module HDLRuby::Low
|
|
2050
2078
|
codeC << " #{inner.type.to_verilog}#{inner.to_verilog}"
|
2051
2079
|
end
|
2052
2080
|
if inner.value then
|
2053
|
-
|
2054
|
-
|
2081
|
+
val = inner.value
|
2082
|
+
val = val.child while val.is_a?(Cast)
|
2083
|
+
if val.is_a?(Concat) then
|
2084
|
+
arrays_to_init << [inner,val]
|
2085
|
+
else
|
2086
|
+
# There is an initial value.
|
2087
|
+
codeC << " = #{inner.value.to_verilog}"
|
2088
|
+
end
|
2055
2089
|
end
|
2056
2090
|
codeC << ";\n"
|
2057
2091
|
end
|
@@ -2192,6 +2226,22 @@ module HDLRuby::Low
|
|
2192
2226
|
|
2193
2227
|
end
|
2194
2228
|
|
2229
|
+
# Generate the code for the initialization of the arrays.
|
2230
|
+
if arrays_to_init.any? then
|
2231
|
+
codeC << " initial begin\n"
|
2232
|
+
arrays_to_init.each do |(sig,val)|
|
2233
|
+
val.each_expression.with_index do |expr,i|
|
2234
|
+
# Initialization, therefore maybe no cast required...
|
2235
|
+
# if sig.value.is_a?(Cast) then
|
2236
|
+
# expr = Cast.new(sig.value.type,expr.clone)
|
2237
|
+
# end
|
2238
|
+
codeC << " ";
|
2239
|
+
codeC << "#{sig.to_verilog}[#{i}]=#{expr.to_verilog};\n"
|
2240
|
+
end
|
2241
|
+
end
|
2242
|
+
codeC << " end\n"
|
2243
|
+
end
|
2244
|
+
|
2195
2245
|
# Conclusion.
|
2196
2246
|
codeC << "\nendmodule"
|
2197
2247
|
|
data/lib/HDLRuby/std/fsm.rb
CHANGED
@@ -120,10 +120,10 @@ module HDLRuby::High::Std
|
|
120
120
|
|
121
121
|
# Enters the current system
|
122
122
|
HDLRuby::High.cur_system.open do
|
123
|
-
sub do
|
123
|
+
# sub do
|
124
124
|
HDLRuby::High.space_push(namespace)
|
125
125
|
# Execute the instantiation block
|
126
|
-
return_value =HDLRuby::High.top_user.instance_exec(&ruby_block)
|
126
|
+
return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
|
127
127
|
|
128
128
|
# Expands the extra state processing so that al all the
|
129
129
|
# parts of the state machine are in par (clear synthesis).
|
@@ -311,7 +311,7 @@ module HDLRuby::High::Std
|
|
311
311
|
end
|
312
312
|
|
313
313
|
HDLRuby::High.space_pop
|
314
|
-
end
|
314
|
+
# end
|
315
315
|
end
|
316
316
|
|
317
317
|
return return_value
|
data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: HDLRuby
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 2.11.
|
4
|
+
version: 2.11.8
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Lovic Gauthier
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date: 2022-10
|
11
|
+
date: 2022-11-10 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|
@@ -70,6 +70,7 @@ files:
|
|
70
70
|
- ext/hruby_sim/hruby_sim_calc.c
|
71
71
|
- ext/hruby_sim/hruby_sim_core.c
|
72
72
|
- ext/hruby_sim/hruby_sim_list.c
|
73
|
+
- ext/hruby_sim/hruby_sim_mute.c
|
73
74
|
- ext/hruby_sim/hruby_sim_stack_calc.c
|
74
75
|
- ext/hruby_sim/hruby_sim_stack_calc.c.sav
|
75
76
|
- ext/hruby_sim/hruby_sim_tree_calc.c
|
@@ -96,11 +97,13 @@ files:
|
|
96
97
|
- lib/HDLRuby/hdr_samples/addsub.rb
|
97
98
|
- lib/HDLRuby/hdr_samples/addsubz.rb
|
98
99
|
- lib/HDLRuby/hdr_samples/alu.rb
|
100
|
+
- lib/HDLRuby/hdr_samples/arith_bench.rb
|
99
101
|
- lib/HDLRuby/hdr_samples/bstr_bench.rb
|
100
102
|
- lib/HDLRuby/hdr_samples/calculator.rb
|
101
103
|
- lib/HDLRuby/hdr_samples/case_bench.rb
|
102
104
|
- lib/HDLRuby/hdr_samples/comparison_bench.rb
|
103
105
|
- lib/HDLRuby/hdr_samples/constant_in_function.rb
|
106
|
+
- lib/HDLRuby/hdr_samples/constant_prop_bench.rb
|
104
107
|
- lib/HDLRuby/hdr_samples/counter_bench.rb
|
105
108
|
- lib/HDLRuby/hdr_samples/counter_dff_bench.rb
|
106
109
|
- lib/HDLRuby/hdr_samples/dff.rb
|
@@ -286,6 +289,7 @@ files:
|
|
286
289
|
- lib/HDLRuby/hruby_low_without_select.rb
|
287
290
|
- lib/HDLRuby/hruby_rcsim.rb
|
288
291
|
- lib/HDLRuby/hruby_rsim.rb
|
292
|
+
- lib/HDLRuby/hruby_rsim_mute.rb
|
289
293
|
- lib/HDLRuby/hruby_rsim_vcd.rb
|
290
294
|
- lib/HDLRuby/hruby_serializer.rb
|
291
295
|
- lib/HDLRuby/hruby_tools.rb
|