HDLRuby 2.11.5 → 2.11.8

data/lib/HDLRuby/hruby_rsim_mute.rb

@@ -0,0 +1,35 @@
+require "HDLRuby/hruby_rsim"
+
+##
+# Library for enhancing the Ruby simulator with VCD support
+#
+########################################################################
+module HDLRuby::High
+
+    ##
+    # Enhance the system type class with VCD support.
+    class SystemT
+
+        ## Initializes the displayer for generating a vcd on +vcdout+
+        def show_init(vcdout)
+        end
+
+        ## Displays the time.
+        def show_time
+        end
+
+        ## Displays the value of signal +sig+.
+        def show_signal(sig)
+        end
+
+        ## Displays value +val+.
+        #  NOTE: for now displays on the standard output and NOT the vcd.
+        def show_value(val)
+        end
+
+        ## Displays string +str+.
+        def show_string(str)
+        end
+    end
+
+end

data/lib/HDLRuby/hruby_rsim_vcd.rb

@@ -440,7 +440,7 @@ module HDLRuby::High
                 w.statement.show_hierarchy(vcdout)
             end
             # Recurse on the default if any.
-            self.default.show_hierarchy(vcdout)
+            self.default.show_hierarchy(vcdout) if self.default
         end
 
         ## Gets the VCD variables with their long name.
@@ -450,7 +450,7 @@ module HDLRuby::High
                 w.statement.get_vars_with_fullname(vars_with_fullname)
             end
             # Recurse on the default if any.
-            self.default.get_vars_with_fullname(vars_with_fullname)
+            self.default.get_vars_with_fullname(vars_with_fullname) if self.default
             return vars_with_fullname
         end
 
@@ -461,7 +461,7 @@ module HDLRuby::High
                 w.statement.get_vars_with_idstr(vars_with_idstr)
             end
             # Recurse on the default if any.
-            self.default.get_vars_with_idstr(vars_with_idstr)
+            self.default.get_vars_with_idstr(vars_with_idstr) if self.default
             return vars_with_idstr
         end
     end

data/lib/HDLRuby/hruby_values.rb

@@ -34,7 +34,6 @@ module HDLRuby
           :==, :!=, :<, :>, :<=, :>=, :<=>  ].
           each do |op|
             define_method(op) do |val|
-                # puts "op=#{op} value=#{value}"
                 # Ensures val is computable.
                 unless val.to_value? then
                     # Not computable, use the former method that generates
@@ -45,6 +44,7 @@ module HDLRuby
                 if self.content.is_a?(Numeric) && val.content.is_a?(BitString)
                     if val.content.specified? then
                         res_content = self.content.send(op,val.content.to_i)
+                        # puts "op=#{op} self.content=#{self.content} val.content=#{val.content.to_i} res_content=#{res_content}"
                     else
                         res_content = 
                             BitString.new(self.content).send(op,val.content)
@@ -52,7 +52,7 @@ module HDLRuby
                 else
                     # Generate the resulting content.
                     res_content = self.content.send(op,val.content)
-                    # puts "op=#{op} self.content=#{self.content} (#{self.content.class}) val.content=#{val.content} (#{val.content.class}) res_content=#{res_content} (#{res_content.class})"
+                    # puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})" if op == :^
                 end
                 res_type = self.type.resolve(val.type)
                 # # Adjust the result content size.
@@ -374,6 +374,23 @@ module HDLRuby
             return other,self.content
         end
 
+        # Hash-map comparison of values.
+        # Also use in simulation engines to know if a signal changed.
+        def eql?(val)
+            if self.content.is_a?(Numeric) then
+                return self.content == val if val.is_a?(Numeric)
+                return self.content == val.content if val.content.is_a?(Numeric)
+                return false unless val.content.specified?
+                return self.content == val.content.to_i
+            else
+                return self.content.to_i == val if val.is_a?(Numeric)
+                return self.content.eql?(val.content) unless val.content.is_a?(Numeric)
+                return false if self.content.specified?
+                return self.content.to_i == val.content
+            end
+        end
+
+
         # Tell if the value is zero.
         def zero?
             return false unless @content

data/lib/HDLRuby/hruby_verilog.rb

@@ -1524,7 +1524,14 @@ module HDLRuby::Low
         # Converts the system to Verilog code.
         def to_verilog
             # Outputs the first and second choices (choice (0) and choice (1)).
-            return "#{self.select.to_verilog} == 1 #{self.operator} #{self.get_choice(0).to_verilog} : #{self.get_choice(1).to_verilog}"
+            # return "#{self.select.to_verilog} == 1 #{self.operator} #{self.get_choice(0).to_verilog} : #{self.get_choice(1).to_verilog}"
+            res = ""
+            sels = self.select.to_verilog
+            @choices[0..-2].each_with_index do |choice,i|
+                res << "#{sels} == #{i} ? #{choice.to_verilog} : "
+            end
+            res << @choices[-1].to_verilog
+            return res
         end
     end
 
@@ -1534,18 +1541,36 @@ module HDLRuby::Low
         # Converts the system to Verilog code.
         # If it is bit, it is b, and if it is int, it is represented by d. (Example: 4'b0000, 32'd1)
         def to_verilog(unknown = nil)
-            if self.type.base.name.to_s == "bit"
-                return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
-            elsif self.type.name.to_s == "integer"
-                str = self.content.to_verilog
-                if str[0] == "-" then
-                    # Negative value.
-                    return "-#{self.type.range.first + 1}'d#{str[1..-1]}"
+            # if self.type.base.name.to_s == "bit"
+            # if self.type.unsigned? then
+            #     # return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
+            #     return "#{self.type.width}'b#{self.content.to_verilog}"
+            # elsif self.type.name.to_s == "integer"
+            #     str = self.content.to_verilog
+            #     if str[0] == "-" then
+            #         # Negative value.
+            #         return "-#{self.type.range.first + 1}'d#{str[1..-1]}"
+            #     else
+            #         return "#{self.type.range.first + 1}'d#{str}"
+            #     end
+            # end
+            # return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
+            if self.content.is_a?(Numeric) then
+                if self.content < 0 then
+                    # str = (2**self.type.width + self.content).to_s(2)
+                    str = self.content.to_s(2)
+                    str = "0" * (self.type.width-str.length+1) + str[1..-1]
+                    return "-#{self.type.width}'b#{str}"
                 else
-                    return "#{self.type.range.first + 1}'d#{str}"
+                    str = self.content.to_s(2)
+                    str = "0" * (self.type.width-str.length) + str
+                    return "#{self.type.width}'b#{str}"
                 end
+                # return "#{self.type.width}'b#{str}"
+            else
+                str = self.content.to_verilog
+                return "#{str.length}'b#{str}"
             end
-            return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
         end
         # How to use when simply obtaining the width
         def to_getrange
@@ -1602,7 +1627,6 @@ module HDLRuby::Low
 
             result = " " * spc # Indented based on space_count.
 
-            result = ""
             result << "case(#{self.value.to_verilog})\n"
 
             # n the case statement, each branch is partitioned by when. Process each time when.
@@ -1611,18 +1635,19 @@ module HDLRuby::Low
                 result << " " * (spc+3) + "#{whens.match.to_verilog}: "
 
                 if whens.statement.each_statement.count >= 1 then
-                    result << whens.statement.to_verilog(spc+3)
+                    result << whens.statement.to_verilog(spc+3) << "\n"
                 else
-                    result << "\n"
+                    result << ";\n"
                 end
             end
             if self.default then
+                result << " " * (spc+3) + "default: "
                 if self.default.each_statement.count >= 1 then
                     result << self.default.each_statement.map do |stmnt|
                         stmnt.to_verilog(spc+3)
-                    end.join("\n")
+                    end.join("\n") << "\n"
                 else
-                    result << "\n"
+                    result << ";\n"
                 end
             end
             result << " " * spc + "endcase\n" # Conclusion.
@@ -2032,6 +2057,9 @@ module HDLRuby::Low
             # Generate content code.
             codeC = ""
 
+            # Arrays to initialize.
+            arrays_to_init = []
+
             # Declare "inner".
             self.each_inner do |inner|
                 if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
@@ -2050,8 +2078,14 @@ module HDLRuby::Low
                     codeC << " #{inner.type.to_verilog}#{inner.to_verilog}"
                 end
                 if inner.value then
-                    # There is an initial value.
-                    codeC << " = #{inner.value.to_verilog}"
+                    val = inner.value
+                    val = val.child while val.is_a?(Cast)
+                    if val.is_a?(Concat) then
+                        arrays_to_init << [inner,val]
+                    else
+                        # There is an initial value.
+                        codeC << " = #{inner.value.to_verilog}"
+                    end
                 end
                 codeC << ";\n"
             end
@@ -2192,6 +2226,22 @@ module HDLRuby::Low
 
             end
 
+            # Generate the code for the initialization of the arrays.
+            if arrays_to_init.any? then
+                codeC << "   initial begin\n"
+                arrays_to_init.each do |(sig,val)|
+                    val.each_expression.with_index do |expr,i|
+                        # Initialization, therefore maybe no cast required...
+                        # if sig.value.is_a?(Cast) then
+                        #     expr = Cast.new(sig.value.type,expr.clone)
+                        # end
+                        codeC << "      ";
+                        codeC << "#{sig.to_verilog}[#{i}]=#{expr.to_verilog};\n"
+                    end
+                end
+                codeC << "   end\n"
+            end
+
             # Conclusion.
             codeC << "\nendmodule"
 

data/lib/HDLRuby/std/fsm.rb

@@ -120,10 +120,10 @@ module HDLRuby::High::Std
 
             # Enters the current system
             HDLRuby::High.cur_system.open do
-                sub do
+                # sub do
                     HDLRuby::High.space_push(namespace)
                     # Execute the instantiation block
-                    return_value =HDLRuby::High.top_user.instance_exec(&ruby_block)
+                    return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
 
                     # Expands the extra state processing so that al all the
                     # parts of the state machine are in par (clear synthesis).
@@ -311,7 +311,7 @@ module HDLRuby::High::Std
                     end
 
                     HDLRuby::High.space_pop
-                end
+                # end
             end
 
             return return_value

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.11.5"
+  VERSION = "2.11.8"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.11.5
+  version: 2.11.8
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire:
 bindir: exe
 cert_chain: []
-date: 2022-10-14 00:00:00.000000000 Z
+date: 2022-11-10 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -70,6 +70,7 @@ files:
 - ext/hruby_sim/hruby_sim_calc.c
 - ext/hruby_sim/hruby_sim_core.c
 - ext/hruby_sim/hruby_sim_list.c
+- ext/hruby_sim/hruby_sim_mute.c
 - ext/hruby_sim/hruby_sim_stack_calc.c
 - ext/hruby_sim/hruby_sim_stack_calc.c.sav
 - ext/hruby_sim/hruby_sim_tree_calc.c
@@ -96,11 +97,13 @@ files:
 - lib/HDLRuby/hdr_samples/addsub.rb
 - lib/HDLRuby/hdr_samples/addsubz.rb
 - lib/HDLRuby/hdr_samples/alu.rb
+- lib/HDLRuby/hdr_samples/arith_bench.rb
 - lib/HDLRuby/hdr_samples/bstr_bench.rb
 - lib/HDLRuby/hdr_samples/calculator.rb
 - lib/HDLRuby/hdr_samples/case_bench.rb
 - lib/HDLRuby/hdr_samples/comparison_bench.rb
 - lib/HDLRuby/hdr_samples/constant_in_function.rb
+- lib/HDLRuby/hdr_samples/constant_prop_bench.rb
 - lib/HDLRuby/hdr_samples/counter_bench.rb
 - lib/HDLRuby/hdr_samples/counter_dff_bench.rb
 - lib/HDLRuby/hdr_samples/dff.rb
@@ -286,6 +289,7 @@ files:
 - lib/HDLRuby/hruby_low_without_select.rb
 - lib/HDLRuby/hruby_rcsim.rb
 - lib/HDLRuby/hruby_rsim.rb
+- lib/HDLRuby/hruby_rsim_mute.rb
 - lib/HDLRuby/hruby_rsim_vcd.rb
 - lib/HDLRuby/hruby_serializer.rb
 - lib/HDLRuby/hruby_tools.rb