HDLRuby 2.11.3 → 2.11.4

checksums.yaml

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data/README.md

@@ -1949,15 +1949,19 @@ There are two kinds of such statements:
       !10.ns
    ```
 
- - The `repeat` statements: such a statement takes as argument a time value and a block. The execution of the block is repeated until the delay that is given by the time value argument expires.  For example, the following code executes repeatedly the inversion of the `clk` signal every 10 nanoseconds for 10 seconds (i.e., it simulates a clock signal for 10 seconds):
+ - The `repeat` statements: such a statement takes as argument a number of iteration and a block. The execution of the block is repeated the given number times.  For example, the following code executes 10 times the inversion of the `clk` signal every 10 nanoseconds:
 
    ```ruby
-      repeat(10.s) do 
+      repeat(10) do 
          !10.ns
          clk <= ~clk
       end
    ```
 
+__Note:__
+
+   This statement is not synthesizable and therefore can only be used in timed behaviors.
+
 ### Parallel and sequential execution
 
 Time behaviors are by default sequential, but they can include both parallel and

data/ext/hruby_sim/hruby_rcsim_build.c

@@ -430,6 +430,27 @@ VALUE rcsim_make_timeWait(VALUE mod, VALUE unitV, VALUE delayV) {
     return res;
 }
 
+/* Creating a time repeat C object. */
+VALUE rcsim_make_timeRepeat(VALUE mod, VALUE numberV, VALUE statementV) {
+    // printf("rcsim_make_timeRepeat\n"); fflush(stdout);
+    /* Allocates the time repeat. */
+    TimeRepeat timeRepeat = (TimeRepeat)malloc(sizeof(TimeRepeatS));
+    // printf("timeRepeat=%p\n",timeRepeat); fflush(stdout);
+    /* Set it up. */
+    timeRepeat->kind = TIME_REPEAT;
+    /* Get and set the number of repeatition. */
+    long long number;
+    number = NUM2LL(numberV);
+    // printf("number=%lld\n",number); fflush(stdout);
+    timeRepeat->number = number;
+    /* Get and set the statement. */
+    value_to_rcsim(StatementS,statementV,timeRepeat->statement);
+    /* Returns the C time wait embedded into a ruby VALUE. */
+    VALUE res;
+    rcsim_to_value(TimeRepeatS,timeRepeat,res);
+    return res;
+}
+
 
 /* Creating a time terminate C object. */
 VALUE rcsim_make_timeTerminate(VALUE mod) {
@@ -447,19 +468,19 @@ VALUE rcsim_make_timeTerminate(VALUE mod) {
 
 
 /* Creating a hardware if C object. */
-VALUE rcsim_make_hif(VALUE mod, VALUE condition, VALUE yes, VALUE no) {
+VALUE rcsim_make_hif(VALUE mod, VALUE conditionV, VALUE yesV, VALUE noV) {
     // printf("rcsim_make_hif\n");
     /* Allocates the hardware if. */
     HIf hif = (HIf)malloc(sizeof(HIfS));
     // printf("hif=%p\n",hif);
     /* Set it up. */
     hif->kind = HIF;
-    value_to_rcsim(ExpressionS,condition,hif->condition);
-    value_to_rcsim(StatementS,yes,hif->yes);
-    if (TYPE(no) == T_NIL)
+    value_to_rcsim(ExpressionS,conditionV,hif->condition);
+    value_to_rcsim(StatementS,yesV,hif->yes);
+    if (TYPE(noV) == T_NIL)
         hif->no = NULL;
     else
-        value_to_rcsim(StatementS,no,hif->no);
+        value_to_rcsim(StatementS,noV,hif->no);
     hif->num_noifs = 0;
     hif->noconds = NULL;
     hif->nostmnts = NULL;
@@ -471,21 +492,21 @@ VALUE rcsim_make_hif(VALUE mod, VALUE condition, VALUE yes, VALUE no) {
 
 
 /* Creating a hardware case C object. */
-VALUE rcsim_make_hcase(VALUE mod, VALUE value, VALUE defolt) {
+VALUE rcsim_make_hcase(VALUE mod, VALUE valueV, VALUE defoltV) {
     // printf("rcsim_make_hcase\n");
     /* Allocates the hardware case. */
     HCase hcase = (HCase)malloc(sizeof(HCaseS));
     // printf("hcase=%p\n",hcase);
     /* Set it up. */
     hcase->kind = HCASE;
-    value_to_rcsim(ExpressionS,value,hcase->value);
+    value_to_rcsim(ExpressionS,valueV,hcase->value);
     hcase->num_whens = 0;
     hcase->matches = NULL;
     hcase->stmnts = NULL;
-    if (TYPE(defolt) == T_NIL)
+    if (TYPE(defoltV) == T_NIL)
         hcase->defolt = NULL;
     else
-        value_to_rcsim(StatementS,defolt,hcase->defolt);
+        value_to_rcsim(StatementS,defoltV,hcase->defolt);
     /* Returns the C hardware case embedded into a ruby VALUE. */
     VALUE res;
     rcsim_to_value(HCaseS,hcase,res);
@@ -494,7 +515,7 @@ VALUE rcsim_make_hcase(VALUE mod, VALUE value, VALUE defolt) {
 
 
 /* Creating a block C object. */
-VALUE rcsim_make_block(VALUE mod, VALUE mode) {
+VALUE rcsim_make_block(VALUE mod, VALUE modeV) {
     // printf("rcsim_make_block\n");
     /* Allocates the block. */
     Block block = (Block)malloc(sizeof(BlockS));
@@ -507,7 +528,7 @@ VALUE rcsim_make_block(VALUE mod, VALUE mode) {
     block->inners = NULL;
     block->num_stmnts = 0;
     block->stmnts = NULL;
-    block->mode = SYM2ID(mode) == id_PAR ? PAR : SEQ;
+    block->mode = SYM2ID(modeV) == id_PAR ? PAR : SEQ;
     /* Returns the C block embedded into a ruby VALUE. */
     VALUE res;
     rcsim_to_value(BlockS,block,res);
@@ -1373,6 +1394,7 @@ void Init_hruby_sim() {
     rb_define_singleton_method(mod,"rcsim_make_transmit",rcsim_make_transmit,2);
     rb_define_singleton_method(mod,"rcsim_make_print",rcsim_make_print,0);
     rb_define_singleton_method(mod,"rcsim_make_timeWait",rcsim_make_timeWait,2);
+    rb_define_singleton_method(mod,"rcsim_make_timeRepeat",rcsim_make_timeRepeat,2);
     rb_define_singleton_method(mod,"rcsim_make_timeTerminate",rcsim_make_timeTerminate,0);
     rb_define_singleton_method(mod,"rcsim_make_hif",rcsim_make_hif,3);
     rb_define_singleton_method(mod,"rcsim_make_hcase",rcsim_make_hcase,2);

data/ext/hruby_sim/hruby_sim.h

@@ -28,6 +28,7 @@ typedef struct PrintS_ PrintS;
 typedef struct HIfS_ HIfS;
 typedef struct HCaseS_ HCaseS;
 typedef struct TimeWaitS_ TimeWaitS;
+typedef struct TimeRepeatS_ TimeRepeatS;
 typedef struct TimeTerminateS_ TimeTerminateS;
 typedef struct ExpressionS_ ExpressionS;
 typedef struct UnaryS_ UnaryS;
@@ -63,6 +64,7 @@ typedef struct PrintS_* Print;
 typedef struct HIfS_* HIf;
 typedef struct HCaseS_* HCase;
 typedef struct TimeWaitS_* TimeWait;
+typedef struct TimeRepeatS_* TimeRepeat;
 typedef struct TimeTerminateS_* TimeTerminate;
 typedef struct ExpressionS_* Expression;
 typedef struct UnaryS_* Unary;
@@ -89,7 +91,8 @@ typedef enum {
 #endif
     OBJECT, SYSTEMT, SIGNALI, SCOPE, BEHAVIOR, SYSTEMI, CODE, BLOCK, EVENT,
 #ifdef RCSIM
-    /* Statements */  TRANSMIT, PRINT, HIF, HCASE, TIME_WAIT, TIME_TERMINATE,
+    /* Statements */  TRANSMIT, PRINT, HIF, HCASE, 
+                      TIME_WAIT, TIME_REPEAT, TIME_TERMINATE,
     /* Expressions */ UNARY, BINARY, SELECT, CONCAT, CAST,
     /* References */  REF_OBJECT, REF_INDEX, REF_RANGE, REF_CONCAT,
     /* Non-hardware*/ STRINGE,
@@ -670,6 +673,13 @@ typedef struct TimeWaitS_ {
     unsigned long long delay; /* The delay to wait in pico seconds. */
 } TimeWaitS;
 
+/** The C model of a time repeat statement. */
+typedef struct TimeRepeatS_ {
+    Kind kind;          /* The kind of object. */
+    long long number;   /* The number of interations, negative means infinity. */
+    Statement statement;/* The statement to execute in loop. */
+} TimeRepeatS;
+
 /** The C model of a time terminate statement. */
 typedef struct TimeTerminateS_ {
     Kind kind;          /* The kind of object. */

data/ext/hruby_sim/hruby_sim_tree_calc.c

@@ -358,6 +358,20 @@ void execute_statement(Statement stmnt, int mode, Behavior behavior) {
                 hw_wait(delay,behavior);
                 break;
             }
+        case TIME_REPEAT:
+            {
+                TimeRepeat rep = (TimeRepeat)stmnt;
+                if (rep->number>=0) {
+                    for(long long i=0; i<rep->number; ++i) {
+                        execute_statement(rep->statement,mode,behavior);
+                    }
+                } else {
+                    for(;;) {
+                        execute_statement(rep->statement,mode,behavior);
+                    }
+                }
+                break;
+            }
         case BLOCK:
             {
                 Block block = (Block)stmnt;

data/lib/HDLRuby/hdr_samples/repeat_bench.rb

@@ -0,0 +1,48 @@
+# A simple D-FF
+system :dff do
+    input  :d, :clk, :rst
+    output :q
+
+    (q <= d & ~rst).at(clk.posedge)
+end
+
+# A benchmark for the dff using repeat.
+system :dff_bench do
+    inner :d, :clk, :rst
+    inner :q
+
+    dff(:my_dff).(d,clk,rst,q)
+
+    timed do
+        clk <= 0
+        rst <= 0
+        d   <= _z
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= _z
+        !10.ns
+        clk <= 0
+        rst <= 1
+        d   <= _z
+        !10.ns
+        clk <= 1
+        rst <= 1
+        d   <= _z
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 1
+        !10.ns
+        clk <= 1
+        rst <= 0
+        !10.ns
+        repeat(100) do
+            clk <= 0
+            d <= ~d
+            !10.ns
+            clk <= 1
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hruby_high.rb

@@ -2682,10 +2682,10 @@ module HDLRuby::High
 
         # Converts the repeat statement to HDLRuby::Low.
         def to_low
-            # return HDLRuby::Low::TimeRepeat.new(self.statement.to_low,
+            # timeRepeatL = HDLRuby::Low::TimeRepeat.new(self.statement.to_low,
             #                                     self.delay.to_low)
-            timeRepeatL = HDLRuby::Low::TimeRepeat.new(self.statement.to_low,
-                                                self.delay.to_low)
+            timeRepeatL = HDLRuby::Low::TimeRepeat.new(self.number,
+                                                       self.statement.to_low)
             # # For debugging: set the source high object 
             # timeRepeatL.properties[:low2high] = self.hdr_id
             # self.properties[:high2low] = timeRepeatL
@@ -4233,15 +4233,20 @@ module HDLRuby::High
             self.add_statement(TimeWait.new(delay))
         end
 
-        # Adds a loop until +delay+ statement in the block in +mode+ whose
+        # # Adds a loop until +delay+ statement in the block in +mode+ whose
+        # # loop content is built using +ruby_block+.
+        # def repeat(delay, mode = nil, &ruby_block)
+        # Adds a +number+ times loop statement in the block in +mode+ whose
         # loop content is built using +ruby_block+.
-        def repeat(delay, mode = nil, &ruby_block)
+        # NOTE: if +number+ is negative, the number of iteration is infinite.
+        def repeat(number = -1, mode = nil, &ruby_block)
             # Ensure there is a block.
             ruby_block = proc {} unless block_given?
             # Build the content block.
             content = High.make_block(mode,&ruby_block)
             # Create and add the statement.
-            self.add_statement(TimeRepeat.new(content,delay))
+            # self.add_statement(TimeRepeat.new(content,delay))
+            self.add_statement(TimeRepeat.new(number,content))
         end
 
         # Converts the time block to HDLRuby::Low.

data/lib/HDLRuby/hruby_low.rb

@@ -4042,15 +4042,20 @@ module HDLRuby::Low
     ## 
     # Describes a timed loop statement: not synthesizable!
     class TimeRepeat < Statement
-        # The delay until the loop is repeated
-        attr_reader :delay
+        # # The delay until the loop is repeated
+        # attr_reader :delay
+        # The number of interrations.
+        attr_reader :number
 
         # The statement to execute.
         attr_reader :statement
 
-        # Creates a new timed loop statement execute in a loop +statement+ until
-        # +delay+ has passed.
-        def initialize(statement,delay)
+        # # Creates a new timed loop statement execute in a loop +statement+ until
+        # # +delay+ has passed.
+        # def initialize(statement,delay)
+        # Creates a new timed loop statement execute in a loop +statement+ 
+        # +number+ times (negative means inifinity).
+        def initialize(number,statement)
             # Check and set the statement.
             unless statement.is_a?(Statement)
                 raise AnyError,
@@ -4061,13 +4066,15 @@ module HDLRuby::Low
             # And set its parent.
             statement.parent = self
 
-            # Check and set the delay.
-            unless delay.is_a?(Delay)
-                raise AnyError, "Invalid class for a delay: #{delay.class}."
-            end
-            @delay = delay
-            # And set its parent.
-            delay.parent = self
+            # # Check and set the delay.
+            # unless delay.is_a?(Delay)
+            #     raise AnyError, "Invalid class for a delay: #{delay.class}."
+            # end
+            # @delay = delay
+            # Check and set the number.
+            @number = number.to_i
+            # # And set its parent.
+            # delay.parent = self
         end
 
         # Iterates over each object deeply.
@@ -4080,26 +4087,29 @@ module HDLRuby::Low
             ruby_block.call(self)
             # Then apply on the statement.
             self.statement.each_deep(&ruby_block)
-            # Then apply on the delay.
-            self.delay.each_deep(&ruby_block)
+            # # Then apply on the delay.
+            # self.delay.each_deep(&ruby_block)
         end
 
         # Comparison for hash: structural comparison.
         def eql?(obj)
             return false unless obj.is_a?(TimeRepeat)
-            return false unless @delay.eql?(obj.delay)
+            # return false unless @delay.eql?(obj.delay)
+            return false unless @number.eql?(obj.number)
             return false unless @statement.eql?(obj.statement)
             return true
         end
 
         # Hash function.
         def hash
-            return [@delay,@statement].hash
+            # return [@delay,@statement].hash
+            return [@number,@statement].hash
         end
 
         # Clones the TimeRepeat (deeply)
         def clone
-            return TimeRepeat.new(@statement.clone,@delay.clone)
+            # return TimeRepeat.new(@statement.clone,@delay.clone)
+            return TimeRepeat.new(@statement.clone,@number)
         end
 
         # Iterates over the expression children if any.

data/lib/HDLRuby/hruby_low2c.rb

@@ -1803,20 +1803,39 @@ module HDLRuby::Low
     ## Extends the TimeRepeat class with generation of C text.
     class TimeRepeat
 
+        # # Generates the C text of the equivalent HDLRuby code.
+        # # +level+ is the hierachical level of the object.
+        # # def to_c(level = 0)
+        # def to_c(res,level = 0)
+        #     # The resulting string.
+        #     # res = " " * level*3
+        #     res << " " * level*3
+        #     # Generate an infinite loop executing the block and waiting.
+        #     res << "for(;;) {\n"
+        #     # res << "#{self.statement.to_c(level+1)}\n"
+        #     self.statement.to_c(res,level+1)
+        #     res << "\n"
+        #     res << " " * (level+1)*3
+        #     res << Low2C.wait_code(self,level)
+        #     # Return the resulting string.
+        #     return res
+        # end
+
         # Generates the C text of the equivalent HDLRuby code.
         # +level+ is the hierachical level of the object.
         # def to_c(level = 0)
         def to_c(res,level = 0)
             # The resulting string.
-            # res = " " * level*3
             res << " " * level*3
-            # Generate an infinite loop executing the block and waiting.
-            res << "for(;;) {\n"
-            # res << "#{self.statement.to_c(level+1)}\n"
+            if (number < 0) then
+                # Generate an infinite loop executing the block and waiting.
+                res << "for(;;) {\n"
+            else
+                # Generate a finite loop.
+                res << "for(long long i = 0; i<#{self.number}; ++i) {\n"
+            end
             self.statement.to_c(res,level+1)
-            res << "\n"
-            res << " " * (level+1)*3
-            res << Low2C.wait_code(self,level)
+            res << " " * level*3 << "}\n"
             # Return the resulting string.
             return res
         end

data/lib/HDLRuby/hruby_rcsim.rb

@@ -654,7 +654,21 @@ module HDLRuby::High
     ## Extends the TimeRepeat class for hybrid Ruby-C simulation.
     class TimeRepeat
         attr_reader :rcstatement
-        # TODO!!!
+
+        # Generate the C description of the hardware case.
+        # +owner+ is a link to the C description of the owner behavior if any.
+        def to_rcsim(owner = nil)
+            # Create the timeRepeat C object.
+            @rcstatement = RCSim.rcsim_make_timeRepeat(self.number,
+                                                       self.statement.to_rcsim)
+
+            # Sets the owner if any.
+            if owner then
+                RCSim.rcsim_set_owner(@rcstatement,owner)
+            end
+
+            return @rcstatement
+        end
     end
 
 
@@ -670,7 +684,7 @@ module HDLRuby::High
 
             # Sets the owner if any.
             if owner then
-                RCSim.rcsim_set_block_owner(@rcstatement,owner)
+                RCSim.rcsim_set_owner(@rcstatement,owner)
             end
 
             # Add the inner signals.

data/lib/HDLRuby/hruby_rsim.rb

@@ -701,7 +701,16 @@ module HDLRuby::High
     ## 
     # Describes a timed loop statement: not synthesizable!
     class TimeRepeat
-        ## Deprecated
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurde on the statement.
+            self.statement.init_sim(systemT)
+        end
+
+        ## Executes the statement.
+        def execute(mode)
+            self.number.times { self.statement.execute(mode) }
+        end
     end
 
 

data/lib/HDLRuby/hruby_rsim_vcd.rb

@@ -179,6 +179,21 @@ module HDLRuby::High
         end
     end
 
+    ##
+    # Enhance the TimeRepeat class with VCD support.
+    class TimeRepeat
+        ## Shows the hierarchy of the variables.
+        def show_hierarchy(vcdout)
+            # Recurse on the statement.
+            self.statement.show_hierarchy(vcdout)
+        end
+
+        ## Gets the VCD variables with their long name.
+        def get_vars_with_fullname(vars_with_fullname = {})
+            # By default: nothing to do
+        end
+    end
+
     ##
     # Enhance the TimeWait class with VCD support.
     class TimeWait

data/lib/HDLRuby/hruby_verilog.rb

@@ -254,60 +254,62 @@ module HDLRuby::Low
 
 
 
-        # Extract and convert to verilog the TimeRepeat statements.
-        # NOTE: work only on the current level of the block (should be called
-        # through each_block_deep).
-        def repeat_to_verilog!
-            code = ""
-            # Gather the TimeRepeat statements.
-            repeats = self.each_statement.find_all { |st| st.is_a?(TimeRepeat) }
-            # Remove them from the block.
-            repeats.each { |st| self.delete_statement!(st) }
-            # Generate them separately in timed always processes.
-            repeats.each do |st|
-                code << "   always #{st.delay.to_verilog} begin\n"
-
-                # Perform "scheduling" using the method "flatten".
-                block = st.statement.flatten(st.statement.mode.to_s)
-
-                # Declaration of "inner" part within "always".
-                block.each_inner do |inner|
-                    # if regs.include?(inner.name) then
-                    if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
-                        code << "      reg"
-                    else
-                        code << "      wire"
-                    end
-
-                    # Variable has "base", but if there is width etc, it is not in "base".
-                    # It is determined by an if.
-                    if inner.type.base? 
-                        if inner.type.base.base? 
-                            code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
-                        else
-                            code << "#{inner.type.to_verilog} #{inner.to_verilog}"
-                        end
-                    else
-                        code << " #{inner.type.to_verilog}#{inner.to_verilog}"
-                    end
-                    if inner.value then
-                        # There is an initial value.
-                        code << " = #{inner.value.to_verilog}"
-                    end
-                    code << ";\n"
-                end
-
-                # Translate the block that finished scheduling.
-                block.each_statement do |statement|
-                    code  << "\n      #{statement.to_verilog(block.mode.to_s)}"
-                end
-
-                FmI.fm_par.clear()
-
-                code << "\n   end\n\n"
-            end
-            return code
-        end
+        # Deprecated with new TimeRepeat!
+        #
+        # # Extract and convert to verilog the TimeRepeat statements.
+        # # NOTE: work only on the current level of the block (should be called
+        # # through each_block_deep).
+        # def repeat_to_verilog!
+        #     code = ""
+        #     # Gather the TimeRepeat statements.
+        #     repeats = self.each_statement.find_all { |st| st.is_a?(TimeRepeat) }
+        #     # Remove them from the block.
+        #     repeats.each { |st| self.delete_statement!(st) }
+        #     # Generate them separately in timed always processes.
+        #     repeats.each do |st|
+        #         code << "   always #{st.delay.to_verilog} begin\n"
+
+        #         # Perform "scheduling" using the method "flatten".
+        #         block = st.statement.flatten(st.statement.mode.to_s)
+
+        #         # Declaration of "inner" part within "always".
+        #         block.each_inner do |inner|
+        #             # if regs.include?(inner.name) then
+        #             if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
+        #                 code << "      reg"
+        #             else
+        #                 code << "      wire"
+        #             end
+
+        #             # Variable has "base", but if there is width etc, it is not in "base".
+        #             # It is determined by an if.
+        #             if inner.type.base? 
+        #                 if inner.type.base.base? 
+        #                     code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
+        #                 else
+        #                     code << "#{inner.type.to_verilog} #{inner.to_verilog}"
+        #                 end
+        #             else
+        #                 code << " #{inner.type.to_verilog}#{inner.to_verilog}"
+        #             end
+        #             if inner.value then
+        #                 # There is an initial value.
+        #                 code << " = #{inner.value.to_verilog}"
+        #             end
+        #             code << ";\n"
+        #         end
+
+        #         # Translate the block that finished scheduling.
+        #         block.each_statement do |statement|
+        #             code  << "\n      #{statement.to_verilog(block.mode.to_s)}"
+        #         end
+
+        #         FmI.fm_par.clear()
+
+        #         code << "\n   end\n\n"
+        #     end
+        #     return code
+        # end
 
 
         # Process top layer of Block.
@@ -1814,6 +1816,15 @@ module HDLRuby::Low
         end
     end
 
+
+    # Generate verilog code for the TimeRepeat.
+    class TimeRepeat
+        def to_verilog(spc = 3)
+            result = (" " * spc) + "repeat(#{self.number})" + "\n"
+            result << self.statement.to_verilog(spc+3)
+        end
+    end
+
     # Those who disappeared.
     #class SystemI
     #class TypeTuple
@@ -2137,10 +2148,12 @@ module HDLRuby::Low
                 if behavior.block.is_a?(TimeBlock) then
                     # Tell it is a time behavior for further processing.
                     timebeh = true
-                    # Extract and translate the TimeRepeat separately.
-                    behavior.each_block_deep do |blk|
-                        codeC << blk.repeat_to_verilog!
-                    end
+                    # Deprecated with new TimeRepeat.
+                    #
+                    # # Extract and translate the TimeRepeat separately.
+                    # behavior.each_block_deep do |blk|
+                    #     codeC << blk.repeat_to_verilog!
+                    # end
                     # And generate an initial block.
                     codeC << "   initial "
                 else

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.11.3"
+  VERSION = "2.11.4"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.11.3
+  version: 2.11.4
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire:
 bindir: exe
 cert_chain: []
-date: 2022-10-10 00:00:00.000000000 Z
+date: 2022-10-11 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -148,6 +148,7 @@ files:
 - lib/HDLRuby/hdr_samples/ram.rb
 - lib/HDLRuby/hdr_samples/range_bench.rb
 - lib/HDLRuby/hdr_samples/register_with_code_bench.rb
+- lib/HDLRuby/hdr_samples/repeat_bench.rb
 - lib/HDLRuby/hdr_samples/rom.rb
 - lib/HDLRuby/hdr_samples/rom_nest.rb
 - lib/HDLRuby/hdr_samples/ruby_fir_hw.rb