HDLRuby 2.11.2 → 2.11.4

data/lib/HDLRuby/hruby_rcsim.rb

@@ -107,26 +107,32 @@ module HDLRuby::High
             #     rcsig = sig.to_rcsim(@rcsystemT)
             #     RCSim.rcsim_add_systemT_input(@rcsystemT,rcsig)
             # end
-            RCSim.rcsim_add_systemT_inputs(@rcsystemT,
-                                           self.each_input.map do |sig|
-                sig.to_rcsim(@rcsystemT)
-            end)
+            if self.each_input.any? then
+                RCSim.rcsim_add_systemT_inputs(@rcsystemT,
+                                               self.each_input.map do |sig|
+                    sig.to_rcsim(@rcsystemT)
+                end)
+            end
             # self.each_output do |sig|
             #     rcsig = sig.to_rcsim(@rcsystemT)
             #     RCSim.rcsim_add_systemT_output(@rcsystemT,rcsig)
             # end
-            RCSim.rcsim_add_systemT_outputs(@rcsystemT,
-                                            self.each_output.map do |sig|
-                sig.to_rcsim(@rcsystemT)
-            end)
+            if self.each_output.any? then
+                RCSim.rcsim_add_systemT_outputs(@rcsystemT,
+                                                self.each_output.map do |sig|
+                    sig.to_rcsim(@rcsystemT)
+                end)
+            end
             # self.each_inout do |sig|
             #     rcsig = sig.to_rcsim(@rcsystemT)
             #     RCSim.rcsim_add_systemT_inout(@rcsystemT,rcsig)
             # end
-            RCSim.rcsim_add_systemT_inouts(@rcsystemT,
-                                           self.each_inout.map do |sig|
-                sig.to_rcsim(@rcsystemT)
-            end)
+            if self.each_inout.any? then
+                RCSim.rcsim_add_systemT_inouts(@rcsystemT,
+                                               self.each_inout.map do |sig|
+                    sig.to_rcsim(@rcsystemT)
+                end)
+            end
             # Create and add the scope.
             RCSim.rcsim_set_systemT_scope(@rcsystemT,
                                           self.scope.to_rcsim(@rcsystemT))
@@ -170,44 +176,43 @@ module HDLRuby::High
             #     rcsig = sig.to_rcsim(@rcscope)
             #     RCSim.rcsim_add_scope_inner(@rcscope,rcsig)
             # end
-            RCSim.rcsim_add_scope_inners(@rcscope,self.each_inner.map do |sig|
-                # sig.to_rcsim(@rcscope)
-                sig.to_rcsim(subowner)
-            end)
+            if self.each_inner.any? then
+                RCSim.rcsim_add_scope_inners(@rcscope,self.each_inner.map do|sig|
+                    # sig.to_rcsim(@rcscope)
+                    sig.to_rcsim(subowner)
+                end)
+            end
             
             # Create and add the system instances.
             # self.each_systemI do |sys|
             #     rcsys = sys.to_rcsim(@rcscope)
             #     RCSim.rcsim_add_scope_systemI(@rcscope,rcsys)
             # end
-            RCSim.rcsim_add_scope_systemIs(@rcscope,
-                                           self.each_systemI.map do |sys|
-                # sys.to_rcsim(@rcscope)
-                sys.to_rcsim(subowner)
-            end)
+            if self.each_systemI.any? then
+                RCSim.rcsim_add_scope_systemIs(@rcscope,
+                                               self.each_systemI.map do |sys|
+                    # sys.to_rcsim(@rcscope)
+                    sys.to_rcsim(subowner)
+                end)
+            end
 
             # Create and add the behaviors.
-            # self.each_behavior do |beh|
-            #     rcbeh = beh.to_rcsim(@rcscope)
-            #     RCSim.rcsim_add_scope_behavior(@rcscope,rcbeh)
-            # end
-            RCSim.rcsim_add_scope_behaviors(@rcscope,
-                                            self.each_behavior.map do |beh|
-                # beh.to_rcsim(@rcscope)
-                beh.to_rcsim(subowner)
-            end)
+            if self.each_behavior.any? then
+                RCSim.rcsim_add_scope_behaviors(@rcscope,
+                                                self.each_behavior.map do |beh|
+                    # beh.to_rcsim(@rcscope)
+                    beh.to_rcsim(subowner)
+                end)
+            end
 
             # Create and add the connections.
-            # self.each_connection do |cnx|
-            #     rccnx = cnx.to_rcsim(@rcscope)
-            #     # Connections are actually converted to behaviors.
-            #     RCSim.rcsim_add_scope_behavior(@rcscope,rccnx)
-            # end
-            RCSim.rcsim_add_scope_behaviors(@rcscope, 
-                                            self.each_connection.map do |cxt|
-                # cxt.to_rcsim(@rcscope)
-                cxt.to_rcsim(subowner)
-            end)
+            if self.each_connection.any? then
+                RCSim.rcsim_add_scope_behaviors(@rcscope, 
+                                                self.each_connection.map do |cxt|
+                    # cxt.to_rcsim(@rcscope)
+                    cxt.to_rcsim(subowner)
+                end)
+            end
 
             # Create and add the codes.
             # TODO!!
@@ -217,10 +222,12 @@ module HDLRuby::High
             #     rcsub = sub.to_rcsim(@rcscope)
             #     RCSim.rcsim_add_scope_scope(@rcscope,rcsub)
             # end
-            RCSim.rcsim_add_scope_scopes(@rcscope,self.each_scope.map do |sub|
-                # sub.to_rcsim(@rcscope)
-                sub.to_rcsim(subowner)
-            end)
+            if self.each_scope.any? then
+                RCSim.rcsim_add_scope_scopes(@rcscope,self.each_scope.map do|sub|
+                    # sub.to_rcsim(@rcscope)
+                    sub.to_rcsim(subowner)
+                end)
+            end
 
             return @rcscope
         end
@@ -349,11 +356,13 @@ module HDLRuby::High
             # self.each_event do |ev|
             #     RCSim.rcsim_add_behavior_event(@rcbehavior,ev.to_rcsim)
             # end
-            RCSim.rcsim_add_behavior_events(@rcbehavior,
-                                            self.each_event.map do |ev|
-                # puts "adding event: #{ev.ref.object.name}(#{ev.type})"
-                ev.to_rcsim(@rcbehavior)
-            end)
+            if self.each_event.any? then
+                RCSim.rcsim_add_behavior_events(@rcbehavior,
+                                                self.each_event.map do |ev|
+                    # puts "adding event: #{ev.ref.object.name}(#{ev.type})"
+                    ev.to_rcsim(@rcbehavior)
+                end)
+            end
 
             # Create and add the block.
             RCSim.rcsim_set_behavior_block(@rcbehavior,self.block.to_rcsim)
@@ -468,12 +477,15 @@ module HDLRuby::High
             #     rcsys = systemT.to_rcsim(@rcsystemI)
             #     RCSim.rcsim_add_systemI_systemT(@rcsystemI,rcsys)
             # end
-            RCSim.rcsim_add_systemI_systemTs(@rcsystemI,
-                                             self.each_systemT.select do |sys|
-                sys != self.systemT
-            end.map do |sys|
-                sys.to_rcsim(@rcsystemI)
-            end)
+            if self.each_systemI.any? then
+                RCSim.rcsim_add_systemI_systemTs(@rcsystemI,
+                                                 self.each_systemT.select do|sys|
+                    sys != self.systemT
+                end.map do |sys|
+                    # sys.to_rcsim(@rcsystemI)
+                    sys.to_rcsim(rcowner)
+                end)
+            end
 
             return @rcsystemI
         end
@@ -531,8 +543,10 @@ module HDLRuby::High
             # self.each_arg do |arg|
             #     RCSim.rcsim_add_print_arg(@rcstatement,arg.to_rcsim)
             # end
-            RCSim.rcsim_add_print_args(@rcstatement,
-                                       self.each_arg.map(&:to_rcsim))
+            if self.each_arg.any? then
+                RCSim.rcsim_add_print_args(@rcstatement,
+                                           self.each_arg.map(&:to_rcsim))
+            end
 
             return @rcstatement
         end
@@ -576,7 +590,9 @@ module HDLRuby::High
             # end
             rcsim_conds = self.each_noif.map {|cond,stmnt| cond.to_rcsim }
             rcsim_stmnts = self.each_noif.map {|cond,stmnt| stmnt.to_rcsim }
-            RCSim.rcsim_add_hif_noifs(@rcstatement,rcsim_conds,rcsim_stmnts)
+            if rcsim_conds.any? then
+                RCSim.rcsim_add_hif_noifs(@rcstatement,rcsim_conds,rcsim_stmnts)
+            end
 
             return @rcstatement
         end
@@ -605,7 +621,10 @@ module HDLRuby::High
             # end
             rcsim_matches = self.each_when.map {|wh| wh.match.to_rcsim }
             rcsim_stmnts = self.each_when.map {|wh| wh.statement.to_rcsim }
-            RCSim.rcsim_add_hcase_whens(@rcstatement,rcsim_matches,rcsim_stmnts)
+            if rcsim_matches.any? then
+                RCSim.rcsim_add_hcase_whens(@rcstatement,rcsim_matches,
+                                            rcsim_stmnts)
+            end
 
             return @rcstatement
         end
@@ -635,7 +654,21 @@ module HDLRuby::High
     ## Extends the TimeRepeat class for hybrid Ruby-C simulation.
     class TimeRepeat
         attr_reader :rcstatement
-        # TODO!!!
+
+        # Generate the C description of the hardware case.
+        # +owner+ is a link to the C description of the owner behavior if any.
+        def to_rcsim(owner = nil)
+            # Create the timeRepeat C object.
+            @rcstatement = RCSim.rcsim_make_timeRepeat(self.number,
+                                                       self.statement.to_rcsim)
+
+            # Sets the owner if any.
+            if owner then
+                RCSim.rcsim_set_owner(@rcstatement,owner)
+            end
+
+            return @rcstatement
+        end
     end
 
 
@@ -651,26 +684,30 @@ module HDLRuby::High
 
             # Sets the owner if any.
             if owner then
-                RCSim.rcsim_set_block_owner(@rcstatement,owner)
+                RCSim.rcsim_set_owner(@rcstatement,owner)
             end
 
             # Add the inner signals.
             # self.each_inner do |inner|
             #     RCSim.rcsim_add_block_inner(@rcstatement,inner.to_rcsim(@rcstatement))
             # end
-            RCSim.rcsim_add_block_inners(@rcstatement,
-                                         self.each_inner.map do |sig|
-                sig.to_rcsim(@rcstatement)
-            end)
+            if self.each_inner.any? then
+                RCSim.rcsim_add_block_inners(@rcstatement,
+                                             self.each_inner.map do |sig|
+                    sig.to_rcsim(@rcstatement)
+                end)
+            end
 
             # Add the statements.
             # self.each_statement do |stmnt|
             #     RCSim.rcsim_add_block_statement(@rcstatement,stmnt.to_rcsim)
             # end
-            RCSim.rcsim_add_block_statements(@rcstatement,
-                                       self.each_statement.map do |stmnt|
-                stmnt.to_rcsim
-            end)
+            if self.each_statement.any? then
+                RCSim.rcsim_add_block_statements(@rcstatement,
+                                            self.each_statement.map do |stmnt|
+                    stmnt.to_rcsim
+                end)
+            end
 
             return @rcstatement
         end
@@ -710,7 +747,9 @@ module HDLRuby::High
                     rcevs << ev
                 end
             end
-            RCSim.rcsim_add_behavior_events(@rcbehavior,rcevs)
+            if rcevs.any? then
+                RCSim.rcsim_add_behavior_events(@rcbehavior,rcevs)
+            end
 
             # Create and set the block.
             rcblock = RCSim.rcsim_make_block(:par)
@@ -843,8 +882,10 @@ module HDLRuby::High
             # self.each_choice do |choice|
             #     rcsim_add_select_choice(rcexpression,choice.to_rcsim)
             # end
-            RCSim.rcsim_add_select_choices(rcexpression,
-                                     self.each_choice.map(&:to_rcsim))
+            if self.each_choice.any? then
+                RCSim.rcsim_add_select_choices(rcexpression,
+                                               self.each_choice.map(&:to_rcsim))
+            end
             
             return rcexpression
         end
@@ -865,8 +906,10 @@ module HDLRuby::High
             # self.each_expression do |expr|
             #     RCSim.rcsim_add_concat_expression(rcexpression,expr.to_rcsim)
             # end
-            RCSim.rcsim_add_concat_expressions(rcexpression,
+            if self.each_expression.any? then
+                RCSim.rcsim_add_concat_expressions(rcexpression,
                                          self.each_expression.map(&:to_rcsim))
+            end
             
             return rcexpression
         end
@@ -901,7 +944,9 @@ module HDLRuby::High
             # self.each_ref do |ref|
             #     RCSim.rcsim_add_refConcat_ref(rcref,ref.to_rcsim)
             # end
-            RCSim.rcsim_add_refConcat_refs(rcref,self.each_ref(&:to_rcsim))
+            if self.each_ref.any? then
+                RCSim.rcsim_add_refConcat_refs(rcref,self.each_ref(&:to_rcsim))
+            end
             
             return rcref
         end

data/lib/HDLRuby/hruby_rsim.rb

@@ -701,7 +701,16 @@ module HDLRuby::High
     ## 
     # Describes a timed loop statement: not synthesizable!
     class TimeRepeat
-        ## Deprecated
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurde on the statement.
+            self.statement.init_sim(systemT)
+        end
+
+        ## Executes the statement.
+        def execute(mode)
+            self.number.times { self.statement.execute(mode) }
+        end
     end
 
 

data/lib/HDLRuby/hruby_rsim_vcd.rb

@@ -179,6 +179,21 @@ module HDLRuby::High
         end
     end
 
+    ##
+    # Enhance the TimeRepeat class with VCD support.
+    class TimeRepeat
+        ## Shows the hierarchy of the variables.
+        def show_hierarchy(vcdout)
+            # Recurse on the statement.
+            self.statement.show_hierarchy(vcdout)
+        end
+
+        ## Gets the VCD variables with their long name.
+        def get_vars_with_fullname(vars_with_fullname = {})
+            # By default: nothing to do
+        end
+    end
+
     ##
     # Enhance the TimeWait class with VCD support.
     class TimeWait

data/lib/HDLRuby/hruby_verilog.rb

@@ -254,60 +254,62 @@ module HDLRuby::Low
 
 
 
-        # Extract and convert to verilog the TimeRepeat statements.
-        # NOTE: work only on the current level of the block (should be called
-        # through each_block_deep).
-        def repeat_to_verilog!
-            code = ""
-            # Gather the TimeRepeat statements.
-            repeats = self.each_statement.find_all { |st| st.is_a?(TimeRepeat) }
-            # Remove them from the block.
-            repeats.each { |st| self.delete_statement!(st) }
-            # Generate them separately in timed always processes.
-            repeats.each do |st|
-                code << "   always #{st.delay.to_verilog} begin\n"
-
-                # Perform "scheduling" using the method "flatten".
-                block = st.statement.flatten(st.statement.mode.to_s)
-
-                # Declaration of "inner" part within "always".
-                block.each_inner do |inner|
-                    # if regs.include?(inner.name) then
-                    if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
-                        code << "      reg"
-                    else
-                        code << "      wire"
-                    end
-
-                    # Variable has "base", but if there is width etc, it is not in "base".
-                    # It is determined by an if.
-                    if inner.type.base? 
-                        if inner.type.base.base? 
-                            code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
-                        else
-                            code << "#{inner.type.to_verilog} #{inner.to_verilog}"
-                        end
-                    else
-                        code << " #{inner.type.to_verilog}#{inner.to_verilog}"
-                    end
-                    if inner.value then
-                        # There is an initial value.
-                        code << " = #{inner.value.to_verilog}"
-                    end
-                    code << ";\n"
-                end
-
-                # Translate the block that finished scheduling.
-                block.each_statement do |statement|
-                    code  << "\n      #{statement.to_verilog(block.mode.to_s)}"
-                end
-
-                FmI.fm_par.clear()
-
-                code << "\n   end\n\n"
-            end
-            return code
-        end
+        # Deprecated with new TimeRepeat!
+        #
+        # # Extract and convert to verilog the TimeRepeat statements.
+        # # NOTE: work only on the current level of the block (should be called
+        # # through each_block_deep).
+        # def repeat_to_verilog!
+        #     code = ""
+        #     # Gather the TimeRepeat statements.
+        #     repeats = self.each_statement.find_all { |st| st.is_a?(TimeRepeat) }
+        #     # Remove them from the block.
+        #     repeats.each { |st| self.delete_statement!(st) }
+        #     # Generate them separately in timed always processes.
+        #     repeats.each do |st|
+        #         code << "   always #{st.delay.to_verilog} begin\n"
+
+        #         # Perform "scheduling" using the method "flatten".
+        #         block = st.statement.flatten(st.statement.mode.to_s)
+
+        #         # Declaration of "inner" part within "always".
+        #         block.each_inner do |inner|
+        #             # if regs.include?(inner.name) then
+        #             if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
+        #                 code << "      reg"
+        #             else
+        #                 code << "      wire"
+        #             end
+
+        #             # Variable has "base", but if there is width etc, it is not in "base".
+        #             # It is determined by an if.
+        #             if inner.type.base? 
+        #                 if inner.type.base.base? 
+        #                     code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
+        #                 else
+        #                     code << "#{inner.type.to_verilog} #{inner.to_verilog}"
+        #                 end
+        #             else
+        #                 code << " #{inner.type.to_verilog}#{inner.to_verilog}"
+        #             end
+        #             if inner.value then
+        #                 # There is an initial value.
+        #                 code << " = #{inner.value.to_verilog}"
+        #             end
+        #             code << ";\n"
+        #         end
+
+        #         # Translate the block that finished scheduling.
+        #         block.each_statement do |statement|
+        #             code  << "\n      #{statement.to_verilog(block.mode.to_s)}"
+        #         end
+
+        #         FmI.fm_par.clear()
+
+        #         code << "\n   end\n\n"
+        #     end
+        #     return code
+        # end
 
 
         # Process top layer of Block.
@@ -1814,6 +1816,15 @@ module HDLRuby::Low
         end
     end
 
+
+    # Generate verilog code for the TimeRepeat.
+    class TimeRepeat
+        def to_verilog(spc = 3)
+            result = (" " * spc) + "repeat(#{self.number})" + "\n"
+            result << self.statement.to_verilog(spc+3)
+        end
+    end
+
     # Those who disappeared.
     #class SystemI
     #class TypeTuple
@@ -2137,10 +2148,12 @@ module HDLRuby::Low
                 if behavior.block.is_a?(TimeBlock) then
                     # Tell it is a time behavior for further processing.
                     timebeh = true
-                    # Extract and translate the TimeRepeat separately.
-                    behavior.each_block_deep do |blk|
-                        codeC << blk.repeat_to_verilog!
-                    end
+                    # Deprecated with new TimeRepeat.
+                    #
+                    # # Extract and translate the TimeRepeat separately.
+                    # behavior.each_block_deep do |blk|
+                    #     codeC << blk.repeat_to_verilog!
+                    # end
                     # And generate an initial block.
                     codeC << "   initial "
                 else

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.11.2"
+  VERSION = "2.11.4"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.11.2
+  version: 2.11.4
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire:
 bindir: exe
 cert_chain: []
-date: 2022-10-01 00:00:00.000000000 Z
+date: 2022-10-11 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -148,6 +148,7 @@ files:
 - lib/HDLRuby/hdr_samples/ram.rb
 - lib/HDLRuby/hdr_samples/range_bench.rb
 - lib/HDLRuby/hdr_samples/register_with_code_bench.rb
+- lib/HDLRuby/hdr_samples/repeat_bench.rb
 - lib/HDLRuby/hdr_samples/rom.rb
 - lib/HDLRuby/hdr_samples/rom_nest.rb
 - lib/HDLRuby/hdr_samples/ruby_fir_hw.rb