HDLRuby 2.11.0 → 2.11.3

data/ext/hruby_sim/hruby_sim_calc.c

@@ -5,9 +5,9 @@
 #include <limits.h>
 #include "hruby_sim.h"
 
-#ifndef alloca
-#define alloca(x)  __builtin_alloca(x)
-#endif
+// #ifndef alloca
+// #define alloca(x)  __builtin_alloca(x)
+// #endif
 
 
 /**
@@ -147,7 +147,7 @@ Type get_type_signed() {
  *  @number the number of elements */
 Type make_type_vector(Type base, unsigned long long number) {
     /* Create the type. */
-    Type type = calloc(sizeof(TypeS),1);
+    Type type = calloc(1,sizeof(TypeS));
     type->base = type_width(base);
     type->number = number;
     type->flags = base->flags;
@@ -201,7 +201,7 @@ Value make_value(Type type, int numeric) {
     /* Compute the size in words of the data contained in the value. */
     unsigned long long width = type_width(type);
     /* Allocate the value. */
-    Value res = calloc(sizeof(ValueS),1);
+    Value res = calloc(1,sizeof(ValueS));
     /* Allocates the data of the value. */
     if (!numeric) {
         /* Allocate the bit string and fill it with u (undefined) by default. */
@@ -232,7 +232,7 @@ void resize_value(Value value, unsigned long long size) {
         /* Free the former data. */
         free(value->data_str);
         /* Reallocate it. */
-        value->data_str = calloc(sizeof(char),size*2);
+        value->data_str = calloc(size*2,sizeof(char));
         /* Update the size. */
         value->capacity = size*2;
     }
@@ -946,7 +946,7 @@ Value reduce_or_value_bitstring(Value src, Value dst) {
 
     /* Performs the reduce or. */
     unsigned long long count;
-    char res;
+    char res = 0;
     for(count = 0; count < width; ++count) {
         /* Performs the reduce or. */
         char d = src_data[count] - '0'; /* Get and convert to bit. */
@@ -2977,12 +2977,15 @@ Value concat_valueP(unsigned int num, int dir, Value dst, Value* values) {
 }
 Value concat_valueV(unsigned int num, int dir, Value dst, va_list args) {
     unsigned int i;
-    Value* values = alloca(num*sizeof(Value)); /* The values to concatenate. */
+    // Value* values = alloca(num*sizeof(Value)); /* The values to concatenate. */
+    Value* values = calloc(num,sizeof(Value)); /* The values to concatenate. */
     /* Copy the arguments to values for easier processing. */
     for(i=0; i<num; ++i) {
         values[i] = va_arg(args,Value);
     }
-    return concat_valueP(num,dir,dst,values);
+    Value res = concat_valueP(num,dir,dst,values);
+    free(values);
+    return res;
 }
 Value concat_value(unsigned int num, int dir, Value dst, ...) {
     va_list args;

data/ext/hruby_sim/hruby_sim_core.c

@@ -72,11 +72,13 @@ void register_timed_behavior(Behavior behavior) {
         if (cap_timed_behaviors == 0) {
             /* Need to create the array containing the timed behaviors. */
             cap_timed_behaviors = 5;
-            timed_behaviors = calloc(sizeof(Behavior),cap_timed_behaviors);
+            timed_behaviors = calloc(cap_timed_behaviors,sizeof(Behavior));
         } else {
             /* Need to increase the capacity. */
-            Behavior* behaviors = calloc(sizeof(Behavior),cap_timed_behaviors*2);
-            memcpy(timed_behaviors,behaviors,sizeof(Behavior)*cap_timed_behaviors);
+            Behavior* behaviors = calloc(cap_timed_behaviors*2,sizeof(Behavior));
+            // memcpy(behaviors,timed_behaviors,sizeof(Behavior)*cap_timed_behaviors);
+            memcpy(behaviors,timed_behaviors,sizeof(Behavior[cap_timed_behaviors]));
+            timed_behaviors = behaviors;
             cap_timed_behaviors *= 2;
         }
     }
@@ -92,11 +94,12 @@ void register_signal(SignalI signal) {
         if (cap_all_signals == 0) {
             /* Need to create the array containing the timed behaviors. */
             cap_all_signals = 100;
-            all_signals = calloc(sizeof(SignalI),cap_all_signals);
+            all_signals = calloc(cap_all_signals,sizeof(SignalI));
         } else {
             /* Need to increase the capacity. */
-            SignalI* new_signals = calloc(sizeof(SignalI),cap_all_signals*2);
-            memcpy(new_signals,all_signals,sizeof(SignalI)*cap_all_signals);
+            SignalI* new_signals = calloc(cap_all_signals*2,sizeof(SignalI));
+            // memcpy(new_signals,all_signals,sizeof(SignalI)*cap_all_signals);
+            memcpy(new_signals,all_signals,sizeof(SignalI[cap_all_signals]));
             cap_all_signals *= 2;
             all_signals=new_signals;
         }

data/ext/hruby_sim/hruby_value_pool.c

@@ -20,9 +20,10 @@ Value get_value() {
     if (pool_cap == 0) {
         /* First allocation. */
         pool_cap = 16;
-        pool_values = (Value*)malloc(pool_cap*sizeof(Value));
+        // pool_values = (Value*)malloc(pool_cap*sizeof(Value));
+        pool_values = (Value*)calloc(pool_cap,sizeof(Value));
         /* Allocate the new values. */
-        ValueS* new_values = (ValueS*)calloc(sizeof(ValueS),pool_cap);
+        ValueS* new_values = (ValueS*)calloc(pool_cap,sizeof(ValueS));
         /* Assign them to the pool. */
         unsigned int i;
         for(i=0; i<pool_cap; ++i) {
@@ -32,11 +33,16 @@ Value get_value() {
     else if (pool_pos == pool_cap) {
         /* Need to increase the pool capacity. */
         pool_cap = pool_cap * 2;
-        pool_values = (Value*)realloc(pool_values,pool_cap*sizeof(Value));
+        // pool_values = (Value*)realloc(pool_values,pool_cap*sizeof(Value));
+        pool_values = (Value*)realloc(pool_values,sizeof(Value[pool_cap]));
+        if (pool_values == NULL) {
+            perror("Internal error with the pool of values.");
+            exit(1);
+        }
         /* Allocate the new values. */
         /* Note: now pool_pos is the old pool_cap and is also the number
          * of new values to allocate. */
-        ValueS* new_values = (ValueS*)calloc(sizeof(ValueS),pool_pos);
+        ValueS* new_values = (ValueS*)calloc(pool_pos,sizeof(ValueS));
         /* Assign them to the pool. */
         unsigned int i;
         for(i=0; i<pool_pos; ++i) {

data/lib/HDLRuby/hruby_rcsim.rb

@@ -107,26 +107,32 @@ module HDLRuby::High
             #     rcsig = sig.to_rcsim(@rcsystemT)
             #     RCSim.rcsim_add_systemT_input(@rcsystemT,rcsig)
             # end
-            RCSim.rcsim_add_systemT_inputs(@rcsystemT,
-                                           self.each_input.map do |sig|
-                sig.to_rcsim(@rcsystemT)
-            end)
+            if self.each_input.any? then
+                RCSim.rcsim_add_systemT_inputs(@rcsystemT,
+                                               self.each_input.map do |sig|
+                    sig.to_rcsim(@rcsystemT)
+                end)
+            end
             # self.each_output do |sig|
             #     rcsig = sig.to_rcsim(@rcsystemT)
             #     RCSim.rcsim_add_systemT_output(@rcsystemT,rcsig)
             # end
-            RCSim.rcsim_add_systemT_outputs(@rcsystemT,
-                                            self.each_output.map do |sig|
-                sig.to_rcsim(@rcsystemT)
-            end)
+            if self.each_output.any? then
+                RCSim.rcsim_add_systemT_outputs(@rcsystemT,
+                                                self.each_output.map do |sig|
+                    sig.to_rcsim(@rcsystemT)
+                end)
+            end
             # self.each_inout do |sig|
             #     rcsig = sig.to_rcsim(@rcsystemT)
             #     RCSim.rcsim_add_systemT_inout(@rcsystemT,rcsig)
             # end
-            RCSim.rcsim_add_systemT_inouts(@rcsystemT,
-                                           self.each_inout.map do |sig|
-                sig.to_rcsim(@rcsystemT)
-            end)
+            if self.each_inout.any? then
+                RCSim.rcsim_add_systemT_inouts(@rcsystemT,
+                                               self.each_inout.map do |sig|
+                    sig.to_rcsim(@rcsystemT)
+                end)
+            end
             # Create and add the scope.
             RCSim.rcsim_set_systemT_scope(@rcsystemT,
                                           self.scope.to_rcsim(@rcsystemT))
@@ -170,44 +176,43 @@ module HDLRuby::High
             #     rcsig = sig.to_rcsim(@rcscope)
             #     RCSim.rcsim_add_scope_inner(@rcscope,rcsig)
             # end
-            RCSim.rcsim_add_scope_inners(@rcscope,self.each_inner.map do |sig|
-                # sig.to_rcsim(@rcscope)
-                sig.to_rcsim(subowner)
-            end)
+            if self.each_inner.any? then
+                RCSim.rcsim_add_scope_inners(@rcscope,self.each_inner.map do|sig|
+                    # sig.to_rcsim(@rcscope)
+                    sig.to_rcsim(subowner)
+                end)
+            end
             
             # Create and add the system instances.
             # self.each_systemI do |sys|
             #     rcsys = sys.to_rcsim(@rcscope)
             #     RCSim.rcsim_add_scope_systemI(@rcscope,rcsys)
             # end
-            RCSim.rcsim_add_scope_systemIs(@rcscope,
-                                           self.each_systemI.map do |sys|
-                # sys.to_rcsim(@rcscope)
-                sys.to_rcsim(subowner)
-            end)
+            if self.each_systemI.any? then
+                RCSim.rcsim_add_scope_systemIs(@rcscope,
+                                               self.each_systemI.map do |sys|
+                    # sys.to_rcsim(@rcscope)
+                    sys.to_rcsim(subowner)
+                end)
+            end
 
             # Create and add the behaviors.
-            # self.each_behavior do |beh|
-            #     rcbeh = beh.to_rcsim(@rcscope)
-            #     RCSim.rcsim_add_scope_behavior(@rcscope,rcbeh)
-            # end
-            RCSim.rcsim_add_scope_behaviors(@rcscope,
-                                            self.each_behavior.map do |beh|
-                # beh.to_rcsim(@rcscope)
-                beh.to_rcsim(subowner)
-            end)
+            if self.each_behavior.any? then
+                RCSim.rcsim_add_scope_behaviors(@rcscope,
+                                                self.each_behavior.map do |beh|
+                    # beh.to_rcsim(@rcscope)
+                    beh.to_rcsim(subowner)
+                end)
+            end
 
             # Create and add the connections.
-            # self.each_connection do |cnx|
-            #     rccnx = cnx.to_rcsim(@rcscope)
-            #     # Connections are actually converted to behaviors.
-            #     RCSim.rcsim_add_scope_behavior(@rcscope,rccnx)
-            # end
-            RCSim.rcsim_add_scope_behaviors(@rcscope, 
-                                            self.each_connection.map do |cxt|
-                # cxt.to_rcsim(@rcscope)
-                cxt.to_rcsim(subowner)
-            end)
+            if self.each_connection.any? then
+                RCSim.rcsim_add_scope_behaviors(@rcscope, 
+                                                self.each_connection.map do |cxt|
+                    # cxt.to_rcsim(@rcscope)
+                    cxt.to_rcsim(subowner)
+                end)
+            end
 
             # Create and add the codes.
             # TODO!!
@@ -217,10 +222,12 @@ module HDLRuby::High
             #     rcsub = sub.to_rcsim(@rcscope)
             #     RCSim.rcsim_add_scope_scope(@rcscope,rcsub)
             # end
-            RCSim.rcsim_add_scope_scopes(@rcscope,self.each_scope.map do |sub|
-                # sub.to_rcsim(@rcscope)
-                sub.to_rcsim(subowner)
-            end)
+            if self.each_scope.any? then
+                RCSim.rcsim_add_scope_scopes(@rcscope,self.each_scope.map do|sub|
+                    # sub.to_rcsim(@rcscope)
+                    sub.to_rcsim(subowner)
+                end)
+            end
 
             return @rcscope
         end
@@ -349,11 +356,13 @@ module HDLRuby::High
             # self.each_event do |ev|
             #     RCSim.rcsim_add_behavior_event(@rcbehavior,ev.to_rcsim)
             # end
-            RCSim.rcsim_add_behavior_events(@rcbehavior,
-                                            self.each_event.map do |ev|
-                # puts "adding event: #{ev.ref.object.name}(#{ev.type})"
-                ev.to_rcsim(@rcbehavior)
-            end)
+            if self.each_event.any? then
+                RCSim.rcsim_add_behavior_events(@rcbehavior,
+                                                self.each_event.map do |ev|
+                    # puts "adding event: #{ev.ref.object.name}(#{ev.type})"
+                    ev.to_rcsim(@rcbehavior)
+                end)
+            end
 
             # Create and add the block.
             RCSim.rcsim_set_behavior_block(@rcbehavior,self.block.to_rcsim)
@@ -468,12 +477,15 @@ module HDLRuby::High
             #     rcsys = systemT.to_rcsim(@rcsystemI)
             #     RCSim.rcsim_add_systemI_systemT(@rcsystemI,rcsys)
             # end
-            RCSim.rcsim_add_systemI_systemTs(@rcsystemI,
-                                             self.each_systemT.select do |sys|
-                sys != self.systemT
-            end.map do |sys|
-                sys.to_rcsim(@rcsystemI)
-            end)
+            if self.each_systemI.any? then
+                RCSim.rcsim_add_systemI_systemTs(@rcsystemI,
+                                                 self.each_systemT.select do|sys|
+                    sys != self.systemT
+                end.map do |sys|
+                    # sys.to_rcsim(@rcsystemI)
+                    sys.to_rcsim(rcowner)
+                end)
+            end
 
             return @rcsystemI
         end
@@ -531,8 +543,10 @@ module HDLRuby::High
             # self.each_arg do |arg|
             #     RCSim.rcsim_add_print_arg(@rcstatement,arg.to_rcsim)
             # end
-            RCSim.rcsim_add_print_args(@rcstatement,
-                                       self.each_arg.map(&:to_rcsim))
+            if self.each_arg.any? then
+                RCSim.rcsim_add_print_args(@rcstatement,
+                                           self.each_arg.map(&:to_rcsim))
+            end
 
             return @rcstatement
         end
@@ -576,7 +590,9 @@ module HDLRuby::High
             # end
             rcsim_conds = self.each_noif.map {|cond,stmnt| cond.to_rcsim }
             rcsim_stmnts = self.each_noif.map {|cond,stmnt| stmnt.to_rcsim }
-            RCSim.rcsim_add_hif_noifs(@rcstatement,rcsim_conds,rcsim_stmnts)
+            if rcsim_conds.any? then
+                RCSim.rcsim_add_hif_noifs(@rcstatement,rcsim_conds,rcsim_stmnts)
+            end
 
             return @rcstatement
         end
@@ -605,7 +621,10 @@ module HDLRuby::High
             # end
             rcsim_matches = self.each_when.map {|wh| wh.match.to_rcsim }
             rcsim_stmnts = self.each_when.map {|wh| wh.statement.to_rcsim }
-            RCSim.rcsim_add_hcase_whens(@rcstatement,rcsim_matches,rcsim_stmnts)
+            if rcsim_matches.any? then
+                RCSim.rcsim_add_hcase_whens(@rcstatement,rcsim_matches,
+                                            rcsim_stmnts)
+            end
 
             return @rcstatement
         end
@@ -658,19 +677,23 @@ module HDLRuby::High
             # self.each_inner do |inner|
             #     RCSim.rcsim_add_block_inner(@rcstatement,inner.to_rcsim(@rcstatement))
             # end
-            RCSim.rcsim_add_block_inners(@rcstatement,
-                                         self.each_inner.map do |sig|
-                sig.to_rcsim(@rcstatement)
-            end)
+            if self.each_inner.any? then
+                RCSim.rcsim_add_block_inners(@rcstatement,
+                                             self.each_inner.map do |sig|
+                    sig.to_rcsim(@rcstatement)
+                end)
+            end
 
             # Add the statements.
             # self.each_statement do |stmnt|
             #     RCSim.rcsim_add_block_statement(@rcstatement,stmnt.to_rcsim)
             # end
-            RCSim.rcsim_add_block_statements(@rcstatement,
-                                       self.each_statement.map do |stmnt|
-                stmnt.to_rcsim
-            end)
+            if self.each_statement.any? then
+                RCSim.rcsim_add_block_statements(@rcstatement,
+                                            self.each_statement.map do |stmnt|
+                    stmnt.to_rcsim
+                end)
+            end
 
             return @rcstatement
         end
@@ -710,7 +733,9 @@ module HDLRuby::High
                     rcevs << ev
                 end
             end
-            RCSim.rcsim_add_behavior_events(@rcbehavior,rcevs)
+            if rcevs.any? then
+                RCSim.rcsim_add_behavior_events(@rcbehavior,rcevs)
+            end
 
             # Create and set the block.
             rcblock = RCSim.rcsim_make_block(:par)
@@ -843,8 +868,10 @@ module HDLRuby::High
             # self.each_choice do |choice|
             #     rcsim_add_select_choice(rcexpression,choice.to_rcsim)
             # end
-            RCSim.rcsim_add_select_choices(rcexpression,
-                                     self.each_choice.map(&:to_rcsim))
+            if self.each_choice.any? then
+                RCSim.rcsim_add_select_choices(rcexpression,
+                                               self.each_choice.map(&:to_rcsim))
+            end
             
             return rcexpression
         end
@@ -865,8 +892,10 @@ module HDLRuby::High
             # self.each_expression do |expr|
             #     RCSim.rcsim_add_concat_expression(rcexpression,expr.to_rcsim)
             # end
-            RCSim.rcsim_add_concat_expressions(rcexpression,
+            if self.each_expression.any? then
+                RCSim.rcsim_add_concat_expressions(rcexpression,
                                          self.each_expression.map(&:to_rcsim))
+            end
             
             return rcexpression
         end
@@ -901,7 +930,9 @@ module HDLRuby::High
             # self.each_ref do |ref|
             #     RCSim.rcsim_add_refConcat_ref(rcref,ref.to_rcsim)
             # end
-            RCSim.rcsim_add_refConcat_refs(rcref,self.each_ref(&:to_rcsim))
+            if self.each_ref.any? then
+                RCSim.rcsim_add_refConcat_refs(rcref,self.each_ref(&:to_rcsim))
+            end
             
             return rcref
         end

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.11.0"
+  VERSION = "2.11.3"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.11.0
+  version: 2.11.3
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire:
 bindir: exe
 cert_chain: []
-date: 2022-09-23 00:00:00.000000000 Z
+date: 2022-10-10 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler