HDLRuby 2.1.6 → 2.2.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/HDLRuby/hruby_low_bool2select.rb +11 -0
- data/lib/HDLRuby/hruby_low_with_var.rb +15 -0
- data/lib/HDLRuby/hruby_low_without_select.rb +13 -0
- data/lib/HDLRuby/hruby_verilog.rb +27 -19
- data/lib/HDLRuby/version.rb +1 -1
- metadata +1 -1
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: e8f74ac40d2f3ddc8ec9eb5a17c8d48b091068288a4bdb37adad8008c9b29e78
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data.tar.gz: '084b85f61816a823c92b736e1d203274f3e1beb2b2278f240bee36218665afe7'
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: ef3418dda3d976fe68beb65a305c6163da94cdecf398ddd9bbc06786abc3c130b8df6ecd3a94064ecc0ffc64105a63838c455bd0709c3f64c83f2e40d7406a2b
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data.tar.gz: 8c9284a2c34be1f2e39b55cac6419ea858dd4972f9715bf2e39317bdcc4d7fcdcffae4d5c76ff3bbfabd77acd1a295a2cbba651568c569e144900e47814fc072
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@@ -119,6 +119,17 @@ module HDLRuby::Low
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end
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## Extends the TimeWait class with functionality for converting booleans
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# in assignments to select operators.
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class TimeWait
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# Converts booleans in assignments to select operators.
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def boolean_in_assign2select!
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# Nothing to do.
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return self
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end
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end
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## Extends the Block class with functionality for converting booleans
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# in assignments to select operators.
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class Block
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@@ -247,6 +247,21 @@ module HDLRuby::Low
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end
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## Extends the TimeBlock class with separation between signals and variables.
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class TimeBlock
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# Converts to a variable-compatible block where +upper+ is
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# the upper block if any.
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#
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# NOTE: the result is a new block.
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def with_var(upper = nil)
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# For the specific case of block, the conversion is not
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# done.
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return self
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end
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end
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## Extends the If class with separation between signals and variables.
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class If
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# Converts to a variable-compatible if where +upper+ is
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@@ -96,6 +96,19 @@ module HDLRuby::Low
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end
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end
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## Extends the TimeWait class with functionality for converting booleans
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# in assignments to select operators.
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class TimeWait
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# Extract the Select expressions.
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def extract_selects!
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# Nothing to extract.
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return []
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end
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end
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## Extends the Block class with functionality for converting select
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# expressions to case statements.
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class Block
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# Process top layer of Block.
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# Determine whether there is a block under block and convert it.
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def flatten(mode = nil)
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-
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if self.is_a?(TimeBlock) then
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new_block = TimeBlock.new(self.mode,"")
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else
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new_block = Block.new(self.mode,"") # A new block to store the converted statement.
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end
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list = [] # A list for confirming that variable declarations do not overlap.
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# Is block in the statement?
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@@ -1884,29 +1888,33 @@ class SystemT
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# Translation of behavior part (always).
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self.each_behavior do |behavior|
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if behavior.each_event.to_a.empty? then
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code << "*"
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if behavior.block.is_a?(TimeBlock) then
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code << " initial begin\n"
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else
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code << " always @( "
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# If there is no "always" condition, it is always @("*").
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if behavior.each_event.to_a.empty? then
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code << "*"
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else
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event = behavior.each_event.to_a
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event[0..-2].each do |event|
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# If "posedge" or "negedge" does not exist, the variable is set to condition.
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if (event.type.to_s != "posedge" && event.type.to_s != "negedge") then
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code << "#{event.ref.to_verilog}, "
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else
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# Otherwise, it outputs "psoedge" or "negedge" as a condition.
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code << "#{event.type.to_s} #{event.ref.to_verilog}, "
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end
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end
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# Since no comma is necessary at the end, we try not to separate commas separately at the end.
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if (event.last.type.to_s != "posedge" && event.last.type.to_s != "negedge") then
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code << "#{event.last.ref.to_verilog}"
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else
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code << "#{event.type.to_s} #{event.ref.to_verilog}, "
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code << "#{event.last.type.to_s} #{event.last.ref.to_verilog}"
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end
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end
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if (event.last.type.to_s != "posedge" && event.last.type.to_s != "negedge") then
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code << "#{event.last.ref.to_verilog}"
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else
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code << "#{event.last.type.to_s} #{event.last.ref.to_verilog}"
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end
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code << " ) begin\n"
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end
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code << " ) begin\n"
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# Perform "scheduling" using the method "flatten".
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block = behavior.block.flatten(behavior.block.mode.to_s)
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data/lib/HDLRuby/version.rb
CHANGED