GBRb 0.1.0 → 0.2.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.gitignore +0 -1
- data/README.md +9 -1
- data/bin/gbrb +3 -3
- data/doc/images/blargg_cpu.png +0 -0
- data/doc/images/cpu_01.png +0 -0
- data/doc/images/cpu_03.png +0 -0
- data/doc/images/cpu_04.png +0 -0
- data/doc/images/cpu_05.png +0 -0
- data/doc/images/cpu_06.png +0 -0
- data/doc/images/cpu_07.png +0 -0
- data/doc/images/cpu_08.png +0 -0
- data/doc/images/cpu_09.png +0 -0
- data/doc/images/cpu_10.png +0 -0
- data/doc/images/cpu_11.png +0 -0
- data/doc/images/nintendo_logo.png +0 -0
- data/doc/images/opus5.png +0 -0
- data/doc/images/test.gb.png +0 -0
- data/doc/images/ttt.png +0 -0
- data/lib/gbrb.rb +7 -0
- data/lib/gbrb/cartridge.rb +21 -8
- data/lib/gbrb/cartridge/cartridge.rb +187 -0
- data/lib/gbrb/cpu/concatenated_register.rb +1 -1
- data/lib/gbrb/cpu/z80.rb +575 -498
- data/lib/gbrb/gb.rb +102 -32
- data/lib/gbrb/graphics.rb +1 -1
- data/lib/gbrb/graphics/gpu.rb +38 -30
- data/lib/gbrb/graphics/mode_clock.rb +31 -30
- data/lib/gbrb/graphics/screen_client.rb +3 -2
- data/lib/gbrb/instruction_set.rb +16 -0
- data/lib/gbrb/instruction_set/arithmetic.rb +238 -0
- data/lib/gbrb/instruction_set/bitwise.rb +64 -0
- data/lib/gbrb/instruction_set/boolean.rb +61 -0
- data/lib/gbrb/instruction_set/call.rb +40 -0
- data/lib/gbrb/instruction_set/carry.rb +23 -0
- data/lib/gbrb/instruction_set/cpl.rb +12 -0
- data/lib/gbrb/instruction_set/daa.rb +33 -0
- data/lib/gbrb/instruction_set/instruction.rb +23 -0
- data/lib/gbrb/instruction_set/jump.rb +47 -0
- data/lib/gbrb/instruction_set/ld.rb +241 -0
- data/lib/gbrb/instruction_set/return.rb +43 -0
- data/lib/gbrb/instruction_set/rotate.rb +178 -0
- data/lib/gbrb/instruction_set/rst.rb +16 -0
- data/lib/gbrb/instruction_set/special.rb +37 -0
- data/lib/gbrb/instruction_set/stack.rb +34 -0
- data/lib/gbrb/instruction_set/swap.rb +32 -0
- data/lib/gbrb/mmu.rb +60 -35
- data/lib/gbrb/options.rb +54 -0
- data/lib/gbrb/timer.rb +114 -0
- data/lib/gbrb/version.rb +1 -1
- data/misc/dump_diff +133 -0
- data/perf/cpu_perf_spec.rb +2 -2
- data/spec/gbrb/cartridge/cartridge_spec.rb +19 -0
- data/spec/gbrb/cartridge/mbc1_spec.rb +83 -0
- data/spec/gbrb/cpu/z80_spec.rb +92 -2
- data/spec/gbrb/{cpu/instruction_spec.rb → instruction_set/arithmetic_spec.rb} +21 -100
- data/spec/gbrb/instruction_set/boolean_spec.rb +50 -0
- data/spec/gbrb/instruction_set/instruction_spec.rb +22 -0
- data/spec/gbrb/instruction_set/ld_spec.rb +21 -0
- data/spec/gbrb/instruction_set/special_spec.rb +22 -0
- data/spec/gbrb/mmu_spec.rb +1 -1
- data/spec/gbrb/timer_spec.rb +26 -0
- metadata +53 -9
- data/lib/gbrb/cpu/instruction.rb +0 -648
- data/spec/gbrb/cartridge_spec.rb +0 -19
- data/spec/gbrb/graphics/mode_clock_spec.rb +0 -82
@@ -0,0 +1,50 @@
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require_relative '../../spec_helper'
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require_relative '../../../lib/gbrb/instruction_set/boolean.rb'
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require_relative '../../../lib/gbrb/cpu/register.rb'
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module GBRb::InstructionSet
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describe And do
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it "sets the correct flags" do
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a = GBRb::CPU::Register.new 0x73
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b = GBRb::CPU::Register.new 0xd2
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world = double.as_null_object
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world.stub(:a).and_return(a)
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world.stub(:b).and_return(b)
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world.should_receive :clear_add_sub_flag
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world.should_receive :set_half_carry_flag
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world.should_receive :clear_carry_flag
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i = And.new :a, :b
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i.call world, nil
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end
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end
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describe Or do
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it "sets the correct flags" do
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a = GBRb::CPU::Register.new 0x81
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b = GBRb::CPU::Register.new 0xaf
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world = double.as_null_object
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world.stub(:a).and_return(a)
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world.stub(:b).and_return(b)
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world.should_receive :clear_add_sub_flag
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world.should_receive :clear_half_carry_flag
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world.should_receive :clear_carry_flag
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i= Or.new :a, :b
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i.call world, nil
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end
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end
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describe Xor do
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it "sets the correct flags" do
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a = GBRb::CPU::Register.new 0x81
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b = GBRb::CPU::Register.new 0xaf
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world = double.as_null_object
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world.stub(:a).and_return(a)
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world.stub(:b).and_return(b)
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world.should_receive :clear_add_sub_flag
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world.should_receive :clear_half_carry_flag
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world.should_receive :clear_carry_flag
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i= Xor.new :a, :b
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i.call world, nil
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end
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end
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end
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@@ -0,0 +1,22 @@
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require_relative '../../spec_helper'
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require_relative '../../../lib/gbrb/instruction_set/instruction.rb'
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module GBRb::InstructionSet
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describe Instruction do
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it "has a m time" do
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i = Instruction.new
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i.m.should be_true
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end
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it "has a t time" do
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i = Instruction.new
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i.t.should be_true
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end
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it "is callable" do
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i = Instruction.new
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world = double
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i.call world, nil
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end
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end
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end
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@@ -0,0 +1,21 @@
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require_relative '../../spec_helper'
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require_relative '../../../lib/gbrb/instruction_set/ld.rb'
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require_relative '../../../lib/gbrb/cpu/register.rb'
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module GBRb::InstructionSet
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describe Ld do
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it "does not set any flags" do
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b = GBRb::CPU::Register.new
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c = GBRb::CPU::Register.new 0x34
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world = double.as_null_object
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world.should_receive(:b).at_least(1).times.and_return(b)
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world.should_receive(:c).at_least(1).times.and_return(c)
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world.should_not_receive(:set_half_carry_flag)
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world.should_not_receive(:set_carry_flag)
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world.should_not_receive(:set_add_sub_flag)
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world.should_not_receive(:set_zero_flag)
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i = Ld.new :b, :c
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i.call world, nil
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end
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end
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end
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@@ -0,0 +1,22 @@
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require_relative '../../spec_helper'
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require_relative '../../../lib/gbrb/instruction_set/special.rb'
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module GBRb::InstructionSet
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describe EnableInterrupts do
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it "sets interrupts to enabled" do
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c = double
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c.should_receive(:interrupts=).with(:enabled).once
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ei = EnableInterrupts.new
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ei.call c
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end
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end
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describe DisableInterrupts do
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it "sets interrupts to disabled" do
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c = double
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c.should_receive(:interrupts=).with(:disabled).once
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di = DisableInterrupts.new
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di.call c
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end
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end
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end
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data/spec/gbrb/mmu_spec.rb
CHANGED
@@ -0,0 +1,26 @@
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require_relative '../spec_helper'
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require_relative '../../lib/gbrb/timer'
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module GBRb
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describe Timer do
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let(:t) { Timer.new }
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context "registers" do
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it "has a div counter" do
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t.div
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end
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it "has a counter counter" do
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t.tima
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end
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it "has a modulo register" do
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t.tma
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end
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it "has a control register" do
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t.tac
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end
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end
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end
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end
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metadata
CHANGED
@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: GBRb
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version: !ruby/object:Gem::Version
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version: 0.
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version: 0.2.0
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platform: ruby
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authors:
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- Casey Robinson
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2013-
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date: 2013-10-04 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: bundler
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@@ -83,15 +83,29 @@ files:
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- Rakefile
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- bin/display
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- bin/gbrb
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- doc/images/blargg_cpu.png
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- doc/images/cpu_01.png
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- doc/images/cpu_03.png
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- doc/images/cpu_04.png
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- doc/images/cpu_05.png
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- doc/images/cpu_06.png
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- doc/images/cpu_07.png
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- doc/images/cpu_08.png
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- doc/images/cpu_09.png
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- doc/images/cpu_10.png
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- doc/images/cpu_11.png
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- doc/images/nintendo_logo.png
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- doc/images/opus5.png
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- doc/images/test.gb.png
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- doc/images/ttt.png
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- gbrb.gemspec
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- lib/gbrb.rb
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- lib/gbrb/bios
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- lib/gbrb/cartridge.rb
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- lib/gbrb/cartridge/cartridge.rb
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- lib/gbrb/cpu.rb
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- lib/gbrb/cpu/concatenated_register.rb
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- lib/gbrb/cpu/flags_register.rb
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- lib/gbrb/cpu/instruction.rb
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- lib/gbrb/cpu/register.rb
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- lib/gbrb/cpu/register_ensemble.rb
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- lib/gbrb/cpu/z80.rb
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@@ -101,19 +115,44 @@ files:
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115
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- lib/gbrb/graphics/mode_clock.rb
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- lib/gbrb/graphics/screen_client.rb
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- lib/gbrb/graphics/screen_server.rb
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- lib/gbrb/instruction_set.rb
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- lib/gbrb/instruction_set/arithmetic.rb
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- lib/gbrb/instruction_set/bitwise.rb
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- lib/gbrb/instruction_set/boolean.rb
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- lib/gbrb/instruction_set/call.rb
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- lib/gbrb/instruction_set/carry.rb
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- lib/gbrb/instruction_set/cpl.rb
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- lib/gbrb/instruction_set/daa.rb
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- lib/gbrb/instruction_set/instruction.rb
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- lib/gbrb/instruction_set/jump.rb
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- lib/gbrb/instruction_set/ld.rb
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- lib/gbrb/instruction_set/return.rb
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- lib/gbrb/instruction_set/rotate.rb
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- lib/gbrb/instruction_set/rst.rb
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- lib/gbrb/instruction_set/special.rb
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- lib/gbrb/instruction_set/stack.rb
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- lib/gbrb/instruction_set/swap.rb
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- lib/gbrb/mmu.rb
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- lib/gbrb/options.rb
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- lib/gbrb/timer.rb
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- lib/gbrb/version.rb
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- misc/dump_diff
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- misc/parse_tiles
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141
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- perf/cpu_perf_spec.rb
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-
- spec/gbrb/cartridge_spec.rb
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- spec/gbrb/cartridge/cartridge_spec.rb
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- spec/gbrb/cartridge/mbc1_spec.rb
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144
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- spec/gbrb/cpu/concatenated_register_spec.rb
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145
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- spec/gbrb/cpu/flags_register_spec.rb
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- spec/gbrb/cpu/instruction_spec.rb
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- spec/gbrb/cpu/register_ensemble_spec.rb
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147
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- spec/gbrb/cpu/register_spec.rb
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- spec/gbrb/cpu/z80_spec.rb
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-
- spec/gbrb/
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- spec/gbrb/instruction_set/arithmetic_spec.rb
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- spec/gbrb/instruction_set/boolean_spec.rb
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- spec/gbrb/instruction_set/instruction_spec.rb
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- spec/gbrb/instruction_set/ld_spec.rb
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- spec/gbrb/instruction_set/special_spec.rb
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- spec/gbrb/mmu_spec.rb
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- spec/gbrb/timer_spec.rb
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- spec/gbrb/version_spec.rb
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- spec/spec_helper.rb
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homepage: http://rampantmonkey.github.io/GBRb
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@@ -141,14 +180,19 @@ signing_key:
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specification_version: 4
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summary: Nintendo Game Boy Emulator
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test_files:
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-
- spec/gbrb/cartridge_spec.rb
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- spec/gbrb/cartridge/cartridge_spec.rb
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- spec/gbrb/cartridge/mbc1_spec.rb
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- spec/gbrb/cpu/concatenated_register_spec.rb
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- spec/gbrb/cpu/flags_register_spec.rb
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-
- spec/gbrb/cpu/instruction_spec.rb
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187
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- spec/gbrb/cpu/register_ensemble_spec.rb
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- spec/gbrb/cpu/register_spec.rb
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- spec/gbrb/cpu/z80_spec.rb
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-
- spec/gbrb/
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- spec/gbrb/instruction_set/arithmetic_spec.rb
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- spec/gbrb/instruction_set/boolean_spec.rb
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- spec/gbrb/instruction_set/instruction_spec.rb
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- spec/gbrb/instruction_set/ld_spec.rb
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- spec/gbrb/instruction_set/special_spec.rb
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195
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- spec/gbrb/mmu_spec.rb
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- spec/gbrb/timer_spec.rb
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- spec/gbrb/version_spec.rb
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198
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- spec/spec_helper.rb
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data/lib/gbrb/cpu/instruction.rb
DELETED
@@ -1,648 +0,0 @@
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require_relative '../cpu'
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-
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module GBRb::CPU
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class Instruction
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attr_reader :i, :m, :t
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def initialize m=1, t=4, immediates=0, *extra
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@m = m
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@t = t
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@immediates = immediates
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end
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-
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def immediate_count
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@immediates
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end
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-
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def call r, mem
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nil
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end
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-
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def carry? left, right, mask
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(mask-1 & left).public_send(@op, mask-1 & right) & mask == mask
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end
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end
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-
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class Stop < Instruction; end
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-
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class Scf < Instruction
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def call r, mem
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r.clear_half_carry_flag
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31
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r.clear_add_sub_flag
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32
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r.set_carry_flag
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33
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end
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end
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-
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class Cpl < Instruction
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-
def call r, mem
|
38
|
-
r.set_add_sub_flag
|
39
|
-
r.set_half_carry_flag
|
40
|
-
r.a.store r.a.read ^ 0xff
|
41
|
-
end
|
42
|
-
end
|
43
|
-
|
44
|
-
class Ccf < Instruction
|
45
|
-
def call r, mem
|
46
|
-
if r.carry_flag?
|
47
|
-
r.clear_carry_flag
|
48
|
-
else
|
49
|
-
r.set_carry_flag
|
50
|
-
end
|
51
|
-
r.clear_add_sub_flag
|
52
|
-
r.clear_half_carry_flag
|
53
|
-
end
|
54
|
-
end
|
55
|
-
|
56
|
-
class Inc < Instruction
|
57
|
-
def initialize register, m=1, t=4, flags=true, indirect=false
|
58
|
-
super m, t
|
59
|
-
|
60
|
-
@register = register
|
61
|
-
@flags = flags
|
62
|
-
@op = :+
|
63
|
-
@indirect = indirect
|
64
|
-
end
|
65
|
-
|
66
|
-
def call r, mem
|
67
|
-
reg = r.public_send(@register.to_sym)
|
68
|
-
tmp = reg.read
|
69
|
-
if @indirect
|
70
|
-
v = mem.read_byte(tmp) + 1
|
71
|
-
mem.write_byte(tmp, v)
|
72
|
-
else
|
73
|
-
reg.store tmp + 1
|
74
|
-
end
|
75
|
-
if @flags
|
76
|
-
r.clear_add_sub_flag
|
77
|
-
reg.zero? ? r.set_zero_flag : r.clear_zero_flag
|
78
|
-
if carry? tmp, 0x01, reg.half_mask
|
79
|
-
r.set_half_carry_flag
|
80
|
-
else
|
81
|
-
r.clear_half_carry_flag
|
82
|
-
end
|
83
|
-
end
|
84
|
-
end
|
85
|
-
end
|
86
|
-
|
87
|
-
class Dec < Instruction
|
88
|
-
def initialize register, m=1, t=4, flags=true, indirect=false
|
89
|
-
super m, t
|
90
|
-
|
91
|
-
@register = register
|
92
|
-
@flags = flags
|
93
|
-
@op = :-
|
94
|
-
@indirect = indirect
|
95
|
-
end
|
96
|
-
|
97
|
-
def call r, mem
|
98
|
-
reg = r.public_send(@register.to_sym)
|
99
|
-
tmp = reg.read
|
100
|
-
if @indirect
|
101
|
-
v = mem.read_byte(tmp) - 1
|
102
|
-
mem.write_byte(tmp, v)
|
103
|
-
else
|
104
|
-
reg.store tmp - 0x01
|
105
|
-
end
|
106
|
-
if @flags
|
107
|
-
r.set_add_sub_flag
|
108
|
-
if reg.zero?
|
109
|
-
r.set_zero_flag
|
110
|
-
else
|
111
|
-
r.clear_zero_flag
|
112
|
-
end
|
113
|
-
if carry? tmp, 0x01, reg.half_mask
|
114
|
-
r.set_half_carry_flag
|
115
|
-
else
|
116
|
-
r.clear_half_carry_flag
|
117
|
-
end
|
118
|
-
end
|
119
|
-
end
|
120
|
-
end
|
121
|
-
|
122
|
-
class Ld < Instruction
|
123
|
-
def initialize destination, target, m=1, t=4, indirect_dest=false, indirect_target=false, immediates=0, offset=0x00
|
124
|
-
super m, t, immediates
|
125
|
-
|
126
|
-
@destination = destination
|
127
|
-
@target = target
|
128
|
-
@indirect_dest = indirect_dest
|
129
|
-
@indirect_target = indirect_target
|
130
|
-
@offset = offset
|
131
|
-
end
|
132
|
-
|
133
|
-
def call r, mem, v=nil
|
134
|
-
if not v
|
135
|
-
v = r.public_send(@target.to_sym).read
|
136
|
-
end
|
137
|
-
|
138
|
-
if @indirect_target
|
139
|
-
v = mem.read_byte(v + @offset)
|
140
|
-
target_reg = r.public_send(@destination.to_sym)
|
141
|
-
if @indirect_target == :increment
|
142
|
-
target_reg.store target_reg.read + 1
|
143
|
-
elsif @indirect_target == :decrement
|
144
|
-
target_reg.store target_reg.read - 1
|
145
|
-
end
|
146
|
-
end
|
147
|
-
|
148
|
-
|
149
|
-
if @indirect_dest
|
150
|
-
if @indirect_dest == :immediate
|
151
|
-
if @target.to_s.chars.length == 2
|
152
|
-
mem.write_word(v + @offset, r.public_send(@target.to_sym).read)
|
153
|
-
else
|
154
|
-
mem.write_byte(v + @offset, r.public_send(@target.to_sym).read)
|
155
|
-
end
|
156
|
-
else
|
157
|
-
reg = r.public_send(@destination.to_sym)
|
158
|
-
mem.write_byte(reg.read + @offset, v)
|
159
|
-
if @indirect_dest == :increment
|
160
|
-
reg.store reg.read + 1
|
161
|
-
elsif @indirect_dest == :decrement
|
162
|
-
reg.store reg.read - 1
|
163
|
-
end
|
164
|
-
end
|
165
|
-
else
|
166
|
-
r.public_send(@destination.to_sym).store v
|
167
|
-
end
|
168
|
-
end
|
169
|
-
end
|
170
|
-
|
171
|
-
class Ldh < Ld
|
172
|
-
def call r, mem, address
|
173
|
-
if @indirect_dest
|
174
|
-
value = r.public_send(@target.to_sym).read
|
175
|
-
mem.write_byte address + @offset, value
|
176
|
-
elsif @indirect_target
|
177
|
-
value = mem.read_byte address + @offset
|
178
|
-
r.public_send(@destination.to_sym).store value
|
179
|
-
end
|
180
|
-
end
|
181
|
-
end
|
182
|
-
|
183
|
-
class Ldhlsp < Instruction
|
184
|
-
def initialize m=2, t=12, immediates=1
|
185
|
-
super
|
186
|
-
@op = :+
|
187
|
-
end
|
188
|
-
|
189
|
-
def call r, mem, offset
|
190
|
-
sign = (offset >> 7 == 1) ? :- : :+
|
191
|
-
offset = ((offset ^ 0xff) + 1) & 0xff
|
192
|
-
value = r.sp.read.public_send(sign, offset)
|
193
|
-
r.hl.store value
|
194
|
-
r.clear_zero_flag
|
195
|
-
r.clear_add_sub_flag
|
196
|
-
carry?(value, 0x00, r.hl.mask) ? r.set_carry_flag : r.clear_carry_flag
|
197
|
-
carry?(value, 0x00, r.hl.half_mask) ? r.set_half_carry_flag : r.clear_half_carry_flag
|
198
|
-
end
|
199
|
-
end
|
200
|
-
|
201
|
-
class Jump < Instruction
|
202
|
-
def initialize condition, m=2, t_high=12, t_low=8, immediates=1
|
203
|
-
super m, t_low, immediates
|
204
|
-
@t_high = t_high
|
205
|
-
@condition = condition.downcase.to_sym
|
206
|
-
end
|
207
|
-
|
208
|
-
def call r, mem, offset
|
209
|
-
do_it = case @condition
|
210
|
-
when :c
|
211
|
-
r.carry_flag?
|
212
|
-
when :none
|
213
|
-
true
|
214
|
-
when :nc
|
215
|
-
not r.carry_flag?
|
216
|
-
when :nz
|
217
|
-
not r.zero_flag?
|
218
|
-
when :z
|
219
|
-
r.zero_flag?
|
220
|
-
else
|
221
|
-
false
|
222
|
-
end
|
223
|
-
|
224
|
-
if do_it
|
225
|
-
@t = @t_high
|
226
|
-
if @immediates == 1
|
227
|
-
sign = (offset >> 7 == 1) ? :- : :+
|
228
|
-
offset = ((offset ^ 0xff) + 1) & 0xff if sign == :-
|
229
|
-
r.pc.store r.pc.read.public_send(sign, offset)
|
230
|
-
else
|
231
|
-
r.pc.store offset
|
232
|
-
end
|
233
|
-
end
|
234
|
-
end
|
235
|
-
end
|
236
|
-
|
237
|
-
class Rl < Instruction
|
238
|
-
def initialize target, carry=false, indirect=false, m=2, t=8
|
239
|
-
super m, t
|
240
|
-
@target = target.to_sym
|
241
|
-
@carry = carry
|
242
|
-
@indirect = indirect
|
243
|
-
end
|
244
|
-
|
245
|
-
def call r, mem
|
246
|
-
if @indirect
|
247
|
-
address = r.public_send(@target).read
|
248
|
-
v = mem.read_byte(address) << 1
|
249
|
-
else
|
250
|
-
v = r.public_send(@target).read << 1
|
251
|
-
end
|
252
|
-
|
253
|
-
carry_in = if @carry
|
254
|
-
v & 0x100 == 0x100 ? 1 : 0
|
255
|
-
else
|
256
|
-
r.carry_flag? ? 1 : 0
|
257
|
-
end
|
258
|
-
|
259
|
-
v += carry_in
|
260
|
-
|
261
|
-
if @indirect
|
262
|
-
mem.write_byte(address, v)
|
263
|
-
else
|
264
|
-
r.public_send(@target).store v
|
265
|
-
end
|
266
|
-
|
267
|
-
r.clear_add_sub_flag
|
268
|
-
r.clear_half_carry_flag
|
269
|
-
v & 0xff == 0 ? r.set_zero_flag : r.clear_zero_flag
|
270
|
-
carry_out = v >> 8
|
271
|
-
carry_out == 1 ? r.set_carry_flag : r.clear_carry_flag
|
272
|
-
end
|
273
|
-
end
|
274
|
-
|
275
|
-
class Rr < Instruction
|
276
|
-
def initialize target, carry=false, indirect=false, m=2, t=8
|
277
|
-
super m, t
|
278
|
-
@target = target.to_sym
|
279
|
-
@carry = carry
|
280
|
-
@indirect = indirect
|
281
|
-
end
|
282
|
-
|
283
|
-
def call r, mem
|
284
|
-
if @indirect
|
285
|
-
address = r.public_send(@target).read
|
286
|
-
v = mem.read_byte(address)
|
287
|
-
else
|
288
|
-
v = r.public_send(@target).read
|
289
|
-
end
|
290
|
-
|
291
|
-
carry_out = v & 0x01
|
292
|
-
|
293
|
-
carry_in = if @carry
|
294
|
-
carry_out
|
295
|
-
else
|
296
|
-
r.carry_flag? ? 1 : 0
|
297
|
-
end
|
298
|
-
|
299
|
-
v >>= 1
|
300
|
-
|
301
|
-
v += carry_in << 7
|
302
|
-
|
303
|
-
if @indirect
|
304
|
-
original = mem.read_byte address
|
305
|
-
mem.write_byte(address, v)
|
306
|
-
else
|
307
|
-
r.public_send(@target).store v
|
308
|
-
end
|
309
|
-
|
310
|
-
r.clear_add_sub_flag
|
311
|
-
r.clear_half_carry_flag
|
312
|
-
v & 0xff == 0 ? r.set_zero_flag : r.clear_zero_flag
|
313
|
-
carry_out == 1 ? r.set_carry_flag : r.clear_carry_flag
|
314
|
-
end
|
315
|
-
end
|
316
|
-
|
317
|
-
class Swap < Instruction
|
318
|
-
def initialize target, m=2, t=8, indirect=false
|
319
|
-
@target = target
|
320
|
-
@indirect = indirect
|
321
|
-
super m, t
|
322
|
-
end
|
323
|
-
|
324
|
-
def call r, mem
|
325
|
-
initial = r.public_send(@target).read
|
326
|
-
initial = mem.read_byte(initial) if @indirect
|
327
|
-
high = initial >> 4
|
328
|
-
low = initial & ((1 << 4) - 1)
|
329
|
-
|
330
|
-
result = (low << 4) + high
|
331
|
-
|
332
|
-
if @indirect
|
333
|
-
mem.write_byte r.public_send(@target).read, result
|
334
|
-
mem.read_byte(r.public_send(@target).read) == 0 ? r.set_zero_flag : r.clear_zero_flag
|
335
|
-
else
|
336
|
-
r.public_send(@target).store result
|
337
|
-
r.public_send(@target).read == 0 ? r.set_zero_flag : r.clear_zero_flag
|
338
|
-
end
|
339
|
-
r.clear_add_sub_flag
|
340
|
-
r.clear_half_carry_flag
|
341
|
-
r.clear_carry_flag
|
342
|
-
end
|
343
|
-
end
|
344
|
-
|
345
|
-
class Arithmetic < Instruction
|
346
|
-
def initialize target, m, t, indirect, immediates=0
|
347
|
-
super m, t, immediates
|
348
|
-
@target = target
|
349
|
-
@indirect = indirect
|
350
|
-
end
|
351
|
-
|
352
|
-
def carry? left, right, mask
|
353
|
-
(mask-1 & left).public_send(@op, mask-1 & right) & mask == mask
|
354
|
-
end
|
355
|
-
|
356
|
-
def call r, mem, right_value
|
357
|
-
right_value ||= r.public_send(@target.to_sym).read
|
358
|
-
right_value = mem.read_byte(right_value) if @indirect
|
359
|
-
a_value = r.a.read
|
360
|
-
if carry? a_value, right_value, r.a.half_mask
|
361
|
-
r.set_half_carry_flag
|
362
|
-
else
|
363
|
-
r.clear_half_carry_flag
|
364
|
-
end
|
365
|
-
if carry? a_value, right_value, r.a.mask
|
366
|
-
r.set_carry_flag
|
367
|
-
else
|
368
|
-
r.clear_carry_flag
|
369
|
-
end
|
370
|
-
a_value = a_value.public_send(@op, right_value) & 0xff
|
371
|
-
r.a.store a_value unless @skip_store
|
372
|
-
a_value == 0x00 ? r.set_zero_flag : r.clear_zero_flag
|
373
|
-
end
|
374
|
-
end
|
375
|
-
|
376
|
-
class Add < Arithmetic
|
377
|
-
def initialize target, m=1, t=4, indirect=false, immediates=0
|
378
|
-
super
|
379
|
-
@op = :+
|
380
|
-
end
|
381
|
-
|
382
|
-
def call r, mem, right_value=nil
|
383
|
-
super
|
384
|
-
r.clear_add_sub_flag
|
385
|
-
end
|
386
|
-
end
|
387
|
-
|
388
|
-
class AddHl < Instruction
|
389
|
-
def initialize target, m=1, t=8
|
390
|
-
super m, t
|
391
|
-
@target = target.to_sym
|
392
|
-
@op = :+
|
393
|
-
end
|
394
|
-
|
395
|
-
def call r, mem
|
396
|
-
left = r.hl.read
|
397
|
-
right = r.public_send(@target).read
|
398
|
-
r.hl.store left + right
|
399
|
-
r.set_carry_flag if carry? left, right, r.hl.mask
|
400
|
-
r.set_half_carry_flag if carry? left, right, r.hl.half_mask
|
401
|
-
end
|
402
|
-
end
|
403
|
-
|
404
|
-
class Sub < Arithmetic
|
405
|
-
def initialize target, m=1, t=4, indirect=false, immediates=0
|
406
|
-
super
|
407
|
-
@op = :-
|
408
|
-
end
|
409
|
-
|
410
|
-
def call r, mem, right_value=nil
|
411
|
-
super
|
412
|
-
r.set_add_sub_flag
|
413
|
-
end
|
414
|
-
end
|
415
|
-
|
416
|
-
class Cp < Sub
|
417
|
-
def initialize *args
|
418
|
-
super
|
419
|
-
@skip_store = true
|
420
|
-
end
|
421
|
-
end
|
422
|
-
|
423
|
-
class Adc < Add
|
424
|
-
def call r, mem, right_value=nil
|
425
|
-
carry = r.carry_flag? ? 1 : 0
|
426
|
-
super r, mem, r.public_send(@target.to_sym).read + carry
|
427
|
-
end
|
428
|
-
end
|
429
|
-
|
430
|
-
class Sbc < Sub
|
431
|
-
def call r, mem, right_value=nil
|
432
|
-
carry = r.carry_flag? ? 1 : 0
|
433
|
-
super r, mem, r.public_send(@target.to_sym).read + carry
|
434
|
-
end
|
435
|
-
end
|
436
|
-
|
437
|
-
class Boolean < Instruction
|
438
|
-
def initialize target, m, t, indirect, immediates=0
|
439
|
-
@target = target
|
440
|
-
@indirect = indirect
|
441
|
-
super m, t, immediates
|
442
|
-
end
|
443
|
-
|
444
|
-
def call r, mem, v=nil
|
445
|
-
if v
|
446
|
-
value = v
|
447
|
-
else
|
448
|
-
value = r.public_send(@target.to_sym).read
|
449
|
-
value = mem.read_byte value if @indirect
|
450
|
-
end
|
451
|
-
r.a.store r.a.read.public_send(@op, value)
|
452
|
-
r.a.zero? ? r.set_zero_flag : r.clear_zero_flag
|
453
|
-
r.clear_carry_flag
|
454
|
-
r.clear_add_sub_flag
|
455
|
-
end
|
456
|
-
end
|
457
|
-
|
458
|
-
class And < Boolean
|
459
|
-
def initialize target, m=1, t=4, indirect=false, immediates=0
|
460
|
-
@op = :&
|
461
|
-
super
|
462
|
-
end
|
463
|
-
|
464
|
-
def call r, mem, v=nil
|
465
|
-
super
|
466
|
-
r.set_half_carry_flag
|
467
|
-
end
|
468
|
-
end
|
469
|
-
|
470
|
-
class Or < Boolean
|
471
|
-
def initialize target, m=1, t=4, indirect=false
|
472
|
-
@op = :|
|
473
|
-
super
|
474
|
-
end
|
475
|
-
|
476
|
-
def call r, mem
|
477
|
-
super
|
478
|
-
r.clear_half_carry_flag
|
479
|
-
end
|
480
|
-
end
|
481
|
-
|
482
|
-
class Xor < Boolean
|
483
|
-
def initialize target, m=1, t=4, indirect=false, immediates=0
|
484
|
-
@op = :^
|
485
|
-
super
|
486
|
-
end
|
487
|
-
|
488
|
-
def call r, mem, right_value=nil
|
489
|
-
super
|
490
|
-
r.clear_half_carry_flag
|
491
|
-
end
|
492
|
-
end
|
493
|
-
|
494
|
-
class Pop < Instruction
|
495
|
-
def initialize target, m=1, t=12
|
496
|
-
super m, t
|
497
|
-
@targets = target.to_s.chars.map{|a| a.to_sym}.reverse
|
498
|
-
end
|
499
|
-
|
500
|
-
def call r, mem
|
501
|
-
@targets.each do |target|
|
502
|
-
r.public_send(target).store mem.read_byte(r.sp.read)
|
503
|
-
r.sp.store r.sp.read + 1
|
504
|
-
end
|
505
|
-
end
|
506
|
-
end
|
507
|
-
|
508
|
-
class Push < Instruction
|
509
|
-
def initialize target, m=1, t=16
|
510
|
-
super m, t
|
511
|
-
@targets = target.to_s.chars.map{|a| a.to_sym}
|
512
|
-
end
|
513
|
-
|
514
|
-
def call r, mem
|
515
|
-
@targets.each do |target|
|
516
|
-
r.sp.store r.sp.read - 1
|
517
|
-
mem.write_byte(r.sp.read, r.public_send(target).read)
|
518
|
-
end
|
519
|
-
end
|
520
|
-
end
|
521
|
-
|
522
|
-
class Rst < Instruction
|
523
|
-
def initialize offset
|
524
|
-
@offset = offset
|
525
|
-
super 1, 16
|
526
|
-
end
|
527
|
-
|
528
|
-
def call r, mem
|
529
|
-
r.sp.store r.sp.read - 2
|
530
|
-
mem.write_word r.sp.read, r.pc.read
|
531
|
-
r.pc.store 0x0000 + @offset
|
532
|
-
end
|
533
|
-
end
|
534
|
-
|
535
|
-
class Call < Instruction
|
536
|
-
def initialize m=3, t=24, immediates=2, condition=:none
|
537
|
-
@condition = condition
|
538
|
-
super
|
539
|
-
end
|
540
|
-
|
541
|
-
def call r, mem, addr
|
542
|
-
condition_met = case @condition
|
543
|
-
when :Z
|
544
|
-
r.zero_flag?
|
545
|
-
when :none
|
546
|
-
true
|
547
|
-
else
|
548
|
-
false
|
549
|
-
end
|
550
|
-
if condition_met
|
551
|
-
r.sp.store r.sp.read - 2
|
552
|
-
mem.write_word(r.sp.read, r.pc.read)
|
553
|
-
r.pc.store addr
|
554
|
-
end
|
555
|
-
end
|
556
|
-
end
|
557
|
-
|
558
|
-
class Ret < Instruction
|
559
|
-
def initialize m=1, t=16, t_high=16, condition=:none
|
560
|
-
@condition = condition
|
561
|
-
@t_high = t_high
|
562
|
-
super m, t, 0
|
563
|
-
end
|
564
|
-
|
565
|
-
def call r, mem
|
566
|
-
condition_met = case @condition
|
567
|
-
when :NZ
|
568
|
-
not r.zero_flag?
|
569
|
-
when :none
|
570
|
-
true
|
571
|
-
else
|
572
|
-
false
|
573
|
-
end
|
574
|
-
if condition_met
|
575
|
-
@t = @t_high
|
576
|
-
low = mem.read_byte(r.sp.read)
|
577
|
-
r.sp.store r.sp.read + 1
|
578
|
-
high = mem.read_byte(r.sp.read)
|
579
|
-
r.sp.store r.sp.read + 1
|
580
|
-
|
581
|
-
r.pc.store (high << 8) + low
|
582
|
-
end
|
583
|
-
end
|
584
|
-
end
|
585
|
-
|
586
|
-
class EnableInterrupts < Instruction; end
|
587
|
-
class DisableInterrupts < Instruction; end
|
588
|
-
|
589
|
-
class Res < Instruction
|
590
|
-
def initialize bit, target, indirect=false, m=2, t=16
|
591
|
-
super m, t
|
592
|
-
@bit = bit
|
593
|
-
@mask = 0xff - 0b10 ** bit
|
594
|
-
@target = target.to_sym
|
595
|
-
@indirect = indirect
|
596
|
-
end
|
597
|
-
|
598
|
-
def call r, mem
|
599
|
-
if @indirect
|
600
|
-
addr = r.public_send(@target).read
|
601
|
-
mem.write_byte(addr, mem.read_byte(addr) & @mask)
|
602
|
-
else
|
603
|
-
r.public_send(@target).store r.public_send(@target).read & @mask
|
604
|
-
end
|
605
|
-
end
|
606
|
-
end
|
607
|
-
|
608
|
-
class Set < Instruction
|
609
|
-
def initialize bit, target, indirect=false, m=2, t=16
|
610
|
-
super m, t
|
611
|
-
@bit = bit
|
612
|
-
@mask = 0b10 ** bit
|
613
|
-
@target = target.to_sym
|
614
|
-
@indirect = indirect
|
615
|
-
end
|
616
|
-
|
617
|
-
def call r, mem
|
618
|
-
if @indirect
|
619
|
-
addr = r.public_send(@target).read
|
620
|
-
mem.write_byte(addr, mem.read_byte(addr) | @mask)
|
621
|
-
else
|
622
|
-
r.public_send(@target).store r.public_send(@target).read | @mask
|
623
|
-
end
|
624
|
-
end
|
625
|
-
end
|
626
|
-
|
627
|
-
class Bit < Instruction
|
628
|
-
def initialize bit, target, indirect=false, m=2, t=8
|
629
|
-
super m,t
|
630
|
-
@target = target
|
631
|
-
@bit = bit
|
632
|
-
@indirect = indirect
|
633
|
-
@mask = 1 << @bit
|
634
|
-
end
|
635
|
-
|
636
|
-
def call r, mem
|
637
|
-
if @indirect
|
638
|
-
v = mem.read_byte r.public_send(@target).read
|
639
|
-
else
|
640
|
-
v = r.public_send(@target).read
|
641
|
-
end
|
642
|
-
|
643
|
-
v & @mask != @mask ? r.set_zero_flag : r.clear_zero_flag
|
644
|
-
r.set_half_carry_flag
|
645
|
-
r.clear_add_sub_flag
|
646
|
-
end
|
647
|
-
end
|
648
|
-
end
|