zigzag-dse 3.2.1__tar.gz → 3.3.0__tar.gz

zigzag_dse-3.3.0/MANIFEST.in

@@ -0,0 +1,2 @@
+include zigzag/inputs/workload/*.onnx
+recursive-include zigzag/cacti *

{zigzag_dse-3.2.1/zigzag_dse.egg-info → zigzag_dse-3.3.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: zigzag-dse
-Version: 3.2.1
+Version: 3.3.0
 Summary: ZigZag - Deep Learning Hardware Design Space Exploration
 Author-email: Arne Symons <arne.symons@kuleuven.be>, Linyan Mei <linyan.mei@kuleuven.be>
 License: MIT License
@@ -41,6 +41,7 @@ Requires-Dist: tqdm
 Requires-Dist: multiprocessing_on_dill
 Requires-Dist: pyyaml
 Requires-Dist: cerberus
+Requires-Dist: seaborn
 Provides-Extra: dev
 Requires-Dist: bumpver; extra == "dev"
 Requires-Dist: pip-tools; extra == "dev"

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/pyproject.toml

@@ -14,7 +14,7 @@ namespaces = true  # true by default
 
 [project]
 name = "zigzag-dse"
-version = "3.2.1"
+version = "3.3.0"
 description = "ZigZag - Deep Learning Hardware Design Space Exploration"
 readme = "README.md"
 authors = [{ name = "Arne Symons", email = "arne.symons@kuleuven.be" }, { name = "Linyan Mei", email = "linyan.mei@kuleuven.be" }]
@@ -34,6 +34,7 @@ dependencies = [
     'multiprocessing_on_dill',
     'pyyaml',
     'cerberus',
+    'seaborn'
 ]
 requires-python = ">=3.11"
 
@@ -48,7 +49,7 @@ Homepage = "https://github.com/KULeuven-MICAS/zigzag"
 realpython = "zigzag.__main__:main"
 
 [tool.bumpver]
-current_version = "3.2.1"
+current_version = "3.3.0"
 version_pattern = "MAJOR.MINOR.PATCH"
 commit_message = "bump version {old_version} -> {new_version}"
 commit = true

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_imc/test_aimc.py

@@ -9,10 +9,13 @@ workloads = (
 
 # Expected energy, latency (#cycles), clk time and area for each workload defined above
 ens_lats_clks_areas = {
-    "zigzag/inputs/workload/alexnet.onnx": (6780119394.667442, 9261169.0, 14.07244, 2.3426222152749223),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (2318251910.682223, 10901796.0, 14.07244, 2.3426222152749223),
-    "zigzag/inputs/workload/resnet18.onnx": (4695729577.211851, 5540648.0, 14.07244, 2.3426222152749223),
-    "zigzag/inputs/workload/resnet18.yaml": (4264976904.6396008, 4907495.0, 14.07244, 2.3426222152749223),
+    "zigzag/inputs/workload/resnet18.onnx": (4696819238.427852, 5553018.0, 14.07244, 2.2878123152749223),
+    "zigzag/inputs/workload/resnet18.yaml": (
+        4264976904.6396008,
+        4907495.0,
+        14.07244,
+        2.2878123152749223,
+    ),
 }
 
 
@@ -35,6 +38,7 @@ def test_api(workload: str, accelerator: str, mapping: str):  # pylint: disable=
         expected_tclk,
         expected_area,
     ) = ens_lats_clks_areas[workload]
+    print(f"'{workload}': ({energy}, {latency}, {tclk}, {area}),")
     assert energy == pytest.approx(expected_energy)  # type: ignore
     assert latency == pytest.approx(expected_latency)  # type: ignore
     assert tclk == pytest.approx(expected_tclk)  # type: ignore

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_imc/test_dimc.py

@@ -9,10 +9,13 @@ workloads = (
 
 # Expected energy, latency (#cycles), clk time and area for each workload defined above
 ens_lats_clks_areas = {
-    "zigzag/inputs/workload/alexnet.onnx": (6811036226.435776, 9458913.0, 3.75708, 0.8566212024),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (2884847085.7898636, 20453908.0, 3.75708, 0.8566212024),
-    "zigzag/inputs/workload/resnet18.onnx": (4726170712.825855, 6337728.0, 3.75708, 0.8566212024),
-    "zigzag/inputs/workload/resnet18.yaml": (4268285089.3547516, 5789229.0, 3.75708, 0.8566212024),
+    "zigzag/inputs/workload/resnet18.onnx": (4727682330.905855, 6365842.0, 3.75708, 0.8018113023999999),
+    "zigzag/inputs/workload/resnet18.yaml": (
+        4268285089.3547516,
+        5789229.0,
+        3.75708,
+        0.8018113023999999,
+    ),
 }
 
 
@@ -35,6 +38,7 @@ def test_api(workload: str, accelerator: str, mapping: str):  # pylint: disable=
         expected_tclk,
         expected_area,
     ) = ens_lats_clks_areas[workload]
+    print(f"'{workload}': ({energy}, {latency}, {tclk}, {area}),")
     assert energy == pytest.approx(expected_energy)  # type: ignore
     assert latency == pytest.approx(expected_latency)  # type: ignore
     assert tclk == pytest.approx(expected_tclk)  # type: ignore

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_origin/test_ascend_like.py

@@ -9,7 +9,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/resnet18.onnx": (1860963861.6800003, 3698589.0),
+    "zigzag/inputs/workload/resnet18.onnx": (1860725512.0800002, 3734111.0),
     "zigzag/inputs/workload/resnet18.yaml": (2411783423.28, 4779709.0),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_origin/test_edge_tpu_like.py

@@ -9,7 +9,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/resnet18.onnx": (1902637139.1499994, 3333310.0),
+    "zigzag/inputs/workload/resnet18.onnx": (1903376014.3499994, 3333310.0),
     "zigzag/inputs/workload/resnet18.yaml": (2413348670.67, 4268451.0),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_origin/test_meta_prototype_like.py

@@ -9,7 +9,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/resnet18.onnx": (1869036158.08, 3366695.0),
+    "zigzag/inputs/workload/resnet18.onnx": (1870400796.8, 3614956.0),
     "zigzag/inputs/workload/resnet18.yaml": (2418511845.2400002, 4130645.0),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_origin/test_tesla_npu_like.py

@@ -9,7 +9,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/resnet18.onnx": (1863716799.84, 3380242.0),
+    "zigzag/inputs/workload/resnet18.onnx": (1865018192.8319998, 3876369.0),
     "zigzag/inputs/workload/resnet18.yaml": (2374655424.176, 4066942.0),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_origin/test_tpu_like.py

@@ -9,7 +9,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/resnet18.onnx": (1871436380.6559997, 4158539.0),
+    "zigzag/inputs/workload/resnet18.onnx": (1871930384.8159997, 4159004.0),
     "zigzag/inputs/workload/resnet18.yaml": (2615172831.3759995, 6136285.0),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_with_exploit_data_locality/test_ascend_like.py

@@ -8,9 +8,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/alexnet.onnx": (5649553476, 8605524),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (1880536921, 6472147),
-    "zigzag/inputs/workload/resnet18.onnx": (1711355797, 3567658),
+    "zigzag/inputs/workload/resnet18.onnx": (1711117447.5200002, 3603174.0),
     "zigzag/inputs/workload/resnet18.yaml": (2246606942, 4638794),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_with_exploit_data_locality/test_edge_tpu_like.py

@@ -8,9 +8,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/alexnet.onnx": (5568602396.684999, 8134431),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (735250234.1699998, 2417321.0),
-    "zigzag/inputs/workload/resnet18.onnx": (1783299827.71, 3156625.0),
+    "zigzag/inputs/workload/resnet18.onnx": (1784038702.91, 3156625.0),
     "zigzag/inputs/workload/resnet18.yaml": (2115121959.8699996, 3855157.0),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_with_exploit_data_locality/test_meta_prototype_like.py

@@ -8,9 +8,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/alexnet.onnx": (5679636177, 8279493),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (901087682, 2596085),
-    "zigzag/inputs/workload/resnet18.onnx": (1730188945, 3231087),
+    "zigzag/inputs/workload/resnet18.onnx": (1731553583.8400002, 3479347.0),
     "zigzag/inputs/workload/resnet18.yaml": (2264057101, 3984645),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_with_exploit_data_locality/test_tesla_npu_like.py

@@ -8,9 +8,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/alexnet.onnx": (6039993369, 8373281),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (930699349, 1955657),
-    "zigzag/inputs/workload/resnet18.onnx": (1724869587, 3247768),
+    "zigzag/inputs/workload/resnet18.onnx": (1726170979.8719997, 3743894.0),
     "zigzag/inputs/workload/resnet18.yaml": (2220200680, 3924484),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_with_exploit_data_locality/test_tpu_like.py

@@ -8,9 +8,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/alexnet.onnx": (5475639039, 8963572),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (952681462, 21868059),
-    "zigzag/inputs/workload/resnet18.onnx": (1735241704.2240005, 3998241.0),
+    "zigzag/inputs/workload/resnet18.onnx": (1735735708.3840003, 3998705.0),
     "zigzag/inputs/workload/resnet18.yaml": (2302362179.968, 5736497.0),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_with_mix_spatial_mapping/test_ascend_like.py

@@ -11,9 +11,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/alexnet.onnx": (5664863934, 8479644),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (920740293, 3814440),
-    "zigzag/inputs/workload/resnet18.onnx": (1680938520, 3697986),
+    "zigzag/inputs/workload/resnet18.onnx": (1680986460.6400003, 3829493.0),
     "zigzag/inputs/workload/resnet18.yaml": (2286320480, 4418088),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_with_mix_spatial_mapping/test_edge_tpu_like.py

@@ -11,9 +11,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/alexnet.onnx": (6159980160, 8337351),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (742114179, 2421959),
-    "zigzag/inputs/workload/resnet18.onnx": (1735517944, 4055269),
+    "zigzag/inputs/workload/resnet18.onnx": (1738892454.2700002, 4247189.0),
     "zigzag/inputs/workload/resnet18.yaml": (2029477205, 4738407),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_with_mix_spatial_mapping/test_meta_prototype_like.py

@@ -11,9 +11,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/alexnet.onnx": (5681909132.480001, 8279495.0),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (909647916.68, 2602479.0),
-    "zigzag/inputs/workload/resnet18.onnx": (1751779924.0000002, 3234867.0),
+    "zigzag/inputs/workload/resnet18.onnx": (1753144562.7200003, 3483127.0),
     "zigzag/inputs/workload/resnet18.yaml": (2259198622.68, 3884859.0),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_with_mix_spatial_mapping/test_tesla_npu_like.py

@@ -11,9 +11,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/alexnet.onnx": (6006136982.778, 8290892.0),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (947736166.5380002, 1857838.0),
-    "zigzag/inputs/workload/resnet18.onnx": (1604556365.552, 2828301.0),
+    "zigzag/inputs/workload/resnet18.onnx": (1605857758.544, 3324427.0),
     "zigzag/inputs/workload/resnet18.yaml": (2094141825.5040002, 3480232.0),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/tests/main/test_with_mix_spatial_mapping/test_tpu_like.py

@@ -11,9 +11,7 @@ workloads = (
 
 # Expected energy and latency for each workload defined above
 ens_lats = {
-    "zigzag/inputs/workload/alexnet.onnx": (5589583403, 8671208),
-    "zigzag/inputs/workload/mobilenetv2.onnx": (932571650, 7304307),
-    "zigzag/inputs/workload/resnet18.onnx": (1759424218.3160002, 4495469.0),
+    "zigzag/inputs/workload/resnet18.onnx": (1763016528.7640002, 4688029.0),
     "zigzag/inputs/workload/resnet18.yaml": (2191903732.78, 4845353.0),
 }
 

{zigzag_dse-3.2.1 → zigzag_dse-3.3.0}/zigzag/__init__.py

@@ -1,3 +1,3 @@
-__version__ = "3.2.1"
+__version__ = "3.3.0"
 
 # from . import visualization as visualization

zigzag_dse-3.3.0/zigzag/cacti/README.md

@@ -0,0 +1,10 @@
+# Cacti7_automation
+
+Run CACTI7 in batches and auto-generate mem_pool.yaml, which is required by ZigZag as input file.
+
+Use commends:
+```
+cd ./cacti-master
+python3 cacti_top.py
+```
+To get more configuration details, you can read the comments in "cacti_top.py" and "cacti_config_creator.py".

zigzag_dse-3.3.0/zigzag/cacti/cacti_master/2DDRAM_Samsung2GbDDR2.cfg

@@ -0,0 +1,194 @@
+# Cache size
+//-size (bytes) 528
+//-size (bytes) 4096
+//-size (bytes) 262144
+//-size (bytes) 1048576
+//-size (bytes) 2097152
+//-size (bytes) 4194304
+//-size (bytes) 8388608
+//-size (bytes) 16777216
+//-size (bytes) 33554432
+//-size (bytes) 134217728
+//-size (bytes) 268435456
+//-size (bytes) 536870912
+//-size (bytes) 67108864
+//-size (bytes) 536870912
+//-size (bytes) 1073741824
+# For 3D DRAM memory please use Gb as units
+-size (Gb) 2
+
+# Line size
+//-block size (bytes) 8
+-block size (bytes) 128
+
+# To model Fully Associative cache, set associativity to zero
+//-associativity 0
+//-associativity 2
+//-associativity 4
+-associativity 1
+//-associativity 16
+
+-read-write port 1
+-exclusive read port 0
+-exclusive write port 0
+-single ended read ports 0
+
+# Multiple banks connected using a bus
+-UCA bank count 16
+//-technology (u) 0.032
+//-technology (u) 0.040
+//-technology (u) 0.065
+//-technology (u) 0.078
+-technology (u) 0.080
+
+# following three parameters are meaningful only for main memories
+
+//-page size (bits) 8192 
+-burst length 4
+-internal prefetch width 1
+
+# following parameter can have one of five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
+//-Data array cell type - "itrs-hp"
+//-Data array cell type - "itrs-lstp"
+//-Data array cell type - "itrs-lop"
+-Data array cell type - "comm-dram"
+
+# following parameter can have one of three values -- (itrs-hp, itrs-lstp, itrs-lop)
+//-Data array peripheral type - "itrs-hp"
+-Data array peripheral type - "itrs-lstp"
+//-Data array peripheral type - "itrs-lop"
+
+# following parameter can have one of five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
+-Tag array cell type - "itrs-hp"
+//-Tag array cell type - "itrs-lstp"
+
+# following parameter can have one of three values -- (itrs-hp, itrs-lstp, itrs-lop)
+-Tag array peripheral type - "itrs-hp"
+//-Tag array peripheral type - "itrs-lstp"
+
+# Bus width include data bits and address bits required by the decoder
+//-output/input bus width 16
+//-output/input bus width 64
+-output/input bus width 64
+
+// 300-400 in steps of 10
+-operating temperature (K) 350
+
+# Type of memory - cache (with a tag array) or ram (scratch ram similar to a register file) 
+# or main memory (no tag array and every access will happen at a page granularity Ref: CACTI 5.3 report)
+//-cache type "cache"
+//-cache type "ram"
+//-cache type "main memory"
+-cache type "3D memory or 2D main memory"
+
+# Parameters for 3D DRAM
+//-page size (bits) 16384 
+-page size (bits) 8192
+//-page size (bits) 4096
+-burst depth 4
+-IO width 4
+-system frequency (MHz) 266
+
+-stacked die count 1
+-partitioning granularity 0 // 0: coarse-grained rank-level; 1: fine-grained rank-level
+//-TSV projection 1 // 0: ITRS aggressive; 1: industrial conservative
+
+## End of parameters for 3D DRAM
+
+# to model special structure like branch target buffers, directory, etc. 
+# change the tag size parameter
+# if you want cacti to calculate the tagbits, set the tag size to "default"
+-tag size (b) "default"
+//-tag size (b) 45
+
+# fast - data and tag access happen in parallel
+# sequential - data array is accessed after accessing the tag array
+# normal - data array lookup and tag access happen in parallel
+#          final data block is broadcasted in data array h-tree 
+#          after getting the signal from the tag array
+-access mode (normal, sequential, fast) - "fast"
+//-access mode (normal, sequential, fast) - "normal"
+//-access mode (normal, sequential, fast) - "sequential"
+
+
+# DESIGN OBJECTIVE for UCA (or banks in NUCA)
+-design objective (weight delay, dynamic power, leakage power, cycle time, area) 0:0:0:0:100
+
+# Percentage deviation from the minimum value 
+# Ex: A deviation value of 10:1000:1000:1000:1000 will try to find an organization
+# that compromises at most 10% delay. 
+# NOTE: Try reasonable values for % deviation. Inconsistent deviation
+# percentage values will not produce any valid organizations. For example,
+# 0:0:100:100:100 will try to identify an organization that has both
+# least delay and dynamic power. Since such an organization is not possible, CACTI will
+# throw an error. Refer CACTI-6 Technical report for more details
+-deviate (delay, dynamic power, leakage power, cycle time, area) 50:100000:100000:100000:1000000
+
+# Objective for NUCA
+-NUCAdesign objective (weight delay, dynamic power, leakage power, cycle time, area) 0:0:0:0:100
+-NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) 10:10000:10000:10000:10000
+
+# Set optimize tag to ED or ED^2 to obtain a cache configuration optimized for
+# energy-delay or energy-delay sq. product
+# Note: Optimize tag will disable weight or deviate values mentioned above
+# Set it to NONE to let weight and deviate values determine the 
+# appropriate cache configuration
+//-Optimize ED or ED^2 (ED, ED^2, NONE): "ED"
+//-Optimize ED or ED^2 (ED, ED^2, NONE): "ED^2"
+-Optimize ED or ED^2 (ED, ED^2, NONE): "NONE"
+
+-Cache model (NUCA, UCA)  - "UCA"
+//-Cache model (NUCA, UCA)  - "NUCA"
+
+# In order for CACTI to find the optimal NUCA bank value the following
+# variable should be assigned 0.
+-NUCA bank count 0
+
+# NOTE: for nuca network frequency is set to a default value of 
+# 5GHz in time.c. CACTI automatically
+# calculates the maximum possible frequency and downgrades this value if necessary
+
+# By default CACTI considers both full-swing and low-swing 
+# wires to find an optimal configuration. However, it is possible to 
+# restrict the search space by changing the signaling from "default" to 
+# "fullswing" or "lowswing" type.
+-Wire signaling (fullswing, lowswing, default) - "Global_5"
+//-Wire signaling (fullswing, lowswing, default) - "default"
+//-Wire signaling (fullswing, lowswing, default) - "lowswing"
+
+//-Wire inside mat - "global"
+-Wire inside mat - "semi-global"
+-Wire outside mat - "global"
+//-Wire outside mat - "semi-global"
+
+-Interconnect projection - "conservative"
+//-Interconnect projection - "aggressive"
+
+# Contention in network (which is a function of core count and cache level) is one of
+# the critical factor used for deciding the optimal bank count value
+# core count can be 4, 8, or 16
+//-Core count 4
+-Core count 8
+//-Core count 16
+-Cache level (L2/L3) - "L3"
+
+-Add ECC - "false"
+
+//-Print level (DETAILED, CONCISE) - "CONCISE"
+-Print level (DETAILED, CONCISE) - "DETAILED"
+
+# for debugging
+//-Print input parameters - "true"
+-Print input parameters - "false"
+# force CACTI to model the cache with the 
+# following Ndbl, Ndwl, Nspd, Ndsam,
+# and Ndcm values
+-Force cache config - "true"
+//-Force cache config - "false"
+-Ndwl 128
+-Ndbl 32
+-Nspd 1
+-Ndcm 1
+-Ndsam1 1
+-Ndsam2 1
+