zigzag-dse 2.1.7__tar.gz → 2.2.1__tar.gz

{zigzag-dse-2.1.7/zigzag_dse.egg-info → zigzag-dse-2.2.1}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: zigzag-dse
-Version: 2.1.7
+Version: 2.2.1
 Summary: ZigZag - Deep Learning Hardware Design Space Exploration
 Author-email: Arne Symons <arne.symons@kuleuven.be>, Linyan Mei <linyan.mei@kuleuven.be>
 License: BSD 3-Clause License
@@ -55,6 +55,8 @@ Please take a look at the [Installation](https://zigzag-project.github.io/zigzag
 
 Please take a look at the [Getting Started](https://zigzag-project.github.io/zigzag/getting-started.html) page on how to get started using ZigZag.
 
+Also, a Jupyter Notebook based demo is prepared for new users [here](https://github.com/ZigZag-Project/zigzag-demo).
+
 ## Recent changes
 
 In this novel version, we have: 
@@ -77,17 +79,19 @@ L. Mei, P. Houshmand, V. Jain, S. Giraldo and M. Verhelst, "ZigZag: Enlarging Jo
 L. Mei, H. Liu, T. Wu, H. E. Sumbul, M. Verhelst and E. Beigne, "A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows," 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2022, pp. 220-225, doi: 10.23919/DATE54114.2022.9774728. [paper](https://lirias.kuleuven.be/retrieve/661303), [slides](https://docs.google.com/presentation/d/1mPdzEvuhu4923L0qYfEXGqRH7jtnHDlm/edit?usp=sharing&ouid=117150865143314519834&rtpof=true&sd=true), [video](https://drive.google.com/file/d/1o1ZY_rPsR5d8ZNpxxO7be0Tc2KUQIfX_/view?usp=sharing)
 
 #### The new temporal mapping search engine
-A. Symons, L. Mei and M. Verhelst, "LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4, doi: 10.1109/AICAS51828.2021.9458493. [paper](https://ieeexplore.ieee.org/document/9458493)
+A. Symons, L. Mei and M. Verhelst, "LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4, doi: 10.1109/AICAS51828.2021.9458493. [paper](https://ieeexplore.ieee.org/document/9458493), [slides](https://drive.google.com/file/d/1m_4YznH67mxngP3Mlmoj_c8ruRqrjdbq/view?usp=share_link), [video](https://drive.google.com/file/d/1pK3hoy3znto7JfXHj3V_sWv4FdrcTgzA/view?usp=share_link)
 
 #### Apply ZigZag for different design space exploration case studies
-P. Houshmand, S. Cosemans, L. Mei, I. Papistas, D. Bhattacharjee, P. Debacker, A. Mallik, D. Verkest, M. Verhelst, "Opportunities and Limitations of Emerging Analog in-Memory Compute DNN Architectures," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 29.1.1-29.1.4, doi: 10.1109/IEDM13553.2020.9372006. [paper](https://ieeexplore.ieee.org/abstract/document/9372006)
+P. Houshmand, S. Cosemans, L. Mei, I. Papistas, D. Bhattacharjee, P. Debacker, A. Mallik, D. Verkest, M. Verhelst, "Opportunities and Limitations of Emerging Analog in-Memory Compute DNN Architectures," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 29.1.1-29.1.4, doi: 10.1109/IEDM13553.2020.9372006. [paper](https://ieeexplore.ieee.org/abstract/document/9372006), [slides](https://docs.google.com/presentation/d/e/2PACX-1vRTB-KJemyLhrBmiZ9c7fL8gpnIevJzB2feNHeAGfcKchkFR698Df2_Wh0CXu8Qrg/pub?start=false&loop=false&delayms=30000), [video](https://drive.google.com/file/d/1tfz9NJKDECWgkYCK_vtir8hf2-Dz5ISh/view?usp=sharing)
+
+V. Jain, L. Mei and M. Verhelst, "Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4, doi: 10.1109/AICAS51828.2021.9458553. [paper](https://ieeexplore.ieee.org/abstract/document/9458553), [slides](https://docs.google.com/presentation/d/1IIeNwIfunKE409SmlS3JEIAF-5GyhbCN/edit?usp=sharing&ouid=100287940751782809199&rtpof=true&sd=true), [video](https://drive.google.com/file/d/1SssJKLt89H1SCAeCOUX4ibsZ15ewLKPb/view?usp=sharing)
 
-V. Jain, L. Mei and M. Verhelst, "Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4, doi: 10.1109/AICAS51828.2021.9458553. [paper](https://ieeexplore.ieee.org/abstract/document/9458553)
+S. Colleman, T. Verelst, L. Mei, T. Tuytelaars and M. Verhelst, "Processor Architecture Optimization for Spatially Dynamic Neural Networks," 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), Singapore, Singapore, 2021, pp. 1-6, doi: 10.1109/VLSI-SoC53125.2021.9607013. [paper](https://ieeexplore.ieee.org/abstract/document/9607013), [slides](https://drive.google.com/file/d/1to0IHQP30CUbjh37LrT_g4Tfjo6VhVx7/view?usp=sharing), [video](https://drive.google.com/file/d/1tjp_0OBiXSFOOF_u3cw9Zr-u4fcJRy9_/view?usp=sharing)
 
-S. Colleman, T. Verelst, L. Mei, T. Tuytelaars and M. Verhelst, "Processor Architecture Optimization for Spatially Dynamic Neural Networks," 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), Singapore, Singapore, 2021, pp. 1-6, doi: 10.1109/VLSI-SoC53125.2021.9607013. [paper](https://ieeexplore.ieee.org/abstract/document/9607013)
+S. Colleman, P. Zhu, W. Sun and M. Verhelst, "Optimizing Accelerator Configurability for Mobile Transformer Networks," 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Incheon, Korea, Republic of, 2022, pp. 142-145, doi: 10.1109/AICAS54282.2022.9869945. [paper](https://ieeexplore.ieee.org/document/9869945), [slides](https://docs.google.com/presentation/d/1tp11akyAVGg3Y20Aupp2wlTRSgg9nKAQ/edit?usp=sharing&ouid=117150865143314519834&rtpof=true&sd=true), [video](https://drive.google.com/file/d/1tglc-BCGVclrWT-kNhWy02Vms5sjk1zt/view?usp=sharing)
 
 #### Extend ZigZag to support cross-layer depth-first scheduling
-L. Mei, K. Goetschalckx, A. Symons and M. Verhelst, " DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling," 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023 [paper](https://arxiv.org/abs/2212.05344), [github](https://github.com/ZigZag-Project/DeFiNES)
+L. Mei, K. Goetschalckx, A. Symons and M. Verhelst, " DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling," 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023 [paper](https://arxiv.org/abs/2212.05344), [slides](https://drive.google.com/file/d/1u_PG9ZhjUZVrH2wnMLDe-PYJeO0RUGLd/view?usp=sharing), [github](https://github.com/ZigZag-Project/DeFiNES)
 
 #### Extend ZigZag to support multi-core layer-fused scheduling
 A. Symons, L. Mei, S. Colleman, P. Houshmand, S. Karl and M. Verhelst, “Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks”, <i>arXiv e-prints</i>, 2022. doi:10.48550/arXiv.2212.10612. [paper](https://arxiv.org/abs/2212.10612), [github](https://github.com/ZigZag-Project/stream)

{zigzag-dse-2.1.7 → zigzag-dse-2.2.1}/README.md

@@ -11,6 +11,8 @@ Please take a look at the [Installation](https://zigzag-project.github.io/zigzag
 
 Please take a look at the [Getting Started](https://zigzag-project.github.io/zigzag/getting-started.html) page on how to get started using ZigZag.
 
+Also, a Jupyter Notebook based demo is prepared for new users [here](https://github.com/ZigZag-Project/zigzag-demo).
+
 ## Recent changes
 
 In this novel version, we have: 
@@ -33,17 +35,19 @@ L. Mei, P. Houshmand, V. Jain, S. Giraldo and M. Verhelst, "ZigZag: Enlarging Jo
 L. Mei, H. Liu, T. Wu, H. E. Sumbul, M. Verhelst and E. Beigne, "A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows," 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2022, pp. 220-225, doi: 10.23919/DATE54114.2022.9774728. [paper](https://lirias.kuleuven.be/retrieve/661303), [slides](https://docs.google.com/presentation/d/1mPdzEvuhu4923L0qYfEXGqRH7jtnHDlm/edit?usp=sharing&ouid=117150865143314519834&rtpof=true&sd=true), [video](https://drive.google.com/file/d/1o1ZY_rPsR5d8ZNpxxO7be0Tc2KUQIfX_/view?usp=sharing)
 
 #### The new temporal mapping search engine
-A. Symons, L. Mei and M. Verhelst, "LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4, doi: 10.1109/AICAS51828.2021.9458493. [paper](https://ieeexplore.ieee.org/document/9458493)
+A. Symons, L. Mei and M. Verhelst, "LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4, doi: 10.1109/AICAS51828.2021.9458493. [paper](https://ieeexplore.ieee.org/document/9458493), [slides](https://drive.google.com/file/d/1m_4YznH67mxngP3Mlmoj_c8ruRqrjdbq/view?usp=share_link), [video](https://drive.google.com/file/d/1pK3hoy3znto7JfXHj3V_sWv4FdrcTgzA/view?usp=share_link)
 
 #### Apply ZigZag for different design space exploration case studies
-P. Houshmand, S. Cosemans, L. Mei, I. Papistas, D. Bhattacharjee, P. Debacker, A. Mallik, D. Verkest, M. Verhelst, "Opportunities and Limitations of Emerging Analog in-Memory Compute DNN Architectures," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 29.1.1-29.1.4, doi: 10.1109/IEDM13553.2020.9372006. [paper](https://ieeexplore.ieee.org/abstract/document/9372006)
+P. Houshmand, S. Cosemans, L. Mei, I. Papistas, D. Bhattacharjee, P. Debacker, A. Mallik, D. Verkest, M. Verhelst, "Opportunities and Limitations of Emerging Analog in-Memory Compute DNN Architectures," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 29.1.1-29.1.4, doi: 10.1109/IEDM13553.2020.9372006. [paper](https://ieeexplore.ieee.org/abstract/document/9372006), [slides](https://docs.google.com/presentation/d/e/2PACX-1vRTB-KJemyLhrBmiZ9c7fL8gpnIevJzB2feNHeAGfcKchkFR698Df2_Wh0CXu8Qrg/pub?start=false&loop=false&delayms=30000), [video](https://drive.google.com/file/d/1tfz9NJKDECWgkYCK_vtir8hf2-Dz5ISh/view?usp=sharing)
+
+V. Jain, L. Mei and M. Verhelst, "Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4, doi: 10.1109/AICAS51828.2021.9458553. [paper](https://ieeexplore.ieee.org/abstract/document/9458553), [slides](https://docs.google.com/presentation/d/1IIeNwIfunKE409SmlS3JEIAF-5GyhbCN/edit?usp=sharing&ouid=100287940751782809199&rtpof=true&sd=true), [video](https://drive.google.com/file/d/1SssJKLt89H1SCAeCOUX4ibsZ15ewLKPb/view?usp=sharing)
 
-V. Jain, L. Mei and M. Verhelst, "Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4, doi: 10.1109/AICAS51828.2021.9458553. [paper](https://ieeexplore.ieee.org/abstract/document/9458553)
+S. Colleman, T. Verelst, L. Mei, T. Tuytelaars and M. Verhelst, "Processor Architecture Optimization for Spatially Dynamic Neural Networks," 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), Singapore, Singapore, 2021, pp. 1-6, doi: 10.1109/VLSI-SoC53125.2021.9607013. [paper](https://ieeexplore.ieee.org/abstract/document/9607013), [slides](https://drive.google.com/file/d/1to0IHQP30CUbjh37LrT_g4Tfjo6VhVx7/view?usp=sharing), [video](https://drive.google.com/file/d/1tjp_0OBiXSFOOF_u3cw9Zr-u4fcJRy9_/view?usp=sharing)
 
-S. Colleman, T. Verelst, L. Mei, T. Tuytelaars and M. Verhelst, "Processor Architecture Optimization for Spatially Dynamic Neural Networks," 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), Singapore, Singapore, 2021, pp. 1-6, doi: 10.1109/VLSI-SoC53125.2021.9607013. [paper](https://ieeexplore.ieee.org/abstract/document/9607013)
+S. Colleman, P. Zhu, W. Sun and M. Verhelst, "Optimizing Accelerator Configurability for Mobile Transformer Networks," 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Incheon, Korea, Republic of, 2022, pp. 142-145, doi: 10.1109/AICAS54282.2022.9869945. [paper](https://ieeexplore.ieee.org/document/9869945), [slides](https://docs.google.com/presentation/d/1tp11akyAVGg3Y20Aupp2wlTRSgg9nKAQ/edit?usp=sharing&ouid=117150865143314519834&rtpof=true&sd=true), [video](https://drive.google.com/file/d/1tglc-BCGVclrWT-kNhWy02Vms5sjk1zt/view?usp=sharing)
 
 #### Extend ZigZag to support cross-layer depth-first scheduling
-L. Mei, K. Goetschalckx, A. Symons and M. Verhelst, " DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling," 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023 [paper](https://arxiv.org/abs/2212.05344), [github](https://github.com/ZigZag-Project/DeFiNES)
+L. Mei, K. Goetschalckx, A. Symons and M. Verhelst, " DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling," 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023 [paper](https://arxiv.org/abs/2212.05344), [slides](https://drive.google.com/file/d/1u_PG9ZhjUZVrH2wnMLDe-PYJeO0RUGLd/view?usp=sharing), [github](https://github.com/ZigZag-Project/DeFiNES)
 
 #### Extend ZigZag to support multi-core layer-fused scheduling
-A. Symons, L. Mei, S. Colleman, P. Houshmand, S. Karl and M. Verhelst, “Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks”, <i>arXiv e-prints</i>, 2022. doi:10.48550/arXiv.2212.10612. [paper](https://arxiv.org/abs/2212.10612), [github](https://github.com/ZigZag-Project/stream)
+A. Symons, L. Mei, S. Colleman, P. Houshmand, S. Karl and M. Verhelst, “Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks”, <i>arXiv e-prints</i>, 2022. doi:10.48550/arXiv.2212.10612. [paper](https://arxiv.org/abs/2212.10612), [github](https://github.com/ZigZag-Project/stream)

zigzag-dse-2.2.1/docs/source/conf.py

@@ -0,0 +1,81 @@
+# Configuration file for the Sphinx documentation builder.
+#
+# This file only contains a selection of the most common options. For a full
+# list see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Path setup --------------------------------------------------------------
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+import os
+import sys
+sys.path.insert(0, os.path.abspath('.'))
+
+
+# -- Project information -----------------------------------------------------
+
+project = 'ZigZag'
+copyright = '2022, Arne Symons'
+author = 'Arne Symons'
+
+# The full version, including alpha/beta/rc tags
+release = '2.0.0'
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+    'sphinx.ext.autodoc'
+]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = []
+
+
+# -- Options for HTML output -------------------------------------------------
+
+# The theme to use for HTML and HTML Help pages.  See the documentation for
+# a list of builtin themes.
+#
+html_theme = "sphinx_material"
+
+# Logo
+html_logo = "./zigzag_logo_white_32x32.svg"
+
+# Favicon
+html_favicon = "./zigzag_logo_white_32x32.svg"
+
+# Material theme options
+html_theme_options = {
+    'base_url': 'http://zigzag-project.github.io/zigzag/',
+    'repo_url': 'https://github.com/ZigZag-Project/zigzag',
+    'repo_name': 'ZigZag Framework',
+    'google_analytics_account': 'UA-XXXXX',
+    'html_minify': True,
+    'css_minify': True,
+    'nav_title': 'ZigZag Framework',
+    # 'logo_icon': '&#x1D56B',  # '&#x2124',
+    'globaltoc_depth': 2,
+    'color_primary': "blue-grey",
+    'color_accent': "grey"
+}
+
+html_sidebars = {
+    "**": ["logo-text.html", "globaltoc.html", "localtoc.html", "searchbox.html"]
+}
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['_static']

zigzag-dse-2.2.1/inputs/examples/hardware/Ascend_like_DF.py

@@ -0,0 +1,135 @@
+import os
+from zigzag.classes.hardware.architecture.memory_hierarchy import MemoryHierarchy
+from zigzag.classes.hardware.architecture.memory_level import MemoryLevel
+from zigzag.classes.hardware.architecture.operational_unit import Multiplier
+from zigzag.classes.hardware.architecture.operational_array import MultiplierArray
+from zigzag.classes.hardware.architecture.memory_instance import MemoryInstance
+from zigzag.classes.hardware.architecture.accelerator import Accelerator
+from zigzag.classes.hardware.architecture.core import Core
+
+
+def memory_hierarchy_dut(multiplier_array):
+    """Memory hierarchy variables"""
+    ''' size=#bit, bw=(read bw, write bw), cost=(read word energy, write work energy) '''
+
+    reg_W1 = MemoryInstance(name="rf_1B", size=8, r_bw=8, w_bw=8, r_cost=0.01, w_cost=0.01, area=0,
+                            r_port=1, w_port=1, rw_port=0, latency=1)
+
+    reg_O1 = MemoryInstance(name="rf_2B", size=16, r_bw=16, w_bw=16, r_cost=0.02, w_cost=0.02, area=0,
+                            r_port=2, w_port=2, rw_port=0, latency=1)
+
+    ##################################### on-chip memory hierarchy building blocks #####################################
+
+    sram_64KB_with_8_8K_64_1r_1w_I = \
+        MemoryInstance(name="sram_64KB_I", size=8192 * 8, r_bw=64 * 8, w_bw=64 * 8, r_cost=3.32 * 8, w_cost=3.84 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_64KB_with_8_8K_256_1r_1w_W = \
+        MemoryInstance(name="sram_64KB_W", size=8192 * 8, r_bw=256 * 8, w_bw=256 * 8, r_cost=6.27 * 8, w_cost=13.5 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_256KB_with_8_32KB_256_1r_1w_O = \
+        MemoryInstance(name="sram_256KB_O", size=32768 * 8 * 8, r_bw=256 * 8, w_bw=256 * 8, r_cost=15.4 * 8, w_cost=26.6 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_256KB_with_8_32KB_256_1r_1w_O_staging = \
+        MemoryInstance(name="sram_256KB_O_staging", size=32768 * 8 * 8 + 1, r_bw=256 * 8, w_bw=256 * 8, r_cost=15.4 * 8, w_cost=26.6 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_1M_with_8_128K_bank_128_1r_1w_A = \
+        MemoryInstance(name="sram_1MB_A", size=131072 * 8 * 8, r_bw=512 * 8, w_bw=512 * 8, r_cost=58.2 * 8, w_cost=103.2 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_1M_with_8_128K_bank_128_1r_1w_W = \
+        MemoryInstance(name="sram_1MB_W", size=131072 * 8 * 8, r_bw=512 * 8, w_bw=512 * 8, r_cost=58.2 * 8, w_cost=103.2 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    #######################################################################################################################
+
+    dram = MemoryInstance(name="dram", size=10000000000, r_bw=64, w_bw=64, r_cost=700, w_cost=750, area=0,
+                          r_port=0, w_port=0, rw_port=1, latency=1)
+
+    memory_hierarchy_graph = MemoryHierarchy(operational_array=multiplier_array)
+
+    '''
+    fh: from high = wr_in_by_high 
+    fl: from low = wr_in_by_low 
+    th: to high = rd_out_to_high
+    tl: to low = rd_out_to_low
+    '''
+    # we don't have unrolled I-Reg to better support G unrolling
+    # memory_hierarchy_graph.add_memory(memory_instance=reg_IW1, operands=('I1',),
+    #                                   port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+    #                                   served_dimensions={(0, 0, 0, 0)})
+    memory_hierarchy_graph.add_memory(memory_instance=reg_W1, operands=('I2',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+                                      served_dimensions={(0, 0, 1, 0), (0, 0, 0, 1)})
+    memory_hierarchy_graph.add_memory(memory_instance=reg_O1, operands=('O',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': 'w_port_2', 'th': 'r_port_2'},),
+                                      served_dimensions={(0, 1, 0, 0)})
+
+    ##################################### on-chip highest memory hierarchy initialization #####################################
+
+    memory_hierarchy_graph.add_memory(memory_instance=sram_64KB_with_8_8K_256_1r_1w_W, operands=('I2',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+                                      served_dimensions='all')
+
+    memory_hierarchy_graph.add_memory(memory_instance=sram_64KB_with_8_8K_64_1r_1w_I, operands=('I1', 'O'),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': 'w_port_1', 'th': 'r_port_1'},),
+                                      served_dimensions='all')
+
+    memory_hierarchy_graph.add_memory(memory_instance=sram_256KB_with_8_32KB_256_1r_1w_O, operands=('I1', 'O'),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': 'w_port_1', 'th': 'r_port_1'},),
+                                      served_dimensions='all')
+
+    memory_hierarchy_graph.add_memory(memory_instance=sram_1M_with_8_128K_bank_128_1r_1w_W, operands=('I2',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+                                      served_dimensions='all')
+    memory_hierarchy_graph.add_memory(memory_instance=sram_1M_with_8_128K_bank_128_1r_1w_A, operands=('I1', 'O'),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': 'w_port_1', 'th': 'r_port_1'},),
+                                      served_dimensions='all')
+
+    ####################################################################################################################
+
+    memory_hierarchy_graph.add_memory(memory_instance=dram, operands=('I1', 'I2', 'O'),
+                                      port_alloc=({'fh': 'rw_port_1', 'tl': 'rw_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'rw_port_1', 'tl': 'rw_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'rw_port_1', 'tl': 'rw_port_1', 'fl': 'rw_port_1', 'th': 'rw_port_1'},),
+                                      served_dimensions='all')
+
+    from zigzag.visualization.graph.memory_hierarchy import visualize_memory_hierarchy_graph
+    # visualize_memory_hierarchy_graph(memory_hierarchy_graph)
+    return memory_hierarchy_graph
+
+
+def multiplier_array_dut():
+    """ Multiplier array variables """
+    multiplier_input_precision = [8, 8]
+    multiplier_energy = 0.04
+    multiplier_area = 1
+    dimensions = {'D1': 16, 'D2': 16, 'D3': 2, 'D4': 2}  # {'D1': ('K', 16), 'D2': ('C', 16), 'D3': ('OX', 2), 'D4': ('OY', 2),}
+
+    multiplier = Multiplier(multiplier_input_precision, multiplier_energy, multiplier_area)
+    multiplier_array = MultiplierArray(multiplier, dimensions)
+
+    return multiplier_array
+
+
+def cores():
+    multiplier_array1 = multiplier_array_dut()
+    memory_hierarchy1 = memory_hierarchy_dut(multiplier_array1)
+
+    core1 = Core(1, multiplier_array1, memory_hierarchy1)
+
+    return {core1}
+
+
+cores = cores()
+global_buffer = None
+acc_name = os.path.basename(__file__)[:-3]
+accelerator = Accelerator(acc_name, cores, global_buffer)
+
+a = 1

zigzag-dse-2.2.1/inputs/examples/hardware/Edge_TPU_like_DF.py

@@ -0,0 +1,119 @@
+import os
+from zigzag.classes.hardware.architecture.memory_hierarchy import MemoryHierarchy
+from zigzag.classes.hardware.architecture.memory_level import MemoryLevel
+from zigzag.classes.hardware.architecture.operational_unit import Multiplier
+from zigzag.classes.hardware.architecture.operational_array import MultiplierArray
+from zigzag.classes.hardware.architecture.memory_instance import MemoryInstance
+from zigzag.classes.hardware.architecture.accelerator import Accelerator
+from zigzag.classes.hardware.architecture.core import Core
+
+
+def memory_hierarchy_dut(multiplier_array):
+    """Memory hierarchy variables"""
+    ''' size=#bit, bw=(read bw, write bw), cost=(read word energy, write work energy) '''
+
+    reg_IW1 = MemoryInstance(name="rf_1B", size=8, r_bw=8, w_bw=8, r_cost=0.01, w_cost=0.01, area=0,
+                             r_port=1, w_port=1, rw_port=0, latency=1)
+
+    reg_O1 = MemoryInstance(name="rf_2B", size=16, r_bw=16, w_bw=16, r_cost=0.02, w_cost=0.02, area=0,
+                            r_port=2, w_port=2, rw_port=0, latency=1)
+
+    ##################################### on-chip memory hierarchy building blocks #####################################
+
+    sram_16K_with_16_1K_bank_128_1r_1w = \
+        MemoryInstance(name="sram_16KB_A", size=1024 * 16 * 8, r_bw=128 * 16, w_bw=128 * 16, r_cost=1.7 * 16, w_cost=2.52 * 16, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_16KB_512_1r_1w = \
+        MemoryInstance(name="sram_16KB_W", size=16384 * 8, r_bw=512, w_bw=512, r_cost=19.4, w_cost=33.9, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_1M_with_8_128K_bank_128_1r_1w_A = \
+        MemoryInstance(name="sram_1MB_A", size=131072 * 8 * 8, r_bw=128 * 8, w_bw=128 * 8, r_cost=26.01 * 8, w_cost=23.65 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_1M_with_8_128K_bank_128_1r_1w_W = \
+        MemoryInstance(name="sram_1MB_W", size=131072 * 8 * 8, r_bw=128 * 8, w_bw=128 * 8, r_cost=26.01 * 8, w_cost=23.65 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    #######################################################################################################################
+
+    dram = MemoryInstance(name="dram", size=10000000000, r_bw=64, w_bw=64, r_cost=700, w_cost=750, area=0,
+                          r_port=0, w_port=0, rw_port=1, latency=1)
+
+    memory_hierarchy_graph = MemoryHierarchy(operational_array=multiplier_array)
+
+    '''
+    fh: from high = wr_in_by_high 
+    fl: from low = wr_in_by_low 
+    th: to high = rd_out_to_high
+    tl: to low = rd_out_to_low
+    '''
+    # we don't have unrolled I-Reg to better support G unrolling
+    # memory_hierarchy_graph.add_memory(memory_instance=reg_IW1, operands=('I1',),
+    #                                   port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+    #                                   served_dimensions={(0, 0, 0, 0)})
+    memory_hierarchy_graph.add_memory(memory_instance=reg_IW1, operands=('I2',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+                                      served_dimensions={(0, 0, 1, 0), (0, 0, 0, 1)})
+    memory_hierarchy_graph.add_memory(memory_instance=reg_O1, operands=('O',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': 'w_port_2', 'th': 'r_port_2'},),
+                                      served_dimensions={(0, 1, 0, 0)})
+
+    ##################################### on-chip highest memory hierarchy initialization #####################################
+
+    memory_hierarchy_graph.add_memory(memory_instance=sram_16KB_512_1r_1w, operands=('I2',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+                                      served_dimensions='all')
+    memory_hierarchy_graph.add_memory(memory_instance=sram_1M_with_8_128K_bank_128_1r_1w_W, operands=('I2',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+                                      served_dimensions='all')
+    memory_hierarchy_graph.add_memory(memory_instance=sram_16K_with_16_1K_bank_128_1r_1w, operands=('I1', 'O'),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': 'w_port_1', 'th': 'r_port_1'},),
+                                      served_dimensions='all')
+    memory_hierarchy_graph.add_memory(memory_instance=sram_1M_with_8_128K_bank_128_1r_1w_A, operands=('I1', 'O'),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': 'w_port_1', 'th': 'r_port_1'},),
+                                      served_dimensions='all')
+    ####################################################################################################################
+
+    memory_hierarchy_graph.add_memory(memory_instance=dram, operands=('I1', 'I2', 'O'),
+                                      port_alloc=({'fh': 'rw_port_1', 'tl': 'rw_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'rw_port_1', 'tl': 'rw_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'rw_port_1', 'tl': 'rw_port_1', 'fl': 'rw_port_1', 'th': 'rw_port_1'},),
+                                      served_dimensions='all')
+
+    from zigzag.visualization.graph.memory_hierarchy import visualize_memory_hierarchy_graph
+    # visualize_memory_hierarchy_graph(memory_hierarchy_graph)
+    return memory_hierarchy_graph
+
+
+def multiplier_array_dut():
+    """ Multiplier array variables """
+    multiplier_input_precision = [8, 8]
+    multiplier_energy = 0.04
+    multiplier_area = 1
+    dimensions = {'D1': 8, 'D2': 8, 'D3': 4, 'D4': 4}  # {'D1': ('K', 8), 'D2': ('C', 8), 'D3': ('OX', 4), 'D4': ('OY', 4),}
+
+    multiplier = Multiplier(multiplier_input_precision, multiplier_energy, multiplier_area)
+    multiplier_array = MultiplierArray(multiplier, dimensions)
+
+    return multiplier_array
+
+
+def cores():
+    multiplier_array1 = multiplier_array_dut()
+    memory_hierarchy1 = memory_hierarchy_dut(multiplier_array1)
+
+    core1 = Core(1, multiplier_array1, memory_hierarchy1)
+
+    return {core1}
+
+
+cores = cores()
+global_buffer = None
+acc_name = os.path.basename(__file__)[:-3]
+accelerator = Accelerator(acc_name, cores, global_buffer)
+
+a = 1

zigzag-dse-2.2.1/inputs/examples/hardware/Meta_prototype_DF.py

@@ -0,0 +1,121 @@
+import os
+from zigzag.classes.hardware.architecture.memory_hierarchy import MemoryHierarchy
+from zigzag.classes.hardware.architecture.memory_level import MemoryLevel
+from zigzag.classes.hardware.architecture.operational_unit import Multiplier
+from zigzag.classes.hardware.architecture.operational_array import MultiplierArray
+from zigzag.classes.hardware.architecture.memory_instance import MemoryInstance
+from zigzag.classes.hardware.architecture.accelerator import Accelerator
+from zigzag.classes.hardware.architecture.core import Core
+
+
+def memory_hierarchy_dut(multiplier_array):
+    """Memory hierarchy variables"""
+    ''' size=#bit, bw=(read bw, write bw), cost=(read word energy, write work energy) '''
+
+    reg_IW1 = MemoryInstance(name="rf_1B", size=8, r_bw=8, w_bw=8, r_cost=0.01, w_cost=0.01, area=0,
+                             r_port=1, w_port=1, rw_port=0, latency=1)
+
+    reg_O1 = MemoryInstance(name="rf_2B", size=16, r_bw=16, w_bw=16, r_cost=0.02, w_cost=0.02, area=0,
+                            r_port=2, w_port=2, rw_port=0, latency=1)
+
+    ##################################### on-chip memory hierarchy building blocks #####################################
+
+    sram_64KB_with_8_8K_64_1r_1w = \
+        MemoryInstance(name="sram_64KB", size=8192 * 8 * 8, r_bw=64 * 8, w_bw=64 * 8, r_cost=3.32 * 8, w_cost=3.85 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_32KB_with_4_8K_128_1r_1w = \
+        MemoryInstance(name="sram_32KB", size=8192 * 4 * 8, r_bw=128 * 4, w_bw=128 * 4, r_cost=4.3 * 4, w_cost=7.1 * 4, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_1M_with_8_128K_bank_128_1r_1w_A = \
+        MemoryInstance(name="sram_1MB_A", size=131072 * 8 * 8, r_bw=128 * 8, w_bw=128 * 8, r_cost=26.01 * 8, w_cost=23.65 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    sram_1M_with_8_128K_bank_128_1r_1w_W = \
+        MemoryInstance(name="sram_1MB_W", size=131072 * 8 * 8, r_bw=128 * 8, w_bw=128 * 8, r_cost=26.01 * 8, w_cost=23.65 * 8, area=0,
+                       r_port=1, w_port=1, rw_port=0, latency=1, min_r_granularity=64, min_w_granularity=64)
+
+    #######################################################################################################################
+
+    dram = MemoryInstance(name="dram", size=10000000000, r_bw=64, w_bw=64, r_cost=700, w_cost=750, area=0,
+                          r_port=0, w_port=0, rw_port=1, latency=1)
+
+    memory_hierarchy_graph = MemoryHierarchy(operational_array=multiplier_array)
+
+    '''
+    fh: from high = wr_in_by_high 
+    fl: from low = wr_in_by_low 
+    th: to high = rd_out_to_high
+    tl: to low = rd_out_to_low
+    '''
+    # we don't have unrolled I-Reg to better support G unrolling
+    # memory_hierarchy_graph.add_memory(memory_instance=reg_IW1, operands=('I1',),
+    #                                   port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+    #                                   served_dimensions={(0, 0, 0, 0)})
+    memory_hierarchy_graph.add_memory(memory_instance=reg_IW1, operands=('I2',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+                                      served_dimensions={(0, 0, 1, 0), (0, 0, 0, 1)})
+    memory_hierarchy_graph.add_memory(memory_instance=reg_O1, operands=('O',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': 'w_port_2', 'th': 'r_port_2'},),
+                                      served_dimensions={(0, 1, 0, 0)})
+
+    ##################################### on-chip highest memory hierarchy initialization #####################################
+
+    memory_hierarchy_graph.add_memory(memory_instance=sram_32KB_with_4_8K_128_1r_1w, operands=('I2',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+                                      served_dimensions='all')
+    memory_hierarchy_graph.add_memory(memory_instance=sram_1M_with_8_128K_bank_128_1r_1w_W, operands=('I2',),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},),
+                                      served_dimensions='all')
+
+    memory_hierarchy_graph.add_memory(memory_instance=sram_64KB_with_8_8K_64_1r_1w, operands=('I1', 'O'),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': 'w_port_1', 'th': 'r_port_1'},),
+                                      served_dimensions='all')
+    memory_hierarchy_graph.add_memory(memory_instance=sram_1M_with_8_128K_bank_128_1r_1w_A, operands=('I1', 'O'),
+                                      port_alloc=({'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'w_port_1', 'tl': 'r_port_1', 'fl': 'w_port_1', 'th': 'r_port_1'},),
+                                      served_dimensions='all')
+
+    ####################################################################################################################
+
+    memory_hierarchy_graph.add_memory(memory_instance=dram, operands=('I1', 'I2', 'O'),
+                                      port_alloc=({'fh': 'rw_port_1', 'tl': 'rw_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'rw_port_1', 'tl': 'rw_port_1', 'fl': None, 'th': None},
+                                                  {'fh': 'rw_port_1', 'tl': 'rw_port_1', 'fl': 'rw_port_1', 'th': 'rw_port_1'},),
+                                      served_dimensions='all')
+
+    from zigzag.visualization.graph.memory_hierarchy import visualize_memory_hierarchy_graph
+    # visualize_memory_hierarchy_graph(memory_hierarchy_graph)
+    return memory_hierarchy_graph
+
+
+def multiplier_array_dut():
+    """ Multiplier array variables """
+    multiplier_input_precision = [8, 8]
+    multiplier_energy = 0.04
+    multiplier_area = 1
+    dimensions = {'D1': 32, 'D2': 2, 'D3': 4, 'D4': 4}  # {'D1': ('K', 32), 'D2': ('C', 2), 'D3': ('OX', 4), 'D4': ('OY', 4),}
+
+    multiplier = Multiplier(multiplier_input_precision, multiplier_energy, multiplier_area)
+    multiplier_array = MultiplierArray(multiplier, dimensions)
+
+    return multiplier_array
+
+
+def cores():
+    multiplier_array1 = multiplier_array_dut()
+    memory_hierarchy1 = memory_hierarchy_dut(multiplier_array1)
+
+    core1 = Core(1, multiplier_array1, memory_hierarchy1)
+
+    return {core1}
+
+
+cores = cores()
+global_buffer = None
+acc_name = os.path.basename(__file__)[:-3]
+accelerator = Accelerator(acc_name, cores, global_buffer)
+
+a = 1