wirestudio 0.44.0__tar.gz → 0.46.0__tar.gz

{wirestudio-0.44.0/wirestudio.egg-info → wirestudio-0.46.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: wirestudio
-Version: 0.44.0
+Version: 0.46.0
 Summary: Agent-driven IoT device design tool that produces ESPHome YAML.
 Author: wirestudio contributors
 License: MIT
@@ -147,8 +147,8 @@ Tiers, in priority order:
 | **Verified** | CSP pin solver + compat checker | assign legal pins, surface boot-strap / ADC2-WiFi / voltage / locked-pin issues | unit tests + property checks in `tests/test_pin_solver.py` + `tests/test_compatibility.py` |
 | **Verified** | Fleet handoff | push YAML to `fleet-for-esphome` ha-addon, optional compile + log relay | round-trip tests in `tests/test_fleet.py` |
 | **Verified** | KiCad schematic | write a KiCad 8 `.kicad_sch` the studio draws itself (board, peripherals, subcircuits drawn as circuits from their library layouts; symbols embedded), plus a SKiDL script for the same design | every bundled example builds a KiCad netlist against the pinned upstream symbol libraries, every PR ([gate](.github/workflows/kicad-schematic.yml)) — no unresolved symbols or pins; kicad-cli reads the netlist back from every written sheet's geometry and it must match the design's, then `kicad-cli sch erc` runs on all of them against a baseline of the violation types the writer cannot avoid ([gate](.github/workflows/kicad-render.yml)). Parts KiCad ships no symbol for (sensor/module breakouts) render as labeled generic headers |
-| **Verified** | KiCad PCB layout | emit a placed, unrouted `.kicad_pcb` — footprints, nets, ratsnest, edge cuts | every bundled example emits a structurally sound board, every PR ([gate](.github/workflows/pcb-layout.yml)); a DRC tier opens each board in real KiCad ([gate](.github/workflows/pcb-drc.yml)) |
-| **Verified** | Fab outputs | JLCPCB upload bundle — BOM, CPL, Gerber + drill (`/design/fab/*`) | CPL positions match the `.kicad_pcb` placement; the DRC tier smoke-tests the Gerber export. Boards are unrouted until the Freerouting step, so Gerbers carry pads but no traces (`is_routed` flags it) |
+| **Verified** | KiCad PCB layout | emit a placed, unrouted `.kicad_pcb` — footprints, nets, ratsnest, edge cuts, and a GND pour on the bottom layer that the route step fills | every bundled example emits a structurally sound board, every PR ([gate](.github/workflows/pcb-layout.yml)); a DRC tier opens each board in real KiCad ([gate](.github/workflows/pcb-drc.yml)) |
+| **Verified** | Fab outputs | JLCPCB upload bundle — BOM, CPL, Gerber + drill (`/design/fab/*`) | CPL positions match the `.kicad_pcb` placement; the DRC tier smoke-tests the Gerber export. `?route=true` routes the board first; without it Gerbers carry pads but no tracks or pour (`is_routed` flags it). The routed gate checks a routed board's B.Cu Gerber carries the GND pour ([gate](.github/workflows/pcb-route.yml)) |
 | **Verified** | Subcircuits + building blocks | a component built from discrete parts (five bundled blocks, two H-bridges) expands into the schematic, PCB, BOM, CPL and inventory check; part values are parametric; each block's `verify.checks` rule runs at `validate` with the real params and rails | goldens for every subcircuit example pin YAML + BOM; `component_check` fails a block whose defaults break its own rule (`tests/test_electrical.py`); the schematic and PCB gates cover the expanded parts like any other |
 | **Verified** | Inventory check | cross-check a design's BOM against the drawer (library modules + discrete parts), propose same-package substitutes ranked by pinout, package, rating headroom and stock, accept one or all of them as `part_overrides` that every fab output honours, pick list by location, buy list priced on JLCPCB | matching, substitution and coverage tests in `tests/test_inventory.py` against the real drawer CSV; JLCPCB pricing is mocked and degrades to an unpriced list when the parts API is down |
 | **Verified** | Parametric enclosure | OpenSCAD `.scad` from board mount-hole metadata, built on [YAPP_Box](https://github.com/mrWheel/YAPP_Box): base and lid with standoffs, port cutouts, a ridge and snap joins | every enclosure-capable board renders through real OpenSCAD to a non-empty, manifold (closed, printable) solid, every PR ([gate](.github/workflows/enclosure-render.yml)) |
@@ -160,12 +160,13 @@ Tiers, in priority order:
 | **Works (lighter checks)** | Meshtastic flashing + config | proxy the official release factory image (`/meshtastic/firmware`) for the radio boards, flash it via the unified WebSerial dialog, then push region, modem preset, owner and primary channel as protobufs over the same port | endpoint tests with mocked upstream; board-to-variant map checked against `meshtastic/firmware` variants; config push tested against a fake device; no live-flash gate |
 | **Works (lighter checks)** | MicroPython flashing + main.py | proxy the official release image for the board's chip (`/micropython/firmware`; every library board maps to a generic port image, ESP8266 included), flash via the unified dialog, generate `main.py` from the design over the `machine` API (`/micropython/code`) and push it through the raw REPL over the same serial port | endpoint tests with a captured download page; every board's starter and every example's main.py parse as Python; the raw-REPL push is tested against a fake board; the micropython.org page format could not be fetched from the build session, so the first live flash validates it; no live-flash gate |
 | **Verified** | Component authoring | write a component YAML in the studio or through `component_create`; the same gate as `component_check` (schema, subcircuit nets, template render, KiCad symbols / pins / footprint) before it lands in the user library | a user-authored component goes through the gate and its synthetic design through upstream `esphome config`, every PR ([gate](.github/workflows/esphome-config.yml)); the gate rejects every file in a corpus of bad components for the named reason (`tests/test_component_corpus.py`); KiCad resolution runs only where the toolchain is present |
+| **Verified** | Board authoring | write a board YAML in the studio or through `board_create`; the same gate as `board_check` (schema, every bus / onboard / radio pin against `gpio_capabilities`, KiCad symbol pins and footprint, enclosure geometry, ESPHome's board table, an ESPHome render with the onboard peripherals) before it lands in the user library | every bundled board passes the gate (`tests/test_board_check.py`); a user-authored board with its onboard peripherals goes through upstream `esphome config`, every PR ([gate](.github/workflows/esphome-config.yml)); the pinout is not checked against the datasheet |
 | **Verified** | ESPHome dashboard compile | push the rendered YAML to a running ESPHome Device Builder (`/esphome/push`), start a compile there, stream the log and serve the firmware, with the same job shapes as the fleet path | nightly, against a live Device Builder (ESPHome 2026.10.0) open and password-protected: push, compile over the WebSocket API, fetch the image, with the client's wire assumptions asserted ([dashboard](.github/workflows/esphome-compile.yml)); client + route tests against a fake of the same in `tests/test_esphome_dashboard.py` |
 | **Works (lighter checks)** | CircuitPython flashing | proxy the official release image (`/circuitpython/firmware`) for ESP32/S3/C3/C6 boards, flash via the unified dialog, serve a generated starter `code.py` (`/circuitpython/code`) | endpoint tests with mocked upstream; every board-id mapping verified against downloads.circuitpython.org; generated starters parse as valid Python; no live-flash gate |
 | **Verified** | MCP server | 53 tools over the Model Context Protocol: 31 design / library / inventory / fab, plus 22 that reach hardware — workbench flash and boot verification, LoRaWAN compile / provision / activation, fleet and dashboard push + build status, and job polling for the long ones | the `mcp` package's own client connects to the mounted server over Streamable HTTP with the bearer token, lists the tools, drives a design from `create_design` to `render` and reads a resource, every PR (`tests/test_mcp_client.py`); tool / auth / resource tests in `tests/test_mcp_*.py`; the hardware tools drive the real clients against wire-level fakes, and were exercised against a live bench, ChirpStack and fleet during bring-up |
 | **Experimental** | Thingiverse search relay | rank community models for a board | smoke-tested; depends on a third-party search API that ranks unevenly |
 | **Verified** | Agent (Claude tool-using) | natural-language design driving | scored nightly against the 28-task list in `wirestudio/agent/eval_tasks.yaml`: the design it hands back passes `esphome config`, carries the asked-for change, and the turn stayed within its tool-call budget ([gate](.github/workflows/agent-eval.yml)); every task's reference solution passes the same scorer on every PR (`tests/test_agent_eval.py`). The nightly run drives the studio through Claude Code over MCP with the `CLAUDE_CODE_OAUTH_TOKEN` secret (a subscription); the embedded agent is scored too when `ANTHROPIC_API_KEY` is set. Each driver's first scored run sets its gate |
-| **Verified** | PCB autorouting | Freerouting roundtrip — board → Specctra DSN → routed → SES import; SSE route endpoint, `route_pcb` MCP/agent tool, web-UI Route button, `?route=true` fab exports, `-pcb` image variant | representative examples route with zero unconnected items and pass routed DRC ([gate](.github/workflows/pcb-route.yml)) |
+| **Verified** | PCB autorouting | Freerouting roundtrip — board → Specctra DSN → routed → SES import, GND pour filled; via cost and keepout rectangles as parameters; KiCad's DRC of the routed board reported back; SSE route endpoint, `route_pcb` MCP/agent tool, web-UI Route button, `?route=true` fab exports, `-pcb` image variant | representative examples route with zero unconnected items, a filled pour and a clean routed DRC; a high via cost must remove vias and a keepout must clear the track under it ([gate](.github/workflows/pcb-route.yml)) |
 
 The **Verified** tier is the bar the project is asking to be judged
 on. Everything else is offered with the caveat that's spelled out in

{wirestudio-0.44.0 → wirestudio-0.46.0}/README.md

@@ -113,8 +113,8 @@ Tiers, in priority order:
 | **Verified** | CSP pin solver + compat checker | assign legal pins, surface boot-strap / ADC2-WiFi / voltage / locked-pin issues | unit tests + property checks in `tests/test_pin_solver.py` + `tests/test_compatibility.py` |
 | **Verified** | Fleet handoff | push YAML to `fleet-for-esphome` ha-addon, optional compile + log relay | round-trip tests in `tests/test_fleet.py` |
 | **Verified** | KiCad schematic | write a KiCad 8 `.kicad_sch` the studio draws itself (board, peripherals, subcircuits drawn as circuits from their library layouts; symbols embedded), plus a SKiDL script for the same design | every bundled example builds a KiCad netlist against the pinned upstream symbol libraries, every PR ([gate](.github/workflows/kicad-schematic.yml)) — no unresolved symbols or pins; kicad-cli reads the netlist back from every written sheet's geometry and it must match the design's, then `kicad-cli sch erc` runs on all of them against a baseline of the violation types the writer cannot avoid ([gate](.github/workflows/kicad-render.yml)). Parts KiCad ships no symbol for (sensor/module breakouts) render as labeled generic headers |
-| **Verified** | KiCad PCB layout | emit a placed, unrouted `.kicad_pcb` — footprints, nets, ratsnest, edge cuts | every bundled example emits a structurally sound board, every PR ([gate](.github/workflows/pcb-layout.yml)); a DRC tier opens each board in real KiCad ([gate](.github/workflows/pcb-drc.yml)) |
-| **Verified** | Fab outputs | JLCPCB upload bundle — BOM, CPL, Gerber + drill (`/design/fab/*`) | CPL positions match the `.kicad_pcb` placement; the DRC tier smoke-tests the Gerber export. Boards are unrouted until the Freerouting step, so Gerbers carry pads but no traces (`is_routed` flags it) |
+| **Verified** | KiCad PCB layout | emit a placed, unrouted `.kicad_pcb` — footprints, nets, ratsnest, edge cuts, and a GND pour on the bottom layer that the route step fills | every bundled example emits a structurally sound board, every PR ([gate](.github/workflows/pcb-layout.yml)); a DRC tier opens each board in real KiCad ([gate](.github/workflows/pcb-drc.yml)) |
+| **Verified** | Fab outputs | JLCPCB upload bundle — BOM, CPL, Gerber + drill (`/design/fab/*`) | CPL positions match the `.kicad_pcb` placement; the DRC tier smoke-tests the Gerber export. `?route=true` routes the board first; without it Gerbers carry pads but no tracks or pour (`is_routed` flags it). The routed gate checks a routed board's B.Cu Gerber carries the GND pour ([gate](.github/workflows/pcb-route.yml)) |
 | **Verified** | Subcircuits + building blocks | a component built from discrete parts (five bundled blocks, two H-bridges) expands into the schematic, PCB, BOM, CPL and inventory check; part values are parametric; each block's `verify.checks` rule runs at `validate` with the real params and rails | goldens for every subcircuit example pin YAML + BOM; `component_check` fails a block whose defaults break its own rule (`tests/test_electrical.py`); the schematic and PCB gates cover the expanded parts like any other |
 | **Verified** | Inventory check | cross-check a design's BOM against the drawer (library modules + discrete parts), propose same-package substitutes ranked by pinout, package, rating headroom and stock, accept one or all of them as `part_overrides` that every fab output honours, pick list by location, buy list priced on JLCPCB | matching, substitution and coverage tests in `tests/test_inventory.py` against the real drawer CSV; JLCPCB pricing is mocked and degrades to an unpriced list when the parts API is down |
 | **Verified** | Parametric enclosure | OpenSCAD `.scad` from board mount-hole metadata, built on [YAPP_Box](https://github.com/mrWheel/YAPP_Box): base and lid with standoffs, port cutouts, a ridge and snap joins | every enclosure-capable board renders through real OpenSCAD to a non-empty, manifold (closed, printable) solid, every PR ([gate](.github/workflows/enclosure-render.yml)) |
@@ -126,12 +126,13 @@ Tiers, in priority order:
 | **Works (lighter checks)** | Meshtastic flashing + config | proxy the official release factory image (`/meshtastic/firmware`) for the radio boards, flash it via the unified WebSerial dialog, then push region, modem preset, owner and primary channel as protobufs over the same port | endpoint tests with mocked upstream; board-to-variant map checked against `meshtastic/firmware` variants; config push tested against a fake device; no live-flash gate |
 | **Works (lighter checks)** | MicroPython flashing + main.py | proxy the official release image for the board's chip (`/micropython/firmware`; every library board maps to a generic port image, ESP8266 included), flash via the unified dialog, generate `main.py` from the design over the `machine` API (`/micropython/code`) and push it through the raw REPL over the same serial port | endpoint tests with a captured download page; every board's starter and every example's main.py parse as Python; the raw-REPL push is tested against a fake board; the micropython.org page format could not be fetched from the build session, so the first live flash validates it; no live-flash gate |
 | **Verified** | Component authoring | write a component YAML in the studio or through `component_create`; the same gate as `component_check` (schema, subcircuit nets, template render, KiCad symbols / pins / footprint) before it lands in the user library | a user-authored component goes through the gate and its synthetic design through upstream `esphome config`, every PR ([gate](.github/workflows/esphome-config.yml)); the gate rejects every file in a corpus of bad components for the named reason (`tests/test_component_corpus.py`); KiCad resolution runs only where the toolchain is present |
+| **Verified** | Board authoring | write a board YAML in the studio or through `board_create`; the same gate as `board_check` (schema, every bus / onboard / radio pin against `gpio_capabilities`, KiCad symbol pins and footprint, enclosure geometry, ESPHome's board table, an ESPHome render with the onboard peripherals) before it lands in the user library | every bundled board passes the gate (`tests/test_board_check.py`); a user-authored board with its onboard peripherals goes through upstream `esphome config`, every PR ([gate](.github/workflows/esphome-config.yml)); the pinout is not checked against the datasheet |
 | **Verified** | ESPHome dashboard compile | push the rendered YAML to a running ESPHome Device Builder (`/esphome/push`), start a compile there, stream the log and serve the firmware, with the same job shapes as the fleet path | nightly, against a live Device Builder (ESPHome 2026.10.0) open and password-protected: push, compile over the WebSocket API, fetch the image, with the client's wire assumptions asserted ([dashboard](.github/workflows/esphome-compile.yml)); client + route tests against a fake of the same in `tests/test_esphome_dashboard.py` |
 | **Works (lighter checks)** | CircuitPython flashing | proxy the official release image (`/circuitpython/firmware`) for ESP32/S3/C3/C6 boards, flash via the unified dialog, serve a generated starter `code.py` (`/circuitpython/code`) | endpoint tests with mocked upstream; every board-id mapping verified against downloads.circuitpython.org; generated starters parse as valid Python; no live-flash gate |
 | **Verified** | MCP server | 53 tools over the Model Context Protocol: 31 design / library / inventory / fab, plus 22 that reach hardware — workbench flash and boot verification, LoRaWAN compile / provision / activation, fleet and dashboard push + build status, and job polling for the long ones | the `mcp` package's own client connects to the mounted server over Streamable HTTP with the bearer token, lists the tools, drives a design from `create_design` to `render` and reads a resource, every PR (`tests/test_mcp_client.py`); tool / auth / resource tests in `tests/test_mcp_*.py`; the hardware tools drive the real clients against wire-level fakes, and were exercised against a live bench, ChirpStack and fleet during bring-up |
 | **Experimental** | Thingiverse search relay | rank community models for a board | smoke-tested; depends on a third-party search API that ranks unevenly |
 | **Verified** | Agent (Claude tool-using) | natural-language design driving | scored nightly against the 28-task list in `wirestudio/agent/eval_tasks.yaml`: the design it hands back passes `esphome config`, carries the asked-for change, and the turn stayed within its tool-call budget ([gate](.github/workflows/agent-eval.yml)); every task's reference solution passes the same scorer on every PR (`tests/test_agent_eval.py`). The nightly run drives the studio through Claude Code over MCP with the `CLAUDE_CODE_OAUTH_TOKEN` secret (a subscription); the embedded agent is scored too when `ANTHROPIC_API_KEY` is set. Each driver's first scored run sets its gate |
-| **Verified** | PCB autorouting | Freerouting roundtrip — board → Specctra DSN → routed → SES import; SSE route endpoint, `route_pcb` MCP/agent tool, web-UI Route button, `?route=true` fab exports, `-pcb` image variant | representative examples route with zero unconnected items and pass routed DRC ([gate](.github/workflows/pcb-route.yml)) |
+| **Verified** | PCB autorouting | Freerouting roundtrip — board → Specctra DSN → routed → SES import, GND pour filled; via cost and keepout rectangles as parameters; KiCad's DRC of the routed board reported back; SSE route endpoint, `route_pcb` MCP/agent tool, web-UI Route button, `?route=true` fab exports, `-pcb` image variant | representative examples route with zero unconnected items, a filled pour and a clean routed DRC; a high via cost must remove vias and a keepout must clear the track under it ([gate](.github/workflows/pcb-route.yml)) |
 
 The **Verified** tier is the bar the project is asking to be judged
 on. Everything else is offered with the caveat that's spelled out in

{wirestudio-0.44.0 → wirestudio-0.46.0}/tests/test_api_route.py

@@ -99,3 +99,9 @@ def test_fab_gerbers_route_unavailable_is_503(client, monkeypatch):
 def test_fab_status_reports_route(client):
     body = client.get("/design/fab/status").json()
     assert "route" in body and "route_reason" in body
+
+
+def test_route_bad_params_are_422(client, toolchain):
+    for query in ("keepout=1,2,3", "keepout=1,2,3,4,pads", "via_costs=-5", "passes=0"):
+        resp = client.post(f"/design/kicad/route?{query}", json=_design())
+        assert resp.status_code == 422, query

wirestudio-0.46.0/tests/test_board_check.py

@@ -0,0 +1,205 @@
+"""Checking and creating library boards at runtime."""
+from __future__ import annotations
+
+from pathlib import Path
+
+import pytest
+from fastapi.testclient import TestClient
+
+from wirestudio.api.app import create_app
+from wirestudio.library import Library
+from wirestudio.library.board_check import check_board_yaml, create_board
+
+BUNDLED = Path(__file__).resolve().parent.parent / "wirestudio" / "library"
+DRAFT = (Path(__file__).resolve().parent / "fixtures" / "boards" / "lolin-s2-mini.yaml").read_text()
+DEVKIT = (BUNDLED / "boards" / "esp32-devkitc-v4.yaml").read_text()
+C3 = (BUNDLED / "boards" / "esp32-c3-devkitm-1.yaml").read_text()
+
+
+@pytest.fixture
+def lib(tmp_path):
+    return Library(BUNDLED, tmp_path / "user")
+
+
+@pytest.fixture
+def client(tmp_path):
+    return TestClient(create_app(library=Library(BUNDLED, tmp_path / "user")))
+
+
+def _errors(text: str, lib: Library) -> str:
+    return " | ".join(check_board_yaml(text, lib).errors)
+
+
+def test_every_bundled_board_passes(lib):
+    for path in sorted((BUNDLED / "boards").glob("*.yaml")):
+        report = check_board_yaml(path.read_text(), lib)
+        assert report.ok, (path.stem, report.errors)
+        assert report.exists == "bundled"
+
+
+def test_draft_passes_and_renders_its_onboard_parts(lib):
+    report = check_board_yaml(DRAFT, lib)
+    assert report.ok, report.errors
+    assert report.library_id == "lolin-s2-mini" and report.exists == ""
+    assert any("gpio_output, gpio_input" in v for v in report.verified)
+    assert any("34.3 x 25.4" in v for v in report.verified)
+    assert any("no kicad: block" in w for w in report.warnings)
+    assert any("datasheet" in n for n in report.not_checked)
+
+
+def test_unparseable_and_invalid_files_are_reported(lib):
+    assert "not valid YAML" in _errors("id: [", lib)
+    assert "top level must be a mapping" in _errors("- a", lib)
+    assert "platformio_board" in _errors(DRAFT.replace("platformio_board: lolin_s2_mini\n", ""), lib)
+    assert "names the file" in _errors(DRAFT.replace("id: lolin-s2-mini", "id: Lolin S2"), lib)
+
+
+def test_platform_fields_must_agree(lib):
+    assert "not an ESP32 variant" in _errors(DRAFT.replace("chip_variant: esp32s2", "chip_variant: esp32s9"), lib)
+    assert "needs mcu esp32" in _errors(DRAFT.replace("mcu: esp32\n", "mcu: esp8266\n"), lib)
+    assert "not an ESPHome platform" in _errors(DRAFT.replace("chip_variant: esp32s2", "chip_variant: stm32"), lib)
+    assert "framework" in _errors(DRAFT.replace("framework: arduino", "framework: zephyr"), lib)
+
+
+def test_every_named_pin_must_be_a_gpio(lib):
+    errors = _errors(DRAFT.replace("sda: GPIO33", "sda: GPIO34").replace("pin: GPIO15", "pin: GPIO14"), lib)
+    assert "default_buses.i2c.sda: GPIO34 is not in gpio_capabilities" in errors
+    assert "onboard_peripherals.led.pin: GPIO14 is not in gpio_capabilities" in errors
+    assert "no scl pin" in _errors(DRAFT.replace(", scl: GPIO35", ""), lib)
+    assert "unknown bus type" in _errors(DRAFT.replace("  spi: {", "  qspi: {"), lib)
+    assert "no GND rail" in _errors(DRAFT.replace('  - {name: "GND", voltage: 0.0}\n', ""), lib)
+
+
+def test_an_input_only_pin_cannot_drive_a_bus_line(lib):
+    text = DRAFT.replace("GPIO33: [gpio, pwm, i2c_sda]", "GPIO33: [gpio, input_only]")
+    assert "GPIO33 is input_only and cannot drive sda" in _errors(text, lib)
+
+
+def test_radio_pins_are_cross_checked(lib):
+    heltec = (BUNDLED / "boards" / "heltec-wifi-lora32-v2.yaml").read_text()
+    assert check_board_yaml(heltec, lib).ok
+    broken = heltec.replace("pins: {cs: GPIO18", "pins: {cs: GPIO99")
+    assert broken != heltec
+    assert "radio.pins.cs: GPIO99" in _errors(broken, lib)
+
+
+def test_enclosure_geometry_stays_on_the_pcb(lib):
+    off = DRAFT.replace("offset_mm: 8.95", "offset_mm: 20.0")
+    assert "runs off the 25.4 mm short_a edge" in _errors(off, lib)
+    edge = DRAFT.replace("edge: short_a", "edge: top")
+    assert "edge 'top'" in _errors(edge, lib)
+
+
+def test_pin_map_is_checked_against_the_symbol(lib, tmp_path, monkeypatch):
+    symdir = tmp_path / "symbols"
+    symdir.mkdir()
+    pins = " ".join(
+        f'(pin passive line (at 0 0 0) (length 2.54) (name "Pin_{n}") (number "{n}"))' for n in range(1, 31))
+    (symdir / "Connector_Generic.kicad_sym").write_text(
+        '(kicad_symbol_lib (version 20231120) (generator kicad_symbol_editor)'
+        f' (symbol "Conn_02x15_Odd_Even" {pins}))')
+    monkeypatch.setenv("KICAD8_SYMBOL_DIR", str(symdir))
+    report = check_board_yaml(C3, lib)
+    assert report.ok, report.errors
+    assert any("has every pin_map pin" in v for v in report.verified)
+
+    assert "has no pin '31'" in _errors(C3.replace('GPIO1: "19"', 'GPIO1: "31"'), lib)
+    assert "GPIO1 and GPIO0 share pin 17, which would short them" in _errors(C3.replace('GPIO1: "19"', 'GPIO1: "17"'), lib)
+    assert "no symbol 'Conn_02x20'" in _errors(C3.replace("Conn_02x15_Odd_Even", "Conn_02x20"), lib)
+    assert "symbol library 'RF_Module' not found" in _errors(DEVKIT, lib)
+
+
+def test_create_saves_into_the_user_library_only(lib, tmp_path):
+    report = create_board(DRAFT, lib)
+    assert report.ok and report.saved.endswith("user/boards/lolin-s2-mini.yaml")
+    assert Path(report.saved).read_text() == DRAFT
+    assert lib.board_source("lolin-s2-mini") == "user"
+    assert lib.board("lolin-s2-mini").chip_variant == "esp32s2"
+    assert "lolin-s2-mini" in [b.id for b in lib.list_boards()]
+
+    again = create_board(DRAFT, lib)
+    assert not again.ok and any("already exists" in e for e in again.errors)
+    assert create_board(DRAFT, lib, overwrite=True).ok
+
+    bundled = create_board(DEVKIT, lib)
+    assert not bundled.ok and any("bundled board" in e for e in bundled.errors)
+    assert not (tmp_path / "user" / "boards" / "esp32-devkitc-v4.yaml").exists()
+
+    with pytest.raises(PermissionError):
+        lib.delete_board("esp32-devkitc-v4")
+    lib.delete_board("lolin-s2-mini")
+    assert lib.board_source("lolin-s2-mini") == ""
+    with pytest.raises(FileNotFoundError):
+        lib.board("lolin-s2-mini")
+
+    assert not create_board(DRAFT, Library(BUNDLED)).ok  # no user dir configured
+
+
+def test_a_bundled_board_wins_over_a_user_file(lib, tmp_path):
+    (tmp_path / "user" / "boards").mkdir(parents=True)
+    (tmp_path / "user" / "boards" / "esp32-devkitc-v4.yaml").write_text(DRAFT.replace("lolin-s2-mini", "esp32-devkitc-v4"))
+    assert lib.board_source("esp32-devkitc-v4") == "bundled"
+    assert lib.board("esp32-devkitc-v4").chip_variant == "esp32"
+    assert [b.id for b in lib.list_boards()].count("esp32-devkitc-v4") == 1
+
+
+def test_user_board_flows_into_a_design(lib):
+    from wirestudio.generate.yaml_gen import render_yaml
+    from wirestudio.model import Design
+
+    assert create_board(DRAFT, lib).ok
+    design = Design.model_validate({
+        "schema_version": "0.1", "id": "t", "name": "t",
+        "board": {"library_id": "lolin-s2-mini", "mcu": "esp32"},
+        "power": {"supply": "usb-5v", "rail_voltage_v": 5.0, "budget_ma": 500},
+        "components": [{"id": "led", "library_id": "gpio_output", "label": "LED"}],
+        "buses": [], "requirements": [], "warnings": [],
+        "connections": [
+            {"component_id": "led", "pin_role": "OUT", "target": {"kind": "gpio", "pin": "GPIO15"}},
+        ],
+    })
+    rendered = render_yaml(design, lib)
+    assert "board: lolin_s2_mini" in rendered and "variant: ESP32S2" in rendered
+    assert "pin: GPIO15" in rendered
+
+
+def test_api_round_trip(client):
+    check = client.post("/library/boards/check", json={"yaml": DRAFT})
+    assert check.status_code == 200 and check.json()["ok"]
+
+    created = client.post("/library/boards", json={"yaml": DRAFT})
+    assert created.status_code == 201 and created.json()["saved"]
+    listed = {b["id"]: b for b in client.get("/library/boards").json()}
+    assert listed["lolin-s2-mini"]["source"] == "user"
+    assert listed["esp32-devkitc-v4"]["source"] == "bundled"
+    assert client.get("/library/boards/lolin-s2-mini").json()["chip_variant"] == "esp32s2"
+    assert client.get("/library/boards/lolin-s2-mini/yaml").text == DRAFT
+
+    assert client.post("/library/boards", json={"yaml": DRAFT}).status_code == 409
+    assert client.post("/library/boards", json={"yaml": DEVKIT}).status_code == 409
+    bad = client.post("/library/boards", json={"yaml": DRAFT.replace("pin: GPIO15", "pin: GPIO14")})
+    assert bad.status_code == 422 and not bad.json()["ok"]
+
+    assert client.delete("/library/boards/esp32-devkitc-v4").status_code == 409
+    assert client.delete("/library/boards/lolin-s2-mini").status_code == 200
+    assert client.delete("/library/boards/lolin-s2-mini").status_code == 404
+    assert "lolin-s2-mini" not in {b["id"] for b in client.get("/library/boards").json()}
+
+
+def test_agent_tools(lib):
+    from wirestudio.agent.tools import _run_board_check, _run_board_create, _run_board_delete, _run_list_boards
+
+    assert _run_board_check({}, lib, yaml=DRAFT)["ok"]
+    assert _run_board_create({}, lib, yaml=DRAFT)["saved"]
+    sources = {b["library_id"]: b["source"] for b in _run_list_boards({}, lib)["boards"]}
+    assert sources["lolin-s2-mini"] == "user"
+    assert _run_board_delete({}, lib, library_id="lolin-s2-mini")["ok"]
+    assert not _run_board_delete({}, lib, library_id="esp32-devkitc-v4")["ok"]
+
+
+def test_platformio_board_is_looked_up_in_esphome(lib):
+    pytest.importorskip("esphome")
+    assert any("lolin_s2_mini is an ESPHome esp32 board" in v for v in check_board_yaml(DRAFT, lib).verified)
+    unknown = check_board_yaml(DRAFT.replace("lolin_s2_mini", "no_such_board"), lib)
+    assert unknown.ok and any("not in ESPHome's esp32 board list" in w for w in unknown.warnings)
+    assert "is an esp32c3 board in ESPHome, not esp32s2" in _errors(DRAFT.replace("lolin_s2_mini", "esp32-c3-devkitm-1"), lib)