vagen 0.0.1__tar.gz

vagen-0.0.1/LICENSE

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+MIT License
+
+Copyright (c) 2023 Rodrigo Pedroso Mendes
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

vagen-0.0.1/PKG-INFO

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+Metadata-Version: 2.1
+Name: vagen
+Version: 0.0.1
+Summary: Generates verilogA testbench for verification of analog IPs (VLSI design)
+Author-email: Rodrigo Pedroso Mendes <roedroso@gmail.com>
+Project-URL: Homepage, https://github.com/rpm2003rpm/vagen
+Classifier: Programming Language :: Python :: 3
+Classifier: License :: OSI Approved :: MIT License
+Classifier: Operating System :: OS Independent
+Requires-Python: >=3.7
+Description-Content-Type: text/markdown
+License-File: LICENSE
+Requires-Dist: regex>=2023.6.3
+Requires-Dist: datetime>=5.2
+
+# vagen
+
+## What is vagen?
+
+vagen was created mainly to generate verilogA stimulus for verification of complex analog IPs. However, it has wrappers for most of the verilogA reserved words, so it also generates verilogA models.
+
+## Instalation 
+
+You can install vagen by typing the command:
+
+```
+    pip3 install vagen
+```
+
+## Example 1: Stimulus for verification of a DCDC
+
+Let's assume that a stimulus with the following sequence is required:
+
+* VDD must rise from 0 to 5.0V in 10us.
+* After 10us, the clock signal (CLK) must start with a frequency of 4MHz. CLK domain is VDD.
+* After 1us, RST must rise. RST domain is VDD.
+* Wait for the positive edge of the signal READY when it crosses half of the domain voltage. READY domain is VDD. 
+* A current of 100mA must be drawn from the in OUT with a rise time of 100ns. 
+* After 10us, the bus CONFIG_VOUT[3:0] must be changed from 0 to 5. CONFIG_VOUT[3:0] domain is VDD.
+* After 20us, finishes the simulation. 
+
+The python code that generates this stimulus is shown below:
+
+```
+import vagen as va
+
+#Create a module     
+mod = va.HiLevelMod("DCDC_STML")
+
+#Create pins
+VDD = mod.vdc(name = "VDD", width = 1, direction = "inout")
+OUT = mod.idc(name = "OUT", width = 1, direction = "inout")
+CLK = mod.clock(mod.dig(name = "CLK", domain = VDD, width = 1, direction = "output", rise = 100e-15, fall = 100e-15))
+RST = mod.dig(name = "RST", domain = VDD, width = 1, value = 0, direction = "output", rise = 100e-15, fall = 100e-15)
+READY = mod.dig(name = "READY", domain = VDD, width = 1, direction = "input")
+CONFIG_VOUT = mod.dig(name = "CONFIG_VOUT", domain = VDD, width = 4, value = 0, direction = "output", rise = 100e-15, fall = 100e-15)
+
+#READY positive event
+EVNT_READY = va.Cross(READY.diffHalfDomain, "rising")
+
+#Sequence
+mod.seq(True)(
+    VDD.setRiseFall(10e-6, 10e-6),
+    VDD.applyV(5.0),
+    va.WaitUs(10), 
+    CLK.on(4e6),
+    va.WaitUs(1),
+    RST.write(True),
+    va.WaitSignal(EVNT_READY),
+    OUT.setRiseFall(100e-9, 100e-9),
+    OUT.applyI(100e-3), #Positive current enters the model
+    va.WaitUs(10),
+    CONFIG_VOUT.write(5),
+    va.WaitUs(20),
+    va.Finish()
+)
+
+#Save veriloga file
+file = open('veriloga.va', 'w')
+file.write(mod.getVA())
+file.close()
+```
+
+## Example 2: More than one sequence in the same veriloga
+
+You can create a veriloga parameter called testSeq
+
+```
+seqPar = mod.par(name = "testSeq", value = 0)
+```
+
+And then use this parameter to select the sequence depending on the value
+
+```
+#sequence 1 
+mod.seq(seqPar == 1)(
+...
+)
+
+#sequence 2
+mod.seq(seqPar == 2)(
+...
+)
+```
+
+## Example 3: Model of a configurable resistor
+
+As mentioned before, vagen can be used to generate models. As an example, the code below generates a veriloga model of a configurable resistor.
+
+```
+import vagen as va
+
+#Create a module
+mod = va.HiLevelMod("CONFIG_RES")
+
+#Create pins
+VDD = mod.electrical(name = "VDD", width = 1, direction = "inout")
+IN1 = mod.electrical(name = "IN1", width = 1, direction = "inout")
+IN2 = mod.electrical(name = "IN2", width = 1, direction = "inout")
+CONFIG = mod.dig(name = "CONFIG", domain = VDD, width = 4, value = 0, inCap = 100e-15, direction = "input")
+
+#Parameters
+alfa = mod.par(name = "alfa", value = 10.0)
+
+#Analog block
+mod.analog(
+    va.Branch(IN1, IN2).vCont(va.Branch(IN1, IN2).i*(va.Real(CONFIG.read(signed = False)) + 1)*alfa)
+)
+
+#Save veriloga file
+file = open('veriloga.va', 'w')
+file.write(mod.getVA())
+file.close()
+```
+
+# More examples
+Extra examples will be added to examples folder

vagen-0.0.1/README.md

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+# vagen
+
+## What is vagen?
+
+vagen was created mainly to generate verilogA stimulus for verification of complex analog IPs. However, it has wrappers for most of the verilogA reserved words, so it also generates verilogA models.
+
+## Instalation 
+
+You can install vagen by typing the command:
+
+```
+    pip3 install vagen
+```
+
+## Example 1: Stimulus for verification of a DCDC
+
+Let's assume that a stimulus with the following sequence is required:
+
+* VDD must rise from 0 to 5.0V in 10us.
+* After 10us, the clock signal (CLK) must start with a frequency of 4MHz. CLK domain is VDD.
+* After 1us, RST must rise. RST domain is VDD.
+* Wait for the positive edge of the signal READY when it crosses half of the domain voltage. READY domain is VDD. 
+* A current of 100mA must be drawn from the in OUT with a rise time of 100ns. 
+* After 10us, the bus CONFIG_VOUT[3:0] must be changed from 0 to 5. CONFIG_VOUT[3:0] domain is VDD.
+* After 20us, finishes the simulation. 
+
+The python code that generates this stimulus is shown below:
+
+```
+import vagen as va
+
+#Create a module     
+mod = va.HiLevelMod("DCDC_STML")
+
+#Create pins
+VDD = mod.vdc(name = "VDD", width = 1, direction = "inout")
+OUT = mod.idc(name = "OUT", width = 1, direction = "inout")
+CLK = mod.clock(mod.dig(name = "CLK", domain = VDD, width = 1, direction = "output", rise = 100e-15, fall = 100e-15))
+RST = mod.dig(name = "RST", domain = VDD, width = 1, value = 0, direction = "output", rise = 100e-15, fall = 100e-15)
+READY = mod.dig(name = "READY", domain = VDD, width = 1, direction = "input")
+CONFIG_VOUT = mod.dig(name = "CONFIG_VOUT", domain = VDD, width = 4, value = 0, direction = "output", rise = 100e-15, fall = 100e-15)
+
+#READY positive event
+EVNT_READY = va.Cross(READY.diffHalfDomain, "rising")
+
+#Sequence
+mod.seq(True)(
+    VDD.setRiseFall(10e-6, 10e-6),
+    VDD.applyV(5.0),
+    va.WaitUs(10), 
+    CLK.on(4e6),
+    va.WaitUs(1),
+    RST.write(True),
+    va.WaitSignal(EVNT_READY),
+    OUT.setRiseFall(100e-9, 100e-9),
+    OUT.applyI(100e-3), #Positive current enters the model
+    va.WaitUs(10),
+    CONFIG_VOUT.write(5),
+    va.WaitUs(20),
+    va.Finish()
+)
+
+#Save veriloga file
+file = open('veriloga.va', 'w')
+file.write(mod.getVA())
+file.close()
+```
+
+## Example 2: More than one sequence in the same veriloga
+
+You can create a veriloga parameter called testSeq
+
+```
+seqPar = mod.par(name = "testSeq", value = 0)
+```
+
+And then use this parameter to select the sequence depending on the value
+
+```
+#sequence 1 
+mod.seq(seqPar == 1)(
+...
+)
+
+#sequence 2
+mod.seq(seqPar == 2)(
+...
+)
+```
+
+## Example 3: Model of a configurable resistor
+
+As mentioned before, vagen can be used to generate models. As an example, the code below generates a veriloga model of a configurable resistor.
+
+```
+import vagen as va
+
+#Create a module
+mod = va.HiLevelMod("CONFIG_RES")
+
+#Create pins
+VDD = mod.electrical(name = "VDD", width = 1, direction = "inout")
+IN1 = mod.electrical(name = "IN1", width = 1, direction = "inout")
+IN2 = mod.electrical(name = "IN2", width = 1, direction = "inout")
+CONFIG = mod.dig(name = "CONFIG", domain = VDD, width = 4, value = 0, inCap = 100e-15, direction = "input")
+
+#Parameters
+alfa = mod.par(name = "alfa", value = 10.0)
+
+#Analog block
+mod.analog(
+    va.Branch(IN1, IN2).vCont(va.Branch(IN1, IN2).i*(va.Real(CONFIG.read(signed = False)) + 1)*alfa)
+)
+
+#Save veriloga file
+file = open('veriloga.va', 'w')
+file.write(mod.getVA())
+file.close()
+```
+
+# More examples
+Extra examples will be added to examples folder

vagen-0.0.1/pyproject.toml

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+[build-system]
+requires=["setuptools >= 58.0"]
+build-backend = "setuptools.build_meta"
+
+[project]
+name = "vagen"
+version = "0.0.1"
+authors = [{name="Rodrigo Pedroso Mendes", email="roedroso@gmail.com"}]
+description = "Generates verilogA testbench for verification of analog IPs (VLSI design)"
+readme = "README.md"
+requires-python = ">=3.7"
+dependencies = ["regex>=2023.6.3", "datetime>=5.2"]
+classifiers = [
+    "Programming Language :: Python :: 3",
+    "License :: OSI Approved :: MIT License",
+    "Operating System :: OS Independent",
+]
+
+[project.urls]
+"Homepage" = "https://github.com/rpm2003rpm/vagen"

vagen-0.0.1/setup.cfg

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+[egg_info]
+tag_build = 
+tag_date = 0
+