simdref 0.0.17__tar.gz → 0.0.18__tar.gz

{simdref-0.0.17/src/simdref.egg-info → simdref-0.0.18}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: simdref
-Version: 0.0.17
+Version: 0.0.18
 Summary: Searchable SIMD intrinsic and instruction reference with CLI, manpages, TUI, and LSP.
 Author: Marco
 License: GPL-3.0-or-later
@@ -177,7 +177,8 @@ Dev commands
 | Arm AARCHMRS (A64)      | Base instruction forms and operand tables               | live-only²          |
 | riscv-rvv-intrinsic-doc | RVV intrinsics with deterministic instruction refs      | 77,285 intrinsics   |
 | RISC-V unified-db       | RVV instruction forms, ISA tags, description, operation | 3,666 instructions  |
-| NVIDIA PTX ISA          | Instruction ops, syntax, qualifiers, versions, sm_XX    | 1,088 instructions  |
+| NVIDIA PTX ISA          | Instruction ops, syntax, qualifiers, versions, sm_XX    | 478 instructions    |
+| CUDA intrinsics         | Device intrinsics from clang CUDA headers               | 585 intrinsics      |
 | Intel Guide perf tables | Per-core latency and throughput                         | 9,134 rows          |
 | Intel Optimization Ref. | Latency and throughput tables (volume 2)                | 3,155 rows          |
 | InstLatX64              | Measured latency and throughput dumps                   | 16,235 rows         |

{simdref-0.0.17 → simdref-0.0.18}/README.md

@@ -142,7 +142,8 @@ Dev commands
 | Arm AARCHMRS (A64)      | Base instruction forms and operand tables               | live-only²          |
 | riscv-rvv-intrinsic-doc | RVV intrinsics with deterministic instruction refs      | 77,285 intrinsics   |
 | RISC-V unified-db       | RVV instruction forms, ISA tags, description, operation | 3,666 instructions  |
-| NVIDIA PTX ISA          | Instruction ops, syntax, qualifiers, versions, sm_XX    | 1,088 instructions  |
+| NVIDIA PTX ISA          | Instruction ops, syntax, qualifiers, versions, sm_XX    | 478 instructions    |
+| CUDA intrinsics         | Device intrinsics from clang CUDA headers               | 585 intrinsics      |
 | Intel Guide perf tables | Per-core latency and throughput                         | 9,134 rows          |
 | Intel Optimization Ref. | Latency and throughput tables (volume 2)                | 3,155 rows          |
 | InstLatX64              | Measured latency and throughput dumps                   | 16,235 rows         |

{simdref-0.0.17 → simdref-0.0.18}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "simdref"
-version = "0.0.17"
+version = "0.0.18"
 description = "Searchable SIMD intrinsic and instruction reference with CLI, manpages, TUI, and LSP."
 readme = "README.md"
 requires-python = ">=3.11"

{simdref-0.0.17 → simdref-0.0.18}/src/simdref/annotate.py

@@ -19,8 +19,17 @@ from typing import Any, Iterable, Iterator
 from simdref import perf
 from simdref.arm_instructions import _CONDITION_CODES
 from simdref.asm_identity import isa_by_acceptance
-from simdref.catkey import ISA_FAMILY, isa_family as _isa_family
-from simdref.lsp import NO_CATALOG_ROW, _document_arch, identity_keys
+from simdref.catkey import (
+    IMMEDIATE_ACCEPT,
+    ISA_FAMILY,
+    LITERAL_ACCEPT,
+    form_accept,
+    isa_family as _isa_family,
+    key_names_za_tile,
+    names_za_tile,
+    operands_of_key,
+)
+from simdref.lsp import NO_CATALOG_ROW, _classify_line, _document_arch, identity_keys
 from simdref.models import InstructionRecord
 from simdref.regtable import REG_TABLE, reg_rows
 from simdref.storage import load_instruction_from_db, load_instructions_by_mnemonic_from_db
@@ -471,7 +480,8 @@ def _asm_line(stripped: str, obj: _ObjdumpRecord | None, track_positions: bool)
         return AsmLine(LineKind.LABEL, stripped)
 
     head, comment = _split_comment(stripped)
-    m = _instr_head(head)
+    indent = head[: len(head) - len(head.lstrip())]
+    m = _instr_head(indent + _strip_prefix_tokens(head))
     if not m:
         return AsmLine(LineKind.COMMENT, stripped)
     return AsmLine(
@@ -616,6 +626,42 @@ def _voter_names():
 
 _EXCL_ARM, _SHARED, _RISCV = _voter_names()
 
+# The register families simdref supports: REG_TABLE also carries ARM32 spellings.
+_SUPPORTED_FAMILIES = frozenset({"x86", "a64", "riscv"})
+
+
+def _foreign_operands(operands: str) -> bool:
+    """True when the operands parse as no supported arch's operands.
+
+    A ``$``-sigil register (the MIPS/PPC spelling) belongs to no supported
+    arch, and a line whose register words all name unsupported families
+    (ARM32's r0-r15, ip, pc) carries no supported evidence. A word absent
+    from REG_TABLE is a symbol and stays neutral, and one supported-family
+    register anywhere clears the whole line (issue #65 B2/B6).
+    """
+    unsupported = sigil = False
+    i = 0
+    n = len(operands)
+    while i < n:
+        if not (operands[i] == "_" or operands[i].isalnum()):
+            i += 1
+            continue
+        j = i
+        while j < n and (operands[j] == "_" or operands[j].isalnum()):
+            j += 1
+        if i > 0 and operands[i - 1] == "$" and not operands[i].isdigit():
+            sigil = True
+        else:
+            families = {
+                family for _klass, _width, family in REG_TABLE.get(operands[i:j].casefold(), ())
+            }
+            if families & _SUPPORTED_FAMILIES:
+                return False
+            if families:
+                unsupported = True
+        i = j
+    return sigil or unsupported
+
 
 def _isa_votes(text: str) -> tuple[int, int, int]:
     """(excl_arm, excl_riscv, shared) register votes of one instruction text."""
@@ -630,7 +676,9 @@ def _isa_votes(text: str) -> tuple[int, int, int]:
         while j < n and (text[j] == "_" or text[j].isalnum()):
             j += 1
         token = text[i:j]
-        if i == 0 or text[i - 1] != "%":
+        # '%' starts an AT&T register and '$' a sigil register of no
+        # supported arch (MIPS/PPC): the name inside never votes (issue #65).
+        if i == 0 or text[i - 1] not in "%$":
             if token in _EXCL_ARM:
                 excl_arm += 1
             elif token in _SHARED:
@@ -1047,6 +1095,19 @@ def pick_record(
         # AT&T lists sources first; catalog form tokens are in Intel order.
         slots = list(reversed(slots))
 
+    # A ZA tile operand names the SME tile rows only, and a line without one
+    # never wants them (issue #65 M11): the rows share the mnemonic and
+    # operand count with the plain SVE/NEON forms, so operand shape alone
+    # picks a timed plain row where the ZA forms carry no timing. Same parity
+    # rule as the "_1to" broadcast filter in asm_identity.
+    za_pair = [
+        record
+        for record in candidates
+        if key_names_za_tile(str(getattr(record, "key", "") or "")) == names_za_tile(operands)
+    ]
+    if za_pair:
+        candidates = za_pair
+
     def score(rec: InstructionRecord) -> tuple[int, int, int, int]:
         measured = sum(
             1
@@ -1063,6 +1124,49 @@ def pick_record(
     return max(candidates, key=score)
 
 
+def _record_takes_line(record: InstructionRecord, operands: str) -> bool:
+    """Whether the record's key accepts the line's operand classes.
+
+    Classes and accepts come from the catalog: the lsp line classifier and
+    catkey's accept sets. A bare key constrains nothing, a literal key operand
+    (the zero-idiom rows) constrains nothing, and an input the classifier
+    gave no class constrains nothing. Register and memory classes ride each
+    other here exactly like the form pick, so the only hard mismatch is an
+    immediate input against a key operand that accepts no immediate: on an
+    undecided line that pick is a foreign borrow, not an answer (a bare
+    "1, 2, 3" never names a register-class row, issue #65 B2). A decided
+    line named its family already, so only the undecided line is judged.
+    """
+    ops = operands_of_key(record.key)
+    if not ops:
+        return True
+    arch, classes, _reverse, _weak = _classify_line(operands, False)
+    if arch:
+        # A decided line named its family; the family-pinned pick stands.
+        return True
+    if "%" in operands or "$" in operands:
+        # AT&T lists sources first and key operands are in Intel order, so
+        # the classes flip to meet the key (the rule pick_record's slots
+        # use). A sigil-less line keeps its order: Intel and ARM both name
+        # the destination first, as the key does.
+        classes = list(reversed(classes))
+    immediates = [cls for cls in classes if cls in ("i", "lit0", "lit1")]
+    if not immediates:
+        return True
+    if len(ops) != len(classes):
+        return False
+    for cls, op in zip(classes, ops):
+        accept = form_accept(op)
+        if (
+            cls in ("i", "lit0", "lit1")
+            and accept
+            and accept not in LITERAL_ACCEPT
+            and accept.isdisjoint(IMMEDIATE_ACCEPT)
+        ):
+            return False
+    return True
+
+
 # ---------------------------------------------------------------------------
 # Aggregation
 # ---------------------------------------------------------------------------
@@ -1439,12 +1543,15 @@ def _annotate_instruction(
     line_isa: str | None = None,
     line_number: int | None = None,
     identity_cache: dict[str, tuple[InstructionRecord, PerfSummary | None]] | None = None,
+    foreign: bool = False,
 ) -> tuple[str, dict[str, Any] | None]:
     """Return the rendered output line and an optional JSON record.
 
     ``line_isa`` names the family the line's own evidence shows (a pinned
     ``--isa`` counts as one). None marks a neutral line in auto mode: the
-    stream family answers first, then the family that holds rows.
+    stream family answers first, then the family that holds rows. ``foreign``
+    marks a line whose operands parse as no supported arch's operands
+    (PPC, MIPS, ARM32): no supported family's rows answer it (issue #65 B2/B6).
     """
     if stats is not None:
         stats["parsed"] = stats.get("parsed", 0) + 1
@@ -1509,7 +1616,9 @@ def _annotate_instruction(
     else:
         isa = line_isa or opts.isa
         pick_isa = isa
-        if lookup_cache is not None:
+        if foreign:
+            records = []
+        elif lookup_cache is not None:
             records = lookup_cache.get((parsed.mnemonic, isa))
             if records is None:
                 # Module-level call (not a captured reference) so tests can
@@ -1518,16 +1627,21 @@ def _annotate_instruction(
                 lookup_cache[(parsed.mnemonic, isa)] = records
         else:
             records = lookup(parsed.mnemonic, conn, isa=isa)
-        if not records and line_isa is None:
+        if not records and line_isa is None and not foreign:
             # A neutral line whose stream family holds no rows gets the rows
             # of the family that has them (issue #57 batch: jnle, bare b).
+            # A foreign line borrows nothing (issue #65 B2/B6).
             pick_isa = None
             records = lookup(parsed.mnemonic, conn, isa=None)
             if lookup_cache is not None:
                 lookup_cache[(parsed.mnemonic, None)] = records
-        if stats is not None and records:
-            stats["recognized"] = stats.get("recognized", 0) + 1
         record = pick_record(records, arch=opts.arch, operands=parsed.operands, isa=pick_isa)
+        if record is not None and not _record_takes_line(record, parsed.operands):
+            # The key does not take the line's operand classes: a foreign
+            # borrow, not an answer (issue #65 B2).
+            record = None
+        if stats is not None and record is not None:
+            stats["recognized"] = stats.get("recognized", 0) + 1
 
     if record is None:
         if opts.unknown == "drop":
@@ -1686,6 +1800,7 @@ def annotate_stream(
     }
     auto_isa = opts.isa not in ("x86", "arm", "riscv")
     line_family: dict[int, str] = {}
+    foreign: set[int] = set()
     if auto_isa:
         # Assembler acceptance decides each line's family: one llvm-mc run
         # per candidate triple. The register vote below is the fallback when
@@ -1693,6 +1808,13 @@ def annotate_stream(
         probe_texts = [text for _index, text in items]
         families, majority = isa_by_acceptance(probe_texts)
         line_family = {index: family for (index, _text), family in zip(items, families) if family}
+        # The line's own parse names foreign architectures (PPC/MIPS/ARM32):
+        # those lines borrow no rows from a supported family (issue #65 B2/B6).
+        foreign = {
+            index
+            for index, parsed in enumerate(parsed_lines)
+            if parsed.kind == LineKind.INSTRUCTION and _foreign_operands(parsed.operands)
+        }
         # auto: the acceptance majority names the ISA, then the input
         # signals, then the document arch from _document_arch; x86 stays
         # the guess when all stay silent.
@@ -1729,6 +1851,11 @@ def annotate_stream(
             if not collecting_json:
                 yield parsed.raw + "\n"
             continue
+        line_isa = opts.isa
+        if auto_isa:
+            # A pin forces one family; auto mode splits the batch per line,
+            # the assembler verdict first and the register vote as fallback.
+            line_isa = line_family.get(index) or _line_isa(f"{parsed.mnemonic} {parsed.operands}")
         out_line, record = _annotate_instruction(
             parsed,
             opts,
@@ -1736,13 +1863,10 @@ def annotate_stream(
             lookup_cache,
             stats,
             identity_key=identity.get(index),
-            # A pin forces one family; auto mode splits the batch per line,
-            # the assembler verdict first and the register vote as fallback.
-            line_isa=opts.isa
-            if not auto_isa
-            else line_family.get(index) or _line_isa(f"{parsed.mnemonic} {parsed.operands}"),
+            line_isa=line_isa,
             line_number=index + 1,
             identity_cache=identity_cache,
+            foreign=index in foreign if line_isa is None else False,
         )
         if collecting_json:
             if record is not None:

{simdref-0.0.17 → simdref-0.0.18}/src/simdref/asm_identity.py

@@ -1403,6 +1403,40 @@ _ISA_CANDIDATES = (
 )
 
 
+def _reloc_branch_targets(text: str) -> str:
+    """Spell objdump's bare branch targets the fixup way ("je 7f37b" as ".+0x7f37b").
+
+    objdump prints branch targets as bare hex, and llvm-mc rejects the bare
+    spelling where the value holds an a-f letter: "7f37b" is no decimal
+    number and no valid symbol. The ".+0x" spelling is the same PC-relative
+    fixup the <sym> form answers with, and it carries no immediate range
+    check, so it assembles on every candidate triple for any address. A
+    token qualifies only when it starts with a digit, holds only hex digits
+    with at least one a-f letter (a decimal immediate assembles as-is), and
+    follows a separator, so the tail of "0x...", "0b..." or "#0x..." text is
+    never rewritten.
+    """
+    hexd = "0123456789abcdefABCDEF"
+    letters = "abcdefABCDEF"
+    out: list[str] = []
+    i = 0
+    n = len(text)
+    while i < n:
+        if text[i].isdigit() and (i == 0 or text[i - 1] in " \t,"):
+            j = i
+            while j < n and text[j] in hexd:
+                j += 1
+            token = text[i:j]
+            if any(c in letters for c in token):
+                out.append(".+0x")
+            out.append(token)
+            i = j
+            continue
+        out.append(text[i])
+        i += 1
+    return "".join(out)
+
+
 def _probe_all_triples(lines: list[str], llvm_mc: str) -> dict[tuple[str, str], list[dict]]:
     """Probe every candidate triple, one llvm-mc run per triple.
 
@@ -1412,6 +1446,7 @@ def _probe_all_triples(lines: list[str], llvm_mc: str) -> dict[tuple[str, str],
     """
     from concurrent.futures import ThreadPoolExecutor
 
+    lines = [_reloc_branch_targets(line) for line in lines]
     with ThreadPoolExecutor(max_workers=len(_ISA_CANDIDATES)) as pool:
         futures = {
             (arch, syntax): pool.submit(_probe_lines_split, lines, arch, syntax, llvm_mc)

{simdref-0.0.17 → simdref-0.0.18}/src/simdref/catkey.py

@@ -68,6 +68,7 @@ ISA_FAMILY = {
     "riscv32": "riscv",
     "riscv64": "riscv",
     "ptx": "ptx",
+    "cuda": "cuda",
 }
 
 
@@ -84,6 +85,8 @@ def isa_family(architecture: str | None) -> str | None:
         return "riscv"
     if name.startswith("ptx"):
         return "ptx"
+    if name.startswith("cuda"):
+        return "cuda"
     return "x86"
 
 
@@ -150,6 +153,35 @@ def _first_digits(text: str) -> int | None:
     return int(text[start:end]) if end > start else None
 
 
+def names_za_tile(text: str) -> bool:
+    """True when *text* names a ZA tile operand ("za0h", "za.s"), never ZT0.
+
+    A ZA tile name starts with "za" at an operand boundary and closes the
+    stem with a tile digit ("za0h"), a tile element letter ("zab") or the
+    full-register dot ("za.s"). One boundary scan; no regular expressions.
+    """
+    low = text.casefold()
+    for at in range(len(low) - 2):
+        if low[at] != "z" or low[at + 1] != "a":
+            continue
+        if at > 0 and (low[at - 1].isalnum() or low[at - 1] in "._"):
+            continue
+        if low[at + 2].isdecimal() or low[at + 2] in ".bhwdq":
+            return True
+    return False
+
+
+def key_names_za_tile(key: str) -> bool:
+    """True when a catalog key names a ZA tile operand form.
+
+    The tile encodes as a placeholder ("<ZAT...>"), the tile-slice register
+    ("<WV>") or a literal name ("ZA0<HV>"). ZT0 rows stay out: SVE counted
+    register-list keys reuse "<ZT..>" placeholder names for plain Z lists.
+    """
+    upper = key.upper()
+    return "<ZA" in upper or "<WV>" in upper or names_za_tile(key)
+
+
 def form_accept(op: str) -> frozenset:
     """The line classes a catalog-key operand accepts, as one frozenset.
 
@@ -200,8 +232,10 @@ def form_accept(op: str) -> frozenset:
     name = _cut_key_repeats(op.upper())
     if "<HASH>" in name:
         return IMMEDIATE_ACCEPT
-    # A ZA tile operand ("<ZAT...>[W1, #0]") is not a plain vector register.
-    if "<ZAT" in name:
+    # A ZA tile operand ("<ZAT...>[W1, #0]", "ZA0<HV>.B[W1, #0]",
+    # "Z3.4S[<WV>, #0]") is not a plain vector register: it matches a line's
+    # ZA tile operand only.
+    if key_names_za_tile(op):
         return frozenset({"za"})
     if _is_counted_vector(name):
         # A counted register list accepts only the same count.

simdref-0.0.18/src/simdref/cuda.py

@@ -0,0 +1,50 @@
+"""CUDA C++ device intrinsics parsing and derived record rows.
+
+Parses the JSON bundle produced by tools/vendor_cuda_sources.py, which
+extracts CUDA API names from four clang headers and resolves PTX
+instruction links by parsing LLVM TableGen .td files.
+"""
+
+from __future__ import annotations
+
+import json
+from typing import Any
+
+from simdref.models import IntrinsicRecord
+
+BUNDLE_FORMAT = "clang-cuda-headers-v2"
+CUDA_INTRINSICS_DOC_URL = "https://docs.nvidia.com/cuda/cuda-c-programming-guide/"
+
+
+def parse_cuda_intrinsics_payload(text: str) -> list[IntrinsicRecord]:
+    """Parse the CUDA intrinsics JSON bundle into IntrinsicRecord rows."""
+    data = json.loads(text)
+    if data.get("format") != BUNDLE_FORMAT:
+        raise ValueError(f"Unexpected bundle format: {data.get('format')!r}")
+
+    rows: list[IntrinsicRecord] = []
+    for item in data.get("intrinsics", []):
+        metadata = item.get("metadata", {})
+        classification = metadata.get("classification", "")
+
+        row = IntrinsicRecord(
+            name=item["name"],
+            signature=item.get("signature", ""),
+            description=item.get("description", ""),
+            header=item.get("header", ""),
+            url=item.get("url", ""),
+            architecture="cuda",
+            isa=["CUDA"],
+            category=item.get("category", ""),
+            subcategory=item.get("subcategory", ""),
+            instructions=item.get("instructions", []),
+            instruction_refs=item.get("instruction_refs", []),
+            metadata={"classification": classification},
+            doc_sections=item.get("doc_sections", {}),
+            notes=item.get("notes", []),
+            aliases=item.get("aliases", []),
+            source="clang-cuda-headers",
+        )
+        rows.append(row)
+
+    return rows

{simdref-0.0.17 → simdref-0.0.18}/src/simdref/display.py

@@ -367,6 +367,7 @@ def display_architecture(architecture: str) -> str:
         "x86": "x86",
         "arm": "Arm",
         "riscv": "RISC-V",
+        "cuda": "CUDA",
     }.get((architecture or "").lower(), architecture or "-")
 
 
@@ -390,6 +391,8 @@ def isa_family(isa: str) -> str:
         return "RISC-V"
     if d == "PTX":
         return "PTX"
+    if d == "CUDA":
+        return "CUDA"
     if d.startswith("APX"):
         return "APX"
     if d.startswith("AMX"):
@@ -507,10 +510,17 @@ def instruction_markdown(item, conn=None) -> str:
     """
     lines = [f"```asm\n{display_instruction_form(item.key)}\n```"]
     lines.append(f"**isa.** {display_isa(item.isa)}")
-    for key, value in instruction_metadata_rows(item):
+    # The web app keys an entry by db_key. A display-key link opens no
+    # detail page. It fills the query box instead.
+    link = f"[simdref]({web_deep_link('instruction', item.db_key)})"
+    rows = instruction_metadata_rows(item)
+    for key, value in rows:
         if key != "isa":
             # Escaping a URL would break the editor's autolink.
-            lines.append(f"**{key}.** {value if value.startswith('http') else _md_escape(value)}")
+            row = f"**{key}.** {value if value.startswith('http') else _md_escape(value)}"
+            lines.append(f"{row} | {link}" if key == "url" else row)
+    if not any(key == "url" for key, _ in rows):
+        lines.append(link)
     if item.description:
         shown: set[str] = set()
         for section in _DESCRIPTION_ORDER:
@@ -1196,6 +1206,7 @@ def render_intrinsic(catalog, item, conn=None, short: bool = False, full: bool =
         table.add_row("source", item.url)
     table.add_row("architecture", display_architecture(item.architecture))
     table.add_row("isa", ", ".join(item.isa) or "-")
+    table.add_row("instructions", ", ".join(item.instructions) or "-")
     table.add_row("category", category_display_text(item))
     if item.description:
         table.add_row("description", item.description)

{simdref-0.0.17 → simdref-0.0.18}/src/simdref/filters.py

@@ -27,6 +27,7 @@ ISA_FAMILY_ORDER: dict[str, int] = {
     "SVML": 10,
     "Other": 11,
     "PTX": 12,
+    "CUDA": 13,
 }
 
 DEFAULT_ENABLED_ISAS: tuple[str, ...] = ("SSE", "AVX", "AVX-512", "Arm", "RISC-V")

{simdref-0.0.17 → simdref-0.0.18}/src/simdref/ingest_catalog.py

@@ -21,12 +21,14 @@ from simdref.catkey import (
     parse_key,
     substitute_placeholders,
 )
+from simdref.cuda import parse_cuda_intrinsics_payload
 from simdref.display import strip_instruction_decorators, strip_leading_tags
 from simdref.htmltext import squeeze, strip_html, tidy, unwrap_anchors
 from simdref.ingest_pdf import find_pdf_source_path, load_or_parse_pdf_source, merge_pdf_enrichment
 from simdref.ingest_sources import (
     fetch_arm_a64_data,
     fetch_arm_acle_data,
+    fetch_cuda_data,
     fetch_intel_data,
     fetch_ptx_isa_data,
     fetch_riscv_rvv_intrinsics_data,
@@ -1622,11 +1624,15 @@ def build_catalog(
     emit("Fetching PTX ISA reference")
     ptx_text, ptx_source = fetch_ptx_isa_data()
     emit(f"Fetched PTX ISA reference from {ptx_source.url}")
+    emit("Fetching CUDA intrinsics data")
+    cuda_text, cuda_source = fetch_cuda_data()
+    emit(f"Fetched CUDA intrinsics data from {cuda_source.url}")
     emit("Parsing intrinsic catalog")
     intrinsics = parse_intel_payload(intel_text)
     arm_intrinsics = parse_arm_intrinsics_payload(arm_acle_text)
     intrinsics.extend(arm_intrinsics)
     intrinsics.extend(parse_riscv_intrinsics_payload(riscv_intrinsics_text))
+    intrinsics.extend(parse_cuda_intrinsics_payload(cuda_text))
     emit(f"Parsed {len(intrinsics)} intrinsics")
     emit("Parsing instruction catalog")
     instructions = parse_uops_xml(uops_text)
@@ -1668,6 +1674,7 @@ def build_catalog(
             riscv_instructions_source,
             *perf_sources_version,
             ptx_source,
+            cuda_source,
         ],
         generated_at=now_iso(),
     )

{simdref-0.0.17 → simdref-0.0.18}/src/simdref/ingest_sources.py

@@ -132,6 +132,9 @@ LOCAL_PTX_BUNDLES = [
 LOCAL_PTX_DOC_HTMLS = [
     _REPO_ROOT / "vendor" / "ptx" / "parallel-thread-execution.html",
 ]
+LOCAL_CUDA_BUNDLES = [
+    _REPO_ROOT / "vendor" / "cuda" / "cuda_intrinsics.json",
+]
 
 
 def now_iso() -> str:
@@ -834,3 +837,22 @@ def fetch_ptx_isa_data() -> tuple[str, SourceVersion]:
         fetched_at=now_iso(),
         url=PTX_ISA_DOC_URL,
     )
+
+
+CUDA_INTRINSICS_DOC_URL = "https://docs.nvidia.com/cuda/cuda-c-programming-guide/"
+
+
+def fetch_cuda_data() -> tuple[str, SourceVersion]:
+    local = _read_local_text(LOCAL_CUDA_BUNDLES, "cuda-intrinsics", "local-bundle")
+    if local is not None:
+        return local
+    # Return empty bundle if not found - CUDA intrinsics are optional
+    empty_bundle = (
+        '{"format": "clang-cuda-headers-v2", "intrinsics": [], "metadata": {"total_intrinsics": 0}}'
+    )
+    return empty_bundle, SourceVersion(
+        source="cuda-intrinsics",
+        version="empty",
+        fetched_at=now_iso(),
+        url="local:empty",
+    )