simdref 0.0.16__tar.gz → 0.0.18__tar.gz

{simdref-0.0.16/src/simdref.egg-info → simdref-0.0.18}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: simdref
-Version: 0.0.16
+Version: 0.0.18
 Summary: Searchable SIMD intrinsic and instruction reference with CLI, manpages, TUI, and LSP.
 Author: Marco
 License: GPL-3.0-or-later
@@ -25,7 +25,7 @@ Requires-Dist: msgpack<2,>=1.2.4
 Requires-Dist: PyYAML<7,>=6.0.3
 Requires-Dist: rapidfuzz<4,>=3.14.6
 Requires-Dist: rich<16,>=15.0.0
-Requires-Dist: simdref-llvm-mc==23.1.4; (sys_platform == "linux" and (platform_machine == "x86_64" or platform_machine == "aarch64")) or (sys_platform == "darwin" and (platform_machine == "arm64" or platform_machine == "x86_64")) or (sys_platform == "win32" and platform_machine == "AMD64")
+Requires-Dist: simdref-llvm-mc==23.1.4.post1; (sys_platform == "linux" and (platform_machine == "x86_64" or platform_machine == "aarch64")) or (sys_platform == "darwin" and (platform_machine == "arm64" or platform_machine == "x86_64")) or (sys_platform == "win32" and platform_machine == "AMD64")
 Requires-Dist: textual<9,>=8.2.8
 Requires-Dist: typer<1,>=0.27.3
 Provides-Extra: ingest
@@ -177,6 +177,8 @@ Dev commands
 | Arm AARCHMRS (A64)      | Base instruction forms and operand tables               | live-only²          |
 | riscv-rvv-intrinsic-doc | RVV intrinsics with deterministic instruction refs      | 77,285 intrinsics   |
 | RISC-V unified-db       | RVV instruction forms, ISA tags, description, operation | 3,666 instructions  |
+| NVIDIA PTX ISA          | Instruction ops, syntax, qualifiers, versions, sm_XX    | 478 instructions    |
+| CUDA intrinsics         | Device intrinsics from clang CUDA headers               | 585 intrinsics      |
 | Intel Guide perf tables | Per-core latency and throughput                         | 9,134 rows          |
 | Intel Optimization Ref. | Latency and throughput tables (volume 2)                | 3,155 rows          |
 | InstLatX64              | Measured latency and throughput dumps                   | 16,235 rows         |

{simdref-0.0.16 → simdref-0.0.18}/README.md

@@ -142,6 +142,8 @@ Dev commands
 | Arm AARCHMRS (A64)      | Base instruction forms and operand tables               | live-only²          |
 | riscv-rvv-intrinsic-doc | RVV intrinsics with deterministic instruction refs      | 77,285 intrinsics   |
 | RISC-V unified-db       | RVV instruction forms, ISA tags, description, operation | 3,666 instructions  |
+| NVIDIA PTX ISA          | Instruction ops, syntax, qualifiers, versions, sm_XX    | 478 instructions    |
+| CUDA intrinsics         | Device intrinsics from clang CUDA headers               | 585 intrinsics      |
 | Intel Guide perf tables | Per-core latency and throughput                         | 9,134 rows          |
 | Intel Optimization Ref. | Latency and throughput tables (volume 2)                | 3,155 rows          |
 | InstLatX64              | Measured latency and throughput dumps                   | 16,235 rows         |

{simdref-0.0.16 → simdref-0.0.18}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "simdref"
-version = "0.0.16"
+version = "0.0.18"
 description = "Searchable SIMD intrinsic and instruction reference with CLI, manpages, TUI, and LSP."
 readme = "README.md"
 requires-python = ">=3.11"
@@ -42,7 +42,7 @@ dependencies = [
   # manylinux x86_64 aarch64, macOS arm64 x86_64 and win_amd64, so the
   # marker keeps the dependency off every other platform (musl included),
   # where pip must see no candidate instead of failing to resolve.
-  'simdref-llvm-mc==23.1.4; (sys_platform == "linux" and (platform_machine == "x86_64" or platform_machine == "aarch64")) or (sys_platform == "darwin" and (platform_machine == "arm64" or platform_machine == "x86_64")) or (sys_platform == "win32" and platform_machine == "AMD64")',
+  'simdref-llvm-mc==23.1.4.post1; (sys_platform == "linux" and (platform_machine == "x86_64" or platform_machine == "aarch64")) or (sys_platform == "darwin" and (platform_machine == "arm64" or platform_machine == "x86_64")) or (sys_platform == "win32" and platform_machine == "AMD64")',
   "textual>=8.2.8,<9",
   "typer>=0.27.3,<1",
 ]

{simdref-0.0.16 → simdref-0.0.18}/src/simdref/annotate.py

@@ -9,7 +9,6 @@ simdref catalog.
 from __future__ import annotations
 
 import json
-import re
 import sqlite3
 import statistics
 import string
@@ -18,9 +17,19 @@ from enum import Enum
 from typing import Any, Iterable, Iterator
 
 from simdref import perf
+from simdref.arm_instructions import _CONDITION_CODES
 from simdref.asm_identity import isa_by_acceptance
-from simdref.catkey import ISA_FAMILY, isa_family as _isa_family
-from simdref.lsp import NO_CATALOG_ROW, _document_arch, identity_keys
+from simdref.catkey import (
+    IMMEDIATE_ACCEPT,
+    ISA_FAMILY,
+    LITERAL_ACCEPT,
+    form_accept,
+    isa_family as _isa_family,
+    key_names_za_tile,
+    names_za_tile,
+    operands_of_key,
+)
+from simdref.lsp import NO_CATALOG_ROW, _classify_line, _document_arch, identity_keys
 from simdref.models import InstructionRecord
 from simdref.regtable import REG_TABLE, reg_rows
 from simdref.storage import load_instruction_from_db, load_instructions_by_mnemonic_from_db
@@ -471,7 +480,8 @@ def _asm_line(stripped: str, obj: _ObjdumpRecord | None, track_positions: bool)
         return AsmLine(LineKind.LABEL, stripped)
 
     head, comment = _split_comment(stripped)
-    m = _instr_head(head)
+    indent = head[: len(head) - len(head.lstrip())]
+    m = _instr_head(indent + _strip_prefix_tokens(head))
     if not m:
         return AsmLine(LineKind.COMMENT, stripped)
     return AsmLine(
@@ -507,11 +517,33 @@ def _lookup_variants(mnemonic: str) -> list[str]:
 
 
 # AArch64 condition-code branches: b.<cond>, no register table covers them.
-_A64_BCOND_RE = re.compile(
-    r"(?<![\w])b\.(?:eq|ne|lt|le|gt|ge|hs|lo|hi|ls|mi|pl|vs|vc|al|nv)(?![\w])"
+# The vocabulary is the first spelling of each cond value in the A64 row table
+# (cs/cc alias the hs/lo spellings the llvm-objdump printers print).
+_A64_BCOND_CODES = frozenset(
+    dict(reversed([(cond, code) for code, cond in _CONDITION_CODES])).values()
 )
 
 
+def _bcond_hits(text: str) -> int:
+    """Count b.<cond> branch mnemonics with word boundaries on both sides."""
+    count = 0
+    i = text.find("b.")
+    while i >= 0:
+        tail = text[i + 2 : i + 4]
+        before = text[i - 1 : i]
+        after = text[i + 4 : i + 5]
+        if (
+            tail in _A64_BCOND_CODES
+            and not (before and (before.isalnum() or before == "_"))
+            and not (after and (after.isalnum() or after == "_"))
+        ):
+            count += 1
+            i = text.find("b.", i + 4)
+        else:
+            i = text.find("b.", i + 2)
+    return count
+
+
 def _drop_symbol_annotations(text: str) -> str:
     """Drop objdump symbol annotations ("<x0+0x50>"): a target, never input."""
     out: list[str] = []
@@ -594,6 +626,42 @@ def _voter_names():
 
 _EXCL_ARM, _SHARED, _RISCV = _voter_names()
 
+# The register families simdref supports: REG_TABLE also carries ARM32 spellings.
+_SUPPORTED_FAMILIES = frozenset({"x86", "a64", "riscv"})
+
+
+def _foreign_operands(operands: str) -> bool:
+    """True when the operands parse as no supported arch's operands.
+
+    A ``$``-sigil register (the MIPS/PPC spelling) belongs to no supported
+    arch, and a line whose register words all name unsupported families
+    (ARM32's r0-r15, ip, pc) carries no supported evidence. A word absent
+    from REG_TABLE is a symbol and stays neutral, and one supported-family
+    register anywhere clears the whole line (issue #65 B2/B6).
+    """
+    unsupported = sigil = False
+    i = 0
+    n = len(operands)
+    while i < n:
+        if not (operands[i] == "_" or operands[i].isalnum()):
+            i += 1
+            continue
+        j = i
+        while j < n and (operands[j] == "_" or operands[j].isalnum()):
+            j += 1
+        if i > 0 and operands[i - 1] == "$" and not operands[i].isdigit():
+            sigil = True
+        else:
+            families = {
+                family for _klass, _width, family in REG_TABLE.get(operands[i:j].casefold(), ())
+            }
+            if families & _SUPPORTED_FAMILIES:
+                return False
+            if families:
+                unsupported = True
+        i = j
+    return sigil or unsupported
+
 
 def _isa_votes(text: str) -> tuple[int, int, int]:
     """(excl_arm, excl_riscv, shared) register votes of one instruction text."""
@@ -608,7 +676,9 @@ def _isa_votes(text: str) -> tuple[int, int, int]:
         while j < n and (text[j] == "_" or text[j].isalnum()):
             j += 1
         token = text[i:j]
-        if i == 0 or text[i - 1] != "%":
+        # '%' starts an AT&T register and '$' a sigil register of no
+        # supported arch (MIPS/PPC): the name inside never votes (issue #65).
+        if i == 0 or text[i - 1] not in "%$":
             if token in _EXCL_ARM:
                 excl_arm += 1
             elif token in _SHARED:
@@ -646,7 +716,7 @@ def detect_isa(lines: Iterable[str]) -> str | None:
         # a register (review finding 1).
         text = _drop_symbol_annotations(f"{parsed.mnemonic} {parsed.operands}")
         vote_arm, vote_riscv, vote_shared = _isa_votes(text)
-        excl_arm += vote_arm + len(_A64_BCOND_RE.findall(text))
+        excl_arm += vote_arm + _bcond_hits(text)
         excl_riscv += vote_riscv
         shared += vote_shared
     if excl_arm or excl_riscv:
@@ -682,10 +752,36 @@ def lookup(
     return []
 
 
-_SIZE_SPECIFIER_RE = re.compile(
-    r"\b(byte|word|dword|qword|xmmword|ymmword|zmmword)\s+ptr\b",
-    re.IGNORECASE,
-)
+_SIZE_WORDS = frozenset({"byte", "word", "dword", "qword", "xmmword", "ymmword", "zmmword"})
+
+
+def _has_size_ptr(text: str) -> bool:
+    """True for a size keyword with a trailing "ptr" ("byte ptr [rdx]")."""
+    n = len(text)
+    i = 0
+    while i + 3 <= n:
+        if text[i : i + 3].lower() != "ptr":
+            i += 1
+            continue
+        if i + 3 < n and (text[i + 3].isalnum() or text[i + 3] == "_"):
+            i += 1
+            continue
+        j = i
+        while j > 0 and text[j - 1].isspace():
+            j -= 1
+        if j == i:
+            i += 1
+            continue
+        for word in _SIZE_WORDS:
+            k = j - len(word)
+            if (
+                k >= 0
+                and text[k:j].lower() == word
+                and not (k > 0 and (text[k - 1].isalnum() or text[k - 1] == "_"))
+            ):
+                return True
+        i += 1
+    return False
 
 
 def _x86_reg_class(name: str) -> str | None:
@@ -750,6 +846,26 @@ def _imm_kind(value: int) -> str:
     return "I64"
 
 
+def _is_number(text: str) -> bool:
+    """True for the literal ``-?0x<hex>`` or ``-?<digits>`` the scans matched."""
+    body = text[1:] if text[:1] == "-" else text
+    if body[:2] == "0x":
+        body = body[2:]
+        return bool(body) and all(char in string.hexdigits for char in body)
+    return bool(body) and body.isdecimal()
+
+
+def _is_symbol(text: str) -> bool:
+    """True for ``[A-Za-z_.$]`` heads with ``\\w.$@`` tails (a plain symbol)."""
+    head = text[:1]
+    return (
+        bool(head)
+        and head.isascii()
+        and (head.isalpha() or head in "_.$")
+        and all(char.isalnum() or char in "_.$@" for char in text[1:])
+    )
+
+
 def _classify_operand(op: str) -> tuple[str, str | None]:
     """Return ``(kind, reg_name_lower)`` for one operand.
 
@@ -763,17 +879,22 @@ def _classify_operand(op: str) -> tuple[str, str | None]:
     if not s:
         return "?", None
     # objdump branch target: an address followed by a <symbol> annotation.
-    if re.fullmatch(r"-?(?:0x[0-9a-fA-F]+|\d+)\s+<[^>]*>", s):
-        return "REL", None
+    lt = s.find("<")
+    if lt > 0 and s.endswith(">") and ">" not in s[lt + 1 : -1]:
+        k = lt
+        while k > 0 and s[k - 1].isspace():
+            k -= 1
+        if k < lt and _is_number(s[:k]):
+            return "REL", None
     # AT&T immediate: $... ; Intel immediate: bare number / 0x... / '$'-less literal
-    if s.startswith("$") or re.fullmatch(r"-?0x[0-9a-fA-F]+|-?\d+", s):
+    if s.startswith("$") or _is_number(s):
         try:
             return _imm_kind(int(s.lstrip("$"), 0)), None
         except ValueError:
             return "I", None
     # AT&T memory: ``(%reg)``, ``disp(%reg,%idx,scale)``, or plain symbol
     # with a ``(...)`` section; Intel memory: ``[...]`` or explicit size ptr.
-    if "(" in s or "[" in s or _SIZE_SPECIFIER_RE.search(s):
+    if "(" in s or "[" in s or _has_size_ptr(s):
         return "M", None
     # Pure register?
     name = (s[1:] if s[:1] == "%" else s).casefold()
@@ -781,7 +902,7 @@ def _classify_operand(op: str) -> tuple[str, str | None]:
     if tok is not None or _is_vec_shaped(name):
         return tok or "?", name
     # Plain symbol (branch target) or unknown.
-    if re.fullmatch(r"[A-Za-z_.$][\w.$@]*", s):
+    if _is_symbol(s):
         return "REL", None
     return "?", None
 
@@ -802,9 +923,6 @@ def _operand_shape(operands: str) -> tuple[list[tuple[str, str | None]], bool]:
     return slots, aliased
 
 
-_FORM_OPS_RE = re.compile(r"\(([^)]*)\)\s*$")
-
-
 def _form_operand_tokens(form_or_key: str) -> list[str]:
     """Extract the comma-separated operand tokens from a catalog form/key.
 
@@ -812,14 +930,25 @@ def _form_operand_tokens(form_or_key: str) -> list[str]:
     ``"RET_NEAR"`` returns ``[]``. Tokens are upper-cased.
     """
     s = str(form_or_key or "")
-    m = _FORM_OPS_RE.search(s)
-    if not m:
+    tail = s.rstrip()
+    if not tail or tail[-1] != ")":
+        return []
+    close = len(tail) - 1
+    # The inner text starts at the first "(" after the last ")" before the
+    # closing one, so no ")" splits it (the old group matched the same span).
+    start = tail.find("(", tail.rfind(")", 0, close) + 1)
+    if start < 0:
         return []
-    inner = m.group(1)
+    inner = tail[start + 1 : close]
     return [t.strip().upper() for t in inner.split(",") if t.strip()]
 
 
-_BROADCAST_TOK_RE = re.compile(r"_1TO\d+$")
+def _is_broadcast_token(token: str) -> bool:
+    """True for a form token with a ``_1toN`` tail (``M16_1to8``)."""
+    start = len(token)
+    while start > 0 and token[start - 1].isdecimal():
+        start -= 1
+    return start < len(token) and start >= 4 and token[start - 4 : start] == "_1TO"
 
 
 def _token_matches_slot(form_tok: str, slot_kind: str) -> bool:
@@ -867,7 +996,7 @@ def _slot_token_score(form_tok: str, slot_kind: str) -> int:
     if not _token_matches_slot(ft, sk):
         # Weak near-misses: a broadcast row wants a {1toN} annotation, and a
         # register can ride a memory row (mov r,r against MOV (M32, R32)).
-        if sk == "M" and _BROADCAST_TOK_RE.search(ft):
+        if sk == "M" and _is_broadcast_token(ft):
             return 2
         if sk.startswith("R") and ("M" + sk[1:]) == ft:
             return 2
@@ -966,6 +1095,19 @@ def pick_record(
         # AT&T lists sources first; catalog form tokens are in Intel order.
         slots = list(reversed(slots))
 
+    # A ZA tile operand names the SME tile rows only, and a line without one
+    # never wants them (issue #65 M11): the rows share the mnemonic and
+    # operand count with the plain SVE/NEON forms, so operand shape alone
+    # picks a timed plain row where the ZA forms carry no timing. Same parity
+    # rule as the "_1to" broadcast filter in asm_identity.
+    za_pair = [
+        record
+        for record in candidates
+        if key_names_za_tile(str(getattr(record, "key", "") or "")) == names_za_tile(operands)
+    ]
+    if za_pair:
+        candidates = za_pair
+
     def score(rec: InstructionRecord) -> tuple[int, int, int, int]:
         measured = sum(
             1
@@ -982,6 +1124,49 @@ def pick_record(
     return max(candidates, key=score)
 
 
+def _record_takes_line(record: InstructionRecord, operands: str) -> bool:
+    """Whether the record's key accepts the line's operand classes.
+
+    Classes and accepts come from the catalog: the lsp line classifier and
+    catkey's accept sets. A bare key constrains nothing, a literal key operand
+    (the zero-idiom rows) constrains nothing, and an input the classifier
+    gave no class constrains nothing. Register and memory classes ride each
+    other here exactly like the form pick, so the only hard mismatch is an
+    immediate input against a key operand that accepts no immediate: on an
+    undecided line that pick is a foreign borrow, not an answer (a bare
+    "1, 2, 3" never names a register-class row, issue #65 B2). A decided
+    line named its family already, so only the undecided line is judged.
+    """
+    ops = operands_of_key(record.key)
+    if not ops:
+        return True
+    arch, classes, _reverse, _weak = _classify_line(operands, False)
+    if arch:
+        # A decided line named its family; the family-pinned pick stands.
+        return True
+    if "%" in operands or "$" in operands:
+        # AT&T lists sources first and key operands are in Intel order, so
+        # the classes flip to meet the key (the rule pick_record's slots
+        # use). A sigil-less line keeps its order: Intel and ARM both name
+        # the destination first, as the key does.
+        classes = list(reversed(classes))
+    immediates = [cls for cls in classes if cls in ("i", "lit0", "lit1")]
+    if not immediates:
+        return True
+    if len(ops) != len(classes):
+        return False
+    for cls, op in zip(classes, ops):
+        accept = form_accept(op)
+        if (
+            cls in ("i", "lit0", "lit1")
+            and accept
+            and accept not in LITERAL_ACCEPT
+            and accept.isdisjoint(IMMEDIATE_ACCEPT)
+        ):
+            return False
+    return True
+
+
 # ---------------------------------------------------------------------------
 # Aggregation
 # ---------------------------------------------------------------------------
@@ -1219,8 +1404,45 @@ def collect_ports(
     return ports or None
 
 
-_SUMMARY_BITS_RE = re.compile(r"(\d+)\s*-?\s*bit", re.IGNORECASE)
-_FORM_WIDTH_RE = re.compile(r"[MRI](\d+)")
+def _summary_bits(summary: str) -> str | None:
+    """The digits of the first "NNN - bit" phrase ("32-bit" -> "32"), else None.
+
+    shortcut: str.lower folds no Turkish dotted i in "bit", upgrade if an
+    SDM summary ever carries one
+    """
+    for j in range(len(summary) - 2):
+        if summary[j : j + 3].lower() != "bit":
+            continue
+        k = j
+        while k > 0 and summary[k - 1].isspace():
+            k -= 1
+        if k > 0 and summary[k - 1] == "-":
+            k -= 1
+            while k > 0 and summary[k - 1].isspace():
+                k -= 1
+        end = k
+        while k > 0 and summary[k - 1].isdecimal():
+            k -= 1
+        if k < end:
+            return summary[k:end]
+    return None
+
+
+def _form_widths(key: str) -> list[str]:
+    """The digit groups of the ``M64``-style width tokens of one key."""
+    out: list[str] = []
+    i = 0
+    n = len(key)
+    while i < n:
+        if key[i] in "MRI" and i + 1 < n and key[i + 1].isdecimal():
+            j = i + 1
+            while j < n and key[j].isdecimal():
+                j += 1
+            out.append(key[i + 1 : j])
+            i = j
+        else:
+            i += 1
+    return out
 
 
 def _summary_matches_form(summary: str, record: InstructionRecord) -> bool:
@@ -1229,10 +1451,9 @@ def _summary_matches_form(summary: str, record: InstructionRecord) -> bool:
 
     We only flag a summary as wrong when it declares an explicit bit-width
     that appears nowhere among the form's operand widths."""
-    m = _SUMMARY_BITS_RE.search(summary or "")
-    if not m:
+    declared = _summary_bits(summary or "")
+    if declared is None:
         return True
-    declared = m.group(1)
     widths: list[str] = []
     for op in record.operand_details or []:
         w = op.get("width")
@@ -1240,7 +1461,7 @@ def _summary_matches_form(summary: str, record: InstructionRecord) -> bool:
             widths.append(str(w))
     if not widths:
         key = str(getattr(record, "key", "") or "")
-        widths = _FORM_WIDTH_RE.findall(key)
+        widths = _form_widths(key)
     if not widths:
         return True
     return declared in widths
@@ -1322,12 +1543,15 @@ def _annotate_instruction(
     line_isa: str | None = None,
     line_number: int | None = None,
     identity_cache: dict[str, tuple[InstructionRecord, PerfSummary | None]] | None = None,
+    foreign: bool = False,
 ) -> tuple[str, dict[str, Any] | None]:
     """Return the rendered output line and an optional JSON record.
 
     ``line_isa`` names the family the line's own evidence shows (a pinned
     ``--isa`` counts as one). None marks a neutral line in auto mode: the
-    stream family answers first, then the family that holds rows.
+    stream family answers first, then the family that holds rows. ``foreign``
+    marks a line whose operands parse as no supported arch's operands
+    (PPC, MIPS, ARM32): no supported family's rows answer it (issue #65 B2/B6).
     """
     if stats is not None:
         stats["parsed"] = stats.get("parsed", 0) + 1
@@ -1392,7 +1616,9 @@ def _annotate_instruction(
     else:
         isa = line_isa or opts.isa
         pick_isa = isa
-        if lookup_cache is not None:
+        if foreign:
+            records = []
+        elif lookup_cache is not None:
             records = lookup_cache.get((parsed.mnemonic, isa))
             if records is None:
                 # Module-level call (not a captured reference) so tests can
@@ -1401,16 +1627,21 @@ def _annotate_instruction(
                 lookup_cache[(parsed.mnemonic, isa)] = records
         else:
             records = lookup(parsed.mnemonic, conn, isa=isa)
-        if not records and line_isa is None:
+        if not records and line_isa is None and not foreign:
             # A neutral line whose stream family holds no rows gets the rows
             # of the family that has them (issue #57 batch: jnle, bare b).
+            # A foreign line borrows nothing (issue #65 B2/B6).
             pick_isa = None
             records = lookup(parsed.mnemonic, conn, isa=None)
             if lookup_cache is not None:
                 lookup_cache[(parsed.mnemonic, None)] = records
-        if stats is not None and records:
-            stats["recognized"] = stats.get("recognized", 0) + 1
         record = pick_record(records, arch=opts.arch, operands=parsed.operands, isa=pick_isa)
+        if record is not None and not _record_takes_line(record, parsed.operands):
+            # The key does not take the line's operand classes: a foreign
+            # borrow, not an answer (issue #65 B2).
+            record = None
+        if stats is not None and record is not None:
+            stats["recognized"] = stats.get("recognized", 0) + 1
 
     if record is None:
         if opts.unknown == "drop":
@@ -1569,6 +1800,7 @@ def annotate_stream(
     }
     auto_isa = opts.isa not in ("x86", "arm", "riscv")
     line_family: dict[int, str] = {}
+    foreign: set[int] = set()
     if auto_isa:
         # Assembler acceptance decides each line's family: one llvm-mc run
         # per candidate triple. The register vote below is the fallback when
@@ -1576,6 +1808,13 @@ def annotate_stream(
         probe_texts = [text for _index, text in items]
         families, majority = isa_by_acceptance(probe_texts)
         line_family = {index: family for (index, _text), family in zip(items, families) if family}
+        # The line's own parse names foreign architectures (PPC/MIPS/ARM32):
+        # those lines borrow no rows from a supported family (issue #65 B2/B6).
+        foreign = {
+            index
+            for index, parsed in enumerate(parsed_lines)
+            if parsed.kind == LineKind.INSTRUCTION and _foreign_operands(parsed.operands)
+        }
         # auto: the acceptance majority names the ISA, then the input
         # signals, then the document arch from _document_arch; x86 stays
         # the guess when all stay silent.
@@ -1612,6 +1851,11 @@ def annotate_stream(
             if not collecting_json:
                 yield parsed.raw + "\n"
             continue
+        line_isa = opts.isa
+        if auto_isa:
+            # A pin forces one family; auto mode splits the batch per line,
+            # the assembler verdict first and the register vote as fallback.
+            line_isa = line_family.get(index) or _line_isa(f"{parsed.mnemonic} {parsed.operands}")
         out_line, record = _annotate_instruction(
             parsed,
             opts,
@@ -1619,13 +1863,10 @@ def annotate_stream(
             lookup_cache,
             stats,
             identity_key=identity.get(index),
-            # A pin forces one family; auto mode splits the batch per line,
-            # the assembler verdict first and the register vote as fallback.
-            line_isa=opts.isa
-            if not auto_isa
-            else line_family.get(index) or _line_isa(f"{parsed.mnemonic} {parsed.operands}"),
+            line_isa=line_isa,
             line_number=index + 1,
             identity_cache=identity_cache,
+            foreign=index in foreign if line_isa is None else False,
         )
         if collecting_json:
             if record is not None:

{simdref-0.0.16 → simdref-0.0.18}/src/simdref/arm_instructions.py

@@ -4,7 +4,6 @@ from __future__ import annotations
 
 import html
 import json
-import re
 from collections import Counter
 from functools import lru_cache
 from pathlib import Path