simdref 0.0.16__tar.gz → 0.0.17__tar.gz

{simdref-0.0.16/src/simdref.egg-info → simdref-0.0.17}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: simdref
-Version: 0.0.16
+Version: 0.0.17
 Summary: Searchable SIMD intrinsic and instruction reference with CLI, manpages, TUI, and LSP.
 Author: Marco
 License: GPL-3.0-or-later
@@ -25,7 +25,7 @@ Requires-Dist: msgpack<2,>=1.2.4
 Requires-Dist: PyYAML<7,>=6.0.3
 Requires-Dist: rapidfuzz<4,>=3.14.6
 Requires-Dist: rich<16,>=15.0.0
-Requires-Dist: simdref-llvm-mc==23.1.4; (sys_platform == "linux" and (platform_machine == "x86_64" or platform_machine == "aarch64")) or (sys_platform == "darwin" and (platform_machine == "arm64" or platform_machine == "x86_64")) or (sys_platform == "win32" and platform_machine == "AMD64")
+Requires-Dist: simdref-llvm-mc==23.1.4.post1; (sys_platform == "linux" and (platform_machine == "x86_64" or platform_machine == "aarch64")) or (sys_platform == "darwin" and (platform_machine == "arm64" or platform_machine == "x86_64")) or (sys_platform == "win32" and platform_machine == "AMD64")
 Requires-Dist: textual<9,>=8.2.8
 Requires-Dist: typer<1,>=0.27.3
 Provides-Extra: ingest
@@ -177,6 +177,7 @@ Dev commands
 | Arm AARCHMRS (A64)      | Base instruction forms and operand tables               | live-only²          |
 | riscv-rvv-intrinsic-doc | RVV intrinsics with deterministic instruction refs      | 77,285 intrinsics   |
 | RISC-V unified-db       | RVV instruction forms, ISA tags, description, operation | 3,666 instructions  |
+| NVIDIA PTX ISA          | Instruction ops, syntax, qualifiers, versions, sm_XX    | 1,088 instructions  |
 | Intel Guide perf tables | Per-core latency and throughput                         | 9,134 rows          |
 | Intel Optimization Ref. | Latency and throughput tables (volume 2)                | 3,155 rows          |
 | InstLatX64              | Measured latency and throughput dumps                   | 16,235 rows         |

{simdref-0.0.16 → simdref-0.0.17}/README.md

@@ -142,6 +142,7 @@ Dev commands
 | Arm AARCHMRS (A64)      | Base instruction forms and operand tables               | live-only²          |
 | riscv-rvv-intrinsic-doc | RVV intrinsics with deterministic instruction refs      | 77,285 intrinsics   |
 | RISC-V unified-db       | RVV instruction forms, ISA tags, description, operation | 3,666 instructions  |
+| NVIDIA PTX ISA          | Instruction ops, syntax, qualifiers, versions, sm_XX    | 1,088 instructions  |
 | Intel Guide perf tables | Per-core latency and throughput                         | 9,134 rows          |
 | Intel Optimization Ref. | Latency and throughput tables (volume 2)                | 3,155 rows          |
 | InstLatX64              | Measured latency and throughput dumps                   | 16,235 rows         |

{simdref-0.0.16 → simdref-0.0.17}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "simdref"
-version = "0.0.16"
+version = "0.0.17"
 description = "Searchable SIMD intrinsic and instruction reference with CLI, manpages, TUI, and LSP."
 readme = "README.md"
 requires-python = ">=3.11"
@@ -42,7 +42,7 @@ dependencies = [
   # manylinux x86_64 aarch64, macOS arm64 x86_64 and win_amd64, so the
   # marker keeps the dependency off every other platform (musl included),
   # where pip must see no candidate instead of failing to resolve.
-  'simdref-llvm-mc==23.1.4; (sys_platform == "linux" and (platform_machine == "x86_64" or platform_machine == "aarch64")) or (sys_platform == "darwin" and (platform_machine == "arm64" or platform_machine == "x86_64")) or (sys_platform == "win32" and platform_machine == "AMD64")',
+  'simdref-llvm-mc==23.1.4.post1; (sys_platform == "linux" and (platform_machine == "x86_64" or platform_machine == "aarch64")) or (sys_platform == "darwin" and (platform_machine == "arm64" or platform_machine == "x86_64")) or (sys_platform == "win32" and platform_machine == "AMD64")',
   "textual>=8.2.8,<9",
   "typer>=0.27.3,<1",
 ]

{simdref-0.0.16 → simdref-0.0.17}/src/simdref/annotate.py

@@ -9,7 +9,6 @@ simdref catalog.
 from __future__ import annotations
 
 import json
-import re
 import sqlite3
 import statistics
 import string
@@ -18,6 +17,7 @@ from enum import Enum
 from typing import Any, Iterable, Iterator
 
 from simdref import perf
+from simdref.arm_instructions import _CONDITION_CODES
 from simdref.asm_identity import isa_by_acceptance
 from simdref.catkey import ISA_FAMILY, isa_family as _isa_family
 from simdref.lsp import NO_CATALOG_ROW, _document_arch, identity_keys
@@ -507,11 +507,33 @@ def _lookup_variants(mnemonic: str) -> list[str]:
 
 
 # AArch64 condition-code branches: b.<cond>, no register table covers them.
-_A64_BCOND_RE = re.compile(
-    r"(?<![\w])b\.(?:eq|ne|lt|le|gt|ge|hs|lo|hi|ls|mi|pl|vs|vc|al|nv)(?![\w])"
+# The vocabulary is the first spelling of each cond value in the A64 row table
+# (cs/cc alias the hs/lo spellings the llvm-objdump printers print).
+_A64_BCOND_CODES = frozenset(
+    dict(reversed([(cond, code) for code, cond in _CONDITION_CODES])).values()
 )
 
 
+def _bcond_hits(text: str) -> int:
+    """Count b.<cond> branch mnemonics with word boundaries on both sides."""
+    count = 0
+    i = text.find("b.")
+    while i >= 0:
+        tail = text[i + 2 : i + 4]
+        before = text[i - 1 : i]
+        after = text[i + 4 : i + 5]
+        if (
+            tail in _A64_BCOND_CODES
+            and not (before and (before.isalnum() or before == "_"))
+            and not (after and (after.isalnum() or after == "_"))
+        ):
+            count += 1
+            i = text.find("b.", i + 4)
+        else:
+            i = text.find("b.", i + 2)
+    return count
+
+
 def _drop_symbol_annotations(text: str) -> str:
     """Drop objdump symbol annotations ("<x0+0x50>"): a target, never input."""
     out: list[str] = []
@@ -646,7 +668,7 @@ def detect_isa(lines: Iterable[str]) -> str | None:
         # a register (review finding 1).
         text = _drop_symbol_annotations(f"{parsed.mnemonic} {parsed.operands}")
         vote_arm, vote_riscv, vote_shared = _isa_votes(text)
-        excl_arm += vote_arm + len(_A64_BCOND_RE.findall(text))
+        excl_arm += vote_arm + _bcond_hits(text)
         excl_riscv += vote_riscv
         shared += vote_shared
     if excl_arm or excl_riscv:
@@ -682,10 +704,36 @@ def lookup(
     return []
 
 
-_SIZE_SPECIFIER_RE = re.compile(
-    r"\b(byte|word|dword|qword|xmmword|ymmword|zmmword)\s+ptr\b",
-    re.IGNORECASE,
-)
+_SIZE_WORDS = frozenset({"byte", "word", "dword", "qword", "xmmword", "ymmword", "zmmword"})
+
+
+def _has_size_ptr(text: str) -> bool:
+    """True for a size keyword with a trailing "ptr" ("byte ptr [rdx]")."""
+    n = len(text)
+    i = 0
+    while i + 3 <= n:
+        if text[i : i + 3].lower() != "ptr":
+            i += 1
+            continue
+        if i + 3 < n and (text[i + 3].isalnum() or text[i + 3] == "_"):
+            i += 1
+            continue
+        j = i
+        while j > 0 and text[j - 1].isspace():
+            j -= 1
+        if j == i:
+            i += 1
+            continue
+        for word in _SIZE_WORDS:
+            k = j - len(word)
+            if (
+                k >= 0
+                and text[k:j].lower() == word
+                and not (k > 0 and (text[k - 1].isalnum() or text[k - 1] == "_"))
+            ):
+                return True
+        i += 1
+    return False
 
 
 def _x86_reg_class(name: str) -> str | None:
@@ -750,6 +798,26 @@ def _imm_kind(value: int) -> str:
     return "I64"
 
 
+def _is_number(text: str) -> bool:
+    """True for the literal ``-?0x<hex>`` or ``-?<digits>`` the scans matched."""
+    body = text[1:] if text[:1] == "-" else text
+    if body[:2] == "0x":
+        body = body[2:]
+        return bool(body) and all(char in string.hexdigits for char in body)
+    return bool(body) and body.isdecimal()
+
+
+def _is_symbol(text: str) -> bool:
+    """True for ``[A-Za-z_.$]`` heads with ``\\w.$@`` tails (a plain symbol)."""
+    head = text[:1]
+    return (
+        bool(head)
+        and head.isascii()
+        and (head.isalpha() or head in "_.$")
+        and all(char.isalnum() or char in "_.$@" for char in text[1:])
+    )
+
+
 def _classify_operand(op: str) -> tuple[str, str | None]:
     """Return ``(kind, reg_name_lower)`` for one operand.
 
@@ -763,17 +831,22 @@ def _classify_operand(op: str) -> tuple[str, str | None]:
     if not s:
         return "?", None
     # objdump branch target: an address followed by a <symbol> annotation.
-    if re.fullmatch(r"-?(?:0x[0-9a-fA-F]+|\d+)\s+<[^>]*>", s):
-        return "REL", None
+    lt = s.find("<")
+    if lt > 0 and s.endswith(">") and ">" not in s[lt + 1 : -1]:
+        k = lt
+        while k > 0 and s[k - 1].isspace():
+            k -= 1
+        if k < lt and _is_number(s[:k]):
+            return "REL", None
     # AT&T immediate: $... ; Intel immediate: bare number / 0x... / '$'-less literal
-    if s.startswith("$") or re.fullmatch(r"-?0x[0-9a-fA-F]+|-?\d+", s):
+    if s.startswith("$") or _is_number(s):
         try:
             return _imm_kind(int(s.lstrip("$"), 0)), None
         except ValueError:
             return "I", None
     # AT&T memory: ``(%reg)``, ``disp(%reg,%idx,scale)``, or plain symbol
     # with a ``(...)`` section; Intel memory: ``[...]`` or explicit size ptr.
-    if "(" in s or "[" in s or _SIZE_SPECIFIER_RE.search(s):
+    if "(" in s or "[" in s or _has_size_ptr(s):
         return "M", None
     # Pure register?
     name = (s[1:] if s[:1] == "%" else s).casefold()
@@ -781,7 +854,7 @@ def _classify_operand(op: str) -> tuple[str, str | None]:
     if tok is not None or _is_vec_shaped(name):
         return tok or "?", name
     # Plain symbol (branch target) or unknown.
-    if re.fullmatch(r"[A-Za-z_.$][\w.$@]*", s):
+    if _is_symbol(s):
         return "REL", None
     return "?", None
 
@@ -802,9 +875,6 @@ def _operand_shape(operands: str) -> tuple[list[tuple[str, str | None]], bool]:
     return slots, aliased
 
 
-_FORM_OPS_RE = re.compile(r"\(([^)]*)\)\s*$")
-
-
 def _form_operand_tokens(form_or_key: str) -> list[str]:
     """Extract the comma-separated operand tokens from a catalog form/key.
 
@@ -812,14 +882,25 @@ def _form_operand_tokens(form_or_key: str) -> list[str]:
     ``"RET_NEAR"`` returns ``[]``. Tokens are upper-cased.
     """
     s = str(form_or_key or "")
-    m = _FORM_OPS_RE.search(s)
-    if not m:
+    tail = s.rstrip()
+    if not tail or tail[-1] != ")":
         return []
-    inner = m.group(1)
+    close = len(tail) - 1
+    # The inner text starts at the first "(" after the last ")" before the
+    # closing one, so no ")" splits it (the old group matched the same span).
+    start = tail.find("(", tail.rfind(")", 0, close) + 1)
+    if start < 0:
+        return []
+    inner = tail[start + 1 : close]
     return [t.strip().upper() for t in inner.split(",") if t.strip()]
 
 
-_BROADCAST_TOK_RE = re.compile(r"_1TO\d+$")
+def _is_broadcast_token(token: str) -> bool:
+    """True for a form token with a ``_1toN`` tail (``M16_1to8``)."""
+    start = len(token)
+    while start > 0 and token[start - 1].isdecimal():
+        start -= 1
+    return start < len(token) and start >= 4 and token[start - 4 : start] == "_1TO"
 
 
 def _token_matches_slot(form_tok: str, slot_kind: str) -> bool:
@@ -867,7 +948,7 @@ def _slot_token_score(form_tok: str, slot_kind: str) -> int:
     if not _token_matches_slot(ft, sk):
         # Weak near-misses: a broadcast row wants a {1toN} annotation, and a
         # register can ride a memory row (mov r,r against MOV (M32, R32)).
-        if sk == "M" and _BROADCAST_TOK_RE.search(ft):
+        if sk == "M" and _is_broadcast_token(ft):
             return 2
         if sk.startswith("R") and ("M" + sk[1:]) == ft:
             return 2
@@ -1219,8 +1300,45 @@ def collect_ports(
     return ports or None
 
 
-_SUMMARY_BITS_RE = re.compile(r"(\d+)\s*-?\s*bit", re.IGNORECASE)
-_FORM_WIDTH_RE = re.compile(r"[MRI](\d+)")
+def _summary_bits(summary: str) -> str | None:
+    """The digits of the first "NNN - bit" phrase ("32-bit" -> "32"), else None.
+
+    shortcut: str.lower folds no Turkish dotted i in "bit", upgrade if an
+    SDM summary ever carries one
+    """
+    for j in range(len(summary) - 2):
+        if summary[j : j + 3].lower() != "bit":
+            continue
+        k = j
+        while k > 0 and summary[k - 1].isspace():
+            k -= 1
+        if k > 0 and summary[k - 1] == "-":
+            k -= 1
+            while k > 0 and summary[k - 1].isspace():
+                k -= 1
+        end = k
+        while k > 0 and summary[k - 1].isdecimal():
+            k -= 1
+        if k < end:
+            return summary[k:end]
+    return None
+
+
+def _form_widths(key: str) -> list[str]:
+    """The digit groups of the ``M64``-style width tokens of one key."""
+    out: list[str] = []
+    i = 0
+    n = len(key)
+    while i < n:
+        if key[i] in "MRI" and i + 1 < n and key[i + 1].isdecimal():
+            j = i + 1
+            while j < n and key[j].isdecimal():
+                j += 1
+            out.append(key[i + 1 : j])
+            i = j
+        else:
+            i += 1
+    return out
 
 
 def _summary_matches_form(summary: str, record: InstructionRecord) -> bool:
@@ -1229,10 +1347,9 @@ def _summary_matches_form(summary: str, record: InstructionRecord) -> bool:
 
     We only flag a summary as wrong when it declares an explicit bit-width
     that appears nowhere among the form's operand widths."""
-    m = _SUMMARY_BITS_RE.search(summary or "")
-    if not m:
+    declared = _summary_bits(summary or "")
+    if declared is None:
         return True
-    declared = m.group(1)
     widths: list[str] = []
     for op in record.operand_details or []:
         w = op.get("width")
@@ -1240,7 +1357,7 @@ def _summary_matches_form(summary: str, record: InstructionRecord) -> bool:
             widths.append(str(w))
     if not widths:
         key = str(getattr(record, "key", "") or "")
-        widths = _FORM_WIDTH_RE.findall(key)
+        widths = _form_widths(key)
     if not widths:
         return True
     return declared in widths

{simdref-0.0.16 → simdref-0.0.17}/src/simdref/arm_instructions.py

@@ -4,7 +4,6 @@ from __future__ import annotations
 
 import html
 import json
-import re
 from collections import Counter
 from functools import lru_cache
 from pathlib import Path

{simdref-0.0.16 → simdref-0.0.17}/src/simdref/asm_identity.py

@@ -26,38 +26,139 @@ the platforms it has wheels for; everywhere else point the env vars at a
 
 from __future__ import annotations
 
+import hashlib
 import json
 import os
 import sqlite3
 import subprocess
 import tempfile
+from concurrent.futures import ThreadPoolExecutor
 from dataclasses import dataclass, field
 from pathlib import Path
 
 from simdref.catkey import ISA_FAMILY
 
 # Measured invocation of the 144/401/703 corpora probes (asm-pip/probe).
+# The riscv entries carry no "mattr": _mattr_for derives it from the tool.
 _ARCH_CFG: dict[str, dict] = {
-    "x86": {
-        "triple": "x86_64-unknown-linux-gnu",
-        "mattr": "+avx512f,+avx512bw,+avx512dq,+avx512vl,+avx512vbmi,+avx512vbmi2,"
-        "+avx512vnni,+avx512bitalg,+avx512vpopcntdq,+avx512ifma,+vaes,+vpclmulqdq,"
-        "+avx,+avx2,+fma,+f16c,+bmi,+bmi2,+lzcnt,+movbe",
-    },
-    "aarch64": {
-        "triple": "aarch64-unknown-linux-gnu",
-        "mattr": "+sve,+sve2,+sve2p1,+sme,+sme2,+sme2p1,+lse,+gcs,+aes",
-    },
+    "x86": {"triple": "x86_64-unknown-linux-gnu", "mattr": ""},
+    "aarch64": {"triple": "aarch64-unknown-linux-gnu", "mattr": "+all"},
     "arm": {"triple": "armv7-unknown-linux-gnueabihf", "mattr": "+neon"},
-    "riscv32": {
-        "triple": "riscv32-unknown-linux-gnu",
-        "mattr": "+m,+a,+f,+d,+c,+v,+zba,+zbb,+zbs",
-    },
-    "riscv64": {
-        "triple": "riscv64-unknown-linux-gnu",
-        "mattr": "+m,+a,+f,+d,+c,+v,+zba,+zbb,+zbs,+zvbb,+zvkb,+zvkned,+zfh",
-    },
+    "riscv32": {"triple": "riscv32-unknown-linux-gnu"},
+    "riscv64": {"triple": "riscv64-unknown-linux-gnu"},
 }
+# The ratified profile each riscv derivation anchors on (spike feat H2).
+_RV_ANCHOR = {"riscv32": "+m,+a,+f,+d,+c,+v", "riscv64": "+rva23u64"}
+_RV_MATTR_CACHE: dict[tuple[str, str], str] = {}
+
+
+def _rv_help_names(llvm_mc: str, arch: str) -> list[str]:
+    """Extension names of ``llvm-mc -mattr=help``, in help order.
+
+    An extension line has the shape ``name - 'Name' (...)``. A tuning flag
+    (fusion-*, reserve-x*) has no quoted name, so the quote check keeps only
+    extensions. Vendor (x*) and experimental names drop out: the vendor ones
+    reuse the custom opcode spaces."""
+    # stdin=DEVNULL: -mattr=help keeps reading stdin, and in the LSP server
+    # stdin is the JSON-RPC stream (the derive would eat requests and block).
+    run = subprocess.run(
+        [llvm_mc, f"--triple={_ARCH_CFG[arch]['triple']}", "-mattr=help"],
+        stdin=subprocess.DEVNULL,
+        capture_output=True,
+        text=True,
+    )
+    _head, sep, tail = (run.stdout + run.stderr).partition("Available features for this target:")
+    names = []
+    for line in tail.splitlines() if sep else []:
+        left, sep2, _desc = line.strip().partition(" - '")
+        name = left.strip()
+        if sep2 and name and not any(ch.isspace() for ch in name):
+            if not name.startswith(("x", "experimental-")):
+                names.append(name)
+    return names
+
+
+def _rv_accepts(llvm_mc: str, arch: str, mattr: str) -> bool:
+    """True when llvm-mc assembles one x31 instruction under ``mattr``."""
+    run = subprocess.run(
+        [llvm_mc, f"--triple={_ARCH_CFG[arch]['triple']}", f"-mattr={mattr}", "-show-encoding"],
+        # x31: a base-shrinking entry (e) fails here.
+        input="add t6, t6, t6\n",
+        capture_output=True,
+        text=True,
+    )
+    return run.returncode == 0 and "encoding" in run.stdout
+
+
+def _rv_mattr(llvm_mc: str, arch: str) -> str:
+    """The riscv ``-mattr``, derived from llvm-mc and cached per tool path.
+
+    Never a hand list (spike feat H2): probe each non-vendor extension next
+    to the ratified anchor and keep what assembles, then keep a name only
+    when it also joins the union so far. The anchor decides each
+    incompatible pair (F over Zfinx, Zcd over Zcmp), and an extension that
+    conflicts with it drops out; a pair conflict can need a third
+    extension's implication, so the union test covers that.
+
+    The cache outlives the process (the derive costs about a second and the
+    CLI is one-shot): one file per tool path, size and mtime, so a rebuilt
+    tool re-derives."""
+    cached = _RV_MATTR_CACHE.get((llvm_mc, arch))
+    if cached is not None:
+        return cached
+    cache_file = _rv_mattr_cache_file(llvm_mc, arch)
+    try:
+        cached = cache_file.read_text().strip()
+    except OSError:
+        cached = ""
+    if not cached:
+        names = _rv_help_names(llvm_mc, arch)
+        # Ratified extensions first: on a conflict the earlier one stays.
+        names.sort(key=lambda name: name.startswith("experimental-"))
+        anchor = _RV_ANCHOR[arch]
+        with ThreadPoolExecutor(16) as pool:
+            verdict = list(
+                pool.map(lambda name: _rv_accepts(llvm_mc, arch, f"{anchor},+{name}"), names)
+            )
+        kept: list[str] = []
+        for name, ok in zip(names, verdict):
+            union = ",".join([anchor] + [f"+{k}" for k in kept + [name]])
+            if ok and _rv_accepts(llvm_mc, arch, union):
+                kept.append(name)
+        cached = ",".join([anchor] + [f"+{k}" for k in kept])
+        try:
+            cache_file.parent.mkdir(parents=True, exist_ok=True)
+            tmp = cache_file.with_name(f"{cache_file.name}.tmp{os.getpid()}")
+            tmp.write_text(cached)
+            os.replace(tmp, cache_file)
+        except OSError:
+            pass  # a read-only cache dir costs one re-derive per process
+    _RV_MATTR_CACHE[(llvm_mc, arch)] = cached
+    return cached
+
+
+def _rv_mattr_cache_file(llvm_mc: str, arch: str) -> Path:
+    """The cache file for one tool path: keyed by path, size and mtime."""
+    try:
+        stat = os.stat(llvm_mc)
+        stamp = f"{llvm_mc}:{stat.st_size}:{stat.st_mtime_ns}:{arch}"
+    except OSError:
+        stamp = f"{llvm_mc}:{arch}"
+    name = hashlib.sha256(stamp.encode()).hexdigest()[:16]
+    base = os.environ.get("XDG_CACHE_HOME") or os.path.join(Path.home(), ".cache")
+    return Path(base) / "simdref" / f"rv-mattr-{name}"
+
+
+def _mattr_for(arch: str, llvm_mc: str) -> str:
+    """The ``-mattr`` string for one arch.
+
+    x86 needs none (its assembler accepts every extension by default) and
+    arm keeps its one flag. The riscv string comes from _rv_mattr."""
+    if arch.startswith("riscv"):
+        return _rv_mattr(llvm_mc, arch)
+    return _ARCH_CFG[arch]["mattr"]
+
+
 _X86_SYNTAX_FLAG = {"att": "-x86-asm-syntax=att", "intel": "-x86-asm-syntax=intel"}
 # uops.info eosz attribute values per effective operand size.
 _EOSZ_ATTR = {16: "1", 32: "2", 64: "3"}
@@ -303,8 +404,9 @@ def _probe_lines_uncached(
     every other instruction line reports no row (review E1/E2)."""
     cfg = _ARCH_CFG[arch]
     cmd = [llvm_mc, f"--triple={cfg['triple']}", "-show-encoding", "-show-inst"]
-    if mattr or cfg["mattr"]:
-        cmd.append(f"-mattr={mattr or cfg['mattr']}")
+    use = mattr or _mattr_for(arch, llvm_mc)
+    if use:
+        cmd.append(f"-mattr={use}")
     if arch == "x86":
         cmd.append(_X86_SYNTAX_FLAG[syntax])
 
@@ -441,7 +543,9 @@ def _probe_lines_split(lines: list[str], arch: str, syntax: str, llvm_mc: str) -
             continue
         mattr = None
         if not is_compressed:
-            mattr = ",".join(t for t in _ARCH_CFG[arch]["mattr"].split(",") if t != "+c")
+            # -c,-zca drops every Zc* family (zcb, zcmop, zcd), which the
+            # derived set names and a "+c" strip would leave on.
+            mattr = _mattr_for(arch, llvm_mc) + ",-c,-zca"
         sub = _probe_lines([lines[i] for i in indexes], arch, syntax, llvm_mc, mattr=mattr)
         for index, entry in zip(indexes, sub):
             merged = dict(entry)
@@ -808,8 +912,9 @@ def _string_spans_lines(lines: list[str], arch: str, syntax: str, llvm_mc: str |
         raise ToolUnavailableError("llvm-mc not found (set SIMDREF_LLVM_MC)")
     cfg = _ARCH_CFG[arch]
     cmd = [llvm_mc, f"--triple={cfg['triple']}"]
-    if cfg["mattr"]:
-        cmd.append(f"-mattr={cfg['mattr']}")
+    use = _mattr_for(arch, llvm_mc)
+    if use:
+        cmd.append(f"-mattr={use}")
     if arch == "x86":
         cmd.append(_X86_SYNTAX_FLAG[syntax])
     pending = []
@@ -963,62 +1068,6 @@ def identify(
 # whose printed mnemonic equals the line's own text mnemonic (objdump prints
 # the expanded or alias name too: jal, flw, sext.w). Both or neither match
 # keeps the rv64 result (the current default).
-def _rv64_only_ext(line: str) -> str | None:
-    """The extension name in an "'X' is only supported for 'rv64'" error line.
-
-    Returns None for any other line. The name sits after the last single quote
-    before the fixed tail, so a prefix like "error: ..." is ignored.
-    """
-    head, sep, _tail = line.partition("' is only supported for 'rv64'")
-    if not sep:
-        return None
-    return head.rpartition("'")[2] or None
-
-
-_RV32_MATTR_CACHE: dict[tuple[str, str], str] = {}
-
-
-def _rv32_decode_mattr(llvm_mc: str) -> str:
-    """The riscv32 decode -mattr: the riscv64 one minus rv64-only extensions.
-
-    Derived from llvm-mc's own errors (never hand-listed): the tool rejects
-    an rv64-only extension on the rv32 triple by name. shortcut: an extension
-    named differently in the error keeps its token, upgrade if a tool build
-    rejects it silently."""
-    base = _ARCH_CFG["riscv64"]["mattr"]
-    cached = _RV32_MATTR_CACHE.get((llvm_mc, base))
-    if cached is None:
-        tokens = base.split(",")
-        while True:
-            run = subprocess.run(
-                [
-                    llvm_mc,
-                    f"--triple={_ARCH_CFG['riscv32']['triple']}",
-                    f"-mattr={','.join(tokens)}",
-                    "-show-encoding",
-                ],
-                input="",
-                capture_output=True,
-                text=True,
-            )
-            drop = {
-                name.casefold()
-                for line in run.stderr.splitlines()
-                for name in [_rv64_only_ext(line)]
-                if name
-            }
-            if not drop:
-                break
-            remaining = [token for token in tokens if token.lstrip("+").casefold() not in drop]
-            # guard: the tool names an extension absent from the token list,
-            # so nothing shrank; break here or the loop spins forever
-            if len(remaining) == len(tokens):
-                break
-            tokens = remaining
-        cached = _RV32_MATTR_CACHE[(llvm_mc, base)] = ",".join(tokens)
-    return cached
-
-
 def _parse_disasm(listing: str) -> dict[bytes, tuple[str, str]]:
     """One (printed mnemonic, MCInst opcode) per decoded word.
 
@@ -1052,7 +1101,7 @@ def _rv_xlen_decodes(
     gate: only an undecided RVC line pays the decode)."""
     missing = [raw for raw in dict.fromkeys(raws) if (llvm_mc, xlen, raw) not in _RV_DECODE_CACHE]
     if missing:
-        mattr = _ARCH_CFG["riscv64"]["mattr"] if xlen == 64 else _rv32_decode_mattr(llvm_mc)
+        mattr = _mattr_for(f"riscv{xlen}", llvm_mc)
         hexed = [" ".join(f"0x{byte:02x}" for byte in raw) for raw in missing]
         run = subprocess.run(
             [
@@ -1282,9 +1331,6 @@ def _identify_words(probed, results, catalog: _Catalog, arch: str) -> None:
         _rv_xlen_resolve(probed, results, catalog)
 
 
-_ENDBR_BYTES = {"f30f1efa": "ENDBR64", "f30f1efb": "ENDBR32"}
-
-
 def _identify_x86(probed, results, catalog: _Catalog, xed: str) -> None:
     pending = []
     for entry, result in zip(probed, results):
@@ -1300,7 +1346,7 @@ def _identify_x86(probed, results, catalog: _Catalog, xed: str) -> None:
     if not pending:
         return
     hexes = [_bytes_to_words(entry.get("bytes")).hex() for entry, _result in pending]
-    for (entry, result), facts, hexed in zip(pending, _xed_facts(hexes, xed), hexes):
+    for (entry, result), facts in zip(pending, _xed_facts(hexes, xed)):
         # A fixup placeholder covers the immediate value (audit A1): the
         # pick must not read it, and a row carrying an immzero claim about
         # it would be a guess either way.
@@ -1308,8 +1354,7 @@ def _identify_x86(probed, results, catalog: _Catalog, xed: str) -> None:
         if "error" in facts:
             result.reason = f"no catalog row (XED {facts['error']})"
             continue
-        # XED decodes ENDBR32/64 as the NOP iform NOP_GPRv_GPRv_0F1E, which no uops.info row carries
-        pool = catalog.iform_pools.get(_ENDBR_BYTES.get(hexed, facts["iform"]), [])
+        pool = catalog.iform_pools.get(facts["iform"], [])
         if not pool:
             result.reason = f"no catalog row (iform {facts['iform']} absent)"
             continue