simdref 0.0.15__tar.gz → 0.0.16__tar.gz

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (171) hide show
  1. {simdref-0.0.15/src/simdref.egg-info → simdref-0.0.16}/PKG-INFO +62 -48
  2. {simdref-0.0.15 → simdref-0.0.16}/README.md +50 -36
  3. {simdref-0.0.15 → simdref-0.0.16}/pyproject.toml +26 -18
  4. simdref-0.0.16/src/simdref/annotate.py +1637 -0
  5. simdref-0.0.16/src/simdref/arm_instructions.py +921 -0
  6. simdref-0.0.16/src/simdref/asm_identity.py +1684 -0
  7. simdref-0.0.16/src/simdref/asmline.py +283 -0
  8. simdref-0.0.16/src/simdref/catkey.py +417 -0
  9. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/cli.py +217 -314
  10. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/display.py +275 -150
  11. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/export.py +106 -33
  12. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/filters.py +2 -2
  13. simdref-0.0.16/src/simdref/htmltext.py +218 -0
  14. simdref-0.0.16/src/simdref/ingest.py +37 -0
  15. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/ingest_catalog.py +286 -113
  16. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/ingest_pdf.py +39 -0
  17. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/ingest_sources.py +239 -22
  18. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/lsp.py +553 -458
  19. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/manpages.py +10 -15
  20. simdref-0.0.16/src/simdref/operands.py +91 -0
  21. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/pdfparse/__init__.py +1 -0
  22. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/pdfparse/intel.py +534 -34
  23. simdref-0.0.16/src/simdref/perf.py +480 -0
  24. simdref-0.0.16/src/simdref/perf_sources/amd_swopt.py +789 -0
  25. simdref-0.0.16/src/simdref/perf_sources/arm_swopt.py +477 -0
  26. simdref-0.0.16/src/simdref/perf_sources/cores.py +182 -0
  27. simdref-0.0.16/src/simdref/perf_sources/instlatx64.py +372 -0
  28. simdref-0.0.16/src/simdref/perf_sources/intel_guide.py +254 -0
  29. simdref-0.0.16/src/simdref/perf_sources/intel_optref.py +555 -0
  30. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/perf_sources/llvm_mca.py +153 -8
  31. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/perf_sources/llvm_scheduling.py +6 -21
  32. simdref-0.0.16/src/simdref/perf_sources/merge.py +489 -0
  33. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/queries.py +15 -85
  34. simdref-0.0.16/src/simdref/regtable.py +797 -0
  35. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/riscv.py +171 -105
  36. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/search.py +35 -65
  37. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/storage.py +172 -154
  38. simdref-0.0.16/src/simdref/tablecols.py +182 -0
  39. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/tui.py +133 -226
  40. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/ui_labels.py +3 -2
  41. {simdref-0.0.15 → simdref-0.0.16/src/simdref.egg-info}/PKG-INFO +62 -48
  42. {simdref-0.0.15 → simdref-0.0.16}/src/simdref.egg-info/SOURCES.txt +68 -0
  43. {simdref-0.0.15 → simdref-0.0.16}/src/simdref.egg-info/requires.txt +13 -9
  44. simdref-0.0.16/tests/test_a1_sdm_parser.py +141 -0
  45. simdref-0.0.16/tests/test_a2_perf_rule.py +111 -0
  46. simdref-0.0.16/tests/test_a4_arm_pdfrefs.py +50 -0
  47. simdref-0.0.16/tests/test_a5_offline_aarchmrs.py +45 -0
  48. simdref-0.0.16/tests/test_amd_match_llvm_mc.py +124 -0
  49. {simdref-0.0.15 → simdref-0.0.16}/tests/test_annotate.py +180 -2
  50. {simdref-0.0.15 → simdref-0.0.16}/tests/test_annotate_positions.py +8 -4
  51. simdref-0.0.16/tests/test_arrangement_tail.py +27 -0
  52. {simdref-0.0.15 → simdref-0.0.16}/tests/test_asm_identity.py +63 -12
  53. simdref-0.0.16/tests/test_asmline.py +89 -0
  54. {simdref-0.0.15 → simdref-0.0.16}/tests/test_audit_coverage.py +20 -0
  55. simdref-0.0.16/tests/test_b1_latency_pairs.py +178 -0
  56. simdref-0.0.16/tests/test_b2_metadata.py +275 -0
  57. simdref-0.0.16/tests/test_b3_sdm_forms.py +268 -0
  58. simdref-0.0.16/tests/test_b4_descriptions_provenance.py +198 -0
  59. simdref-0.0.16/tests/test_b5_linking.py +135 -0
  60. simdref-0.0.16/tests/test_b5_perf_family.py +79 -0
  61. simdref-0.0.16/tests/test_b5_sme.py +173 -0
  62. simdref-0.0.16/tests/test_c0_perf_priority.py +207 -0
  63. simdref-0.0.16/tests/test_catkey.py +142 -0
  64. {simdref-0.0.15 → simdref-0.0.16}/tests/test_cli_bootstrap_progress.py +92 -0
  65. {simdref-0.0.15 → simdref-0.0.16}/tests/test_coverage_live.py +1 -4
  66. {simdref-0.0.15 → simdref-0.0.16}/tests/test_coverage_parity.py +1 -4
  67. {simdref-0.0.15 → simdref-0.0.16}/tests/test_display.py +4 -3
  68. simdref-0.0.16/tests/test_display_scanners.py +66 -0
  69. {simdref-0.0.15 → simdref-0.0.16}/tests/test_export.py +2 -0
  70. simdref-0.0.16/tests/test_export_viz.py +127 -0
  71. simdref-0.0.16/tests/test_fixui_display.py +158 -0
  72. simdref-0.0.16/tests/test_htmltext.py +40 -0
  73. {simdref-0.0.15 → simdref-0.0.16}/tests/test_ingest_enc_fields.py +9 -7
  74. {simdref-0.0.15 → simdref-0.0.16}/tests/test_ingest_sources.py +168 -17
  75. simdref-0.0.16/tests/test_int_arm_isa_label.py +33 -0
  76. simdref-0.0.16/tests/test_int_core_ids.py +90 -0
  77. simdref-0.0.16/tests/test_int_ingest_registration.py +82 -0
  78. simdref-0.0.16/tests/test_int_sdm_family_fallback.py +61 -0
  79. simdref-0.0.16/tests/test_isa_detect_llvm_mc.py +225 -0
  80. {simdref-0.0.15 → simdref-0.0.16}/tests/test_issue2_fixes.py +1 -1
  81. simdref-0.0.16/tests/test_issue_51.py +224 -0
  82. simdref-0.0.16/tests/test_issue_52.py +79 -0
  83. simdref-0.0.16/tests/test_issue_53_54.py +122 -0
  84. simdref-0.0.16/tests/test_issue_55.py +40 -0
  85. simdref-0.0.16/tests/test_issue_56_57a.py +285 -0
  86. simdref-0.0.16/tests/test_issue_57_cpi.py +181 -0
  87. simdref-0.0.16/tests/test_issue_60_c1.py +59 -0
  88. simdref-0.0.16/tests/test_issue_60_contract.py +135 -0
  89. simdref-0.0.16/tests/test_issue_60_crossarch.py +445 -0
  90. simdref-0.0.16/tests/test_issue_60_matcher.py +353 -0
  91. simdref-0.0.16/tests/test_issue_65_arm_alias.py +204 -0
  92. simdref-0.0.16/tests/test_issue_65_compressed.py +58 -0
  93. simdref-0.0.16/tests/test_issue_65_identity.py +288 -0
  94. simdref-0.0.16/tests/test_issue_65_m1.py +302 -0
  95. simdref-0.0.16/tests/test_issue_65_perfdata.py +396 -0
  96. simdref-0.0.16/tests/test_issue_65_text.py +275 -0
  97. simdref-0.0.16/tests/test_issue_65_timing.py +206 -0
  98. simdref-0.0.16/tests/test_issues_51_57_join.py +226 -0
  99. {simdref-0.0.15 → simdref-0.0.16}/tests/test_leftover_arm_form_pick.py +177 -29
  100. {simdref-0.0.15 → simdref-0.0.16}/tests/test_leftover_riscv_shared.py +24 -3
  101. {simdref-0.0.15 → simdref-0.0.16}/tests/test_lsp_stdio.py +136 -38
  102. {simdref-0.0.15 → simdref-0.0.16}/tests/test_no_catalog_row.py +2 -0
  103. simdref-0.0.16/tests/test_objdump_listings.py +109 -0
  104. simdref-0.0.16/tests/test_operands.py +41 -0
  105. {simdref-0.0.15 → simdref-0.0.16}/tests/test_pdfparse.py +53 -24
  106. {simdref-0.0.15 → simdref-0.0.16}/tests/test_perf.py +23 -31
  107. simdref-0.0.16/tests/test_perf_source_amd_swopt.py +178 -0
  108. simdref-0.0.16/tests/test_perf_source_arm_swopt.py +133 -0
  109. simdref-0.0.16/tests/test_perf_source_instlatx64.py +91 -0
  110. simdref-0.0.16/tests/test_perf_source_intel_guide.py +108 -0
  111. simdref-0.0.16/tests/test_perf_source_intel_optref.py +89 -0
  112. {simdref-0.0.15 → simdref-0.0.16}/tests/test_presentation.py +5 -0
  113. simdref-0.0.16/tests/test_regtable.py +117 -0
  114. simdref-0.0.16/tests/test_release_tag_pin.py +24 -0
  115. {simdref-0.0.15 → simdref-0.0.16}/tests/test_search.py +54 -22
  116. simdref-0.0.16/tests/test_shared_source_helpers.py +88 -0
  117. simdref-0.0.16/tests/test_storage_alnum.py +39 -0
  118. simdref-0.0.16/tests/test_tablecols.py +42 -0
  119. simdref-0.0.16/tests/test_update_build_stamp.py +64 -0
  120. {simdref-0.0.15 → simdref-0.0.16}/tests/test_vendor_riscv_sources.py +31 -0
  121. {simdref-0.0.15 → simdref-0.0.16}/tests/test_version_matches_pyproject.py +1 -4
  122. simdref-0.0.16/tests/test_x86_key_widths.py +84 -0
  123. simdref-0.0.15/src/simdref/annotate.py +0 -881
  124. simdref-0.0.15/src/simdref/arm_instructions.py +0 -594
  125. simdref-0.0.15/src/simdref/asm_identity.py +0 -928
  126. simdref-0.0.15/src/simdref/ingest.py +0 -119
  127. simdref-0.0.15/src/simdref/perf.py +0 -268
  128. simdref-0.0.15/src/simdref/perf_sources/cores.py +0 -386
  129. simdref-0.0.15/src/simdref/perf_sources/merge.py +0 -122
  130. {simdref-0.0.15 → simdref-0.0.16}/LICENSE +0 -0
  131. {simdref-0.0.15 → simdref-0.0.16}/setup.cfg +0 -0
  132. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/__init__.py +0 -0
  133. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/__main__.py +0 -0
  134. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/models.py +0 -0
  135. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/pdfparse/base.py +0 -0
  136. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/pdfparse/registry.py +0 -0
  137. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/pdfparse/types.py +0 -0
  138. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/pdfrefs.py +0 -0
  139. {simdref-0.0.15 → simdref-0.0.16}/src/simdref/perf_sources/__init__.py +0 -0
  140. {simdref-0.0.15 → simdref-0.0.16}/src/simdref.egg-info/dependency_links.txt +0 -0
  141. {simdref-0.0.15 → simdref-0.0.16}/src/simdref.egg-info/entry_points.txt +0 -0
  142. {simdref-0.0.15 → simdref-0.0.16}/src/simdref.egg-info/top_level.txt +0 -0
  143. {simdref-0.0.15 → simdref-0.0.16}/tests/test_asm_wire.py +0 -0
  144. {simdref-0.0.15 → simdref-0.0.16}/tests/test_auto_update_on_version_change.py +0 -0
  145. {simdref-0.0.15 → simdref-0.0.16}/tests/test_cli_bare_query.py +0 -0
  146. {simdref-0.0.15 → simdref-0.0.16}/tests/test_cli_help.py +0 -0
  147. {simdref-0.0.15 → simdref-0.0.16}/tests/test_cli_llm.py +0 -0
  148. {simdref-0.0.15 → simdref-0.0.16}/tests/test_filters.py +0 -0
  149. {simdref-0.0.15 → simdref-0.0.16}/tests/test_intel_operation_and_url.py +0 -0
  150. {simdref-0.0.15 → simdref-0.0.16}/tests/test_issues_23_24_25.py +0 -0
  151. {simdref-0.0.15 → simdref-0.0.16}/tests/test_leftover_arm_postindex.py +0 -0
  152. {simdref-0.0.15 → simdref-0.0.16}/tests/test_leftover_att_movx.py +0 -0
  153. {simdref-0.0.15 → simdref-0.0.16}/tests/test_leftover_autoupdate.py +0 -0
  154. {simdref-0.0.15 → simdref-0.0.16}/tests/test_leftover_catalog_gaps.py +0 -0
  155. {simdref-0.0.15 → simdref-0.0.16}/tests/test_leftover_ingest_isa_merge.py +0 -0
  156. {simdref-0.0.15 → simdref-0.0.16}/tests/test_leftover_intel_size.py +0 -0
  157. {simdref-0.0.15 → simdref-0.0.16}/tests/test_leftover_perf_join.py +0 -0
  158. {simdref-0.0.15 → simdref-0.0.16}/tests/test_lsp_web.py +0 -0
  159. {simdref-0.0.15 → simdref-0.0.16}/tests/test_models.py +0 -0
  160. {simdref-0.0.15 → simdref-0.0.16}/tests/test_perf_sources.py +0 -0
  161. {simdref-0.0.15 → simdref-0.0.16}/tests/test_preset_persistence.py +0 -0
  162. {simdref-0.0.15 → simdref-0.0.16}/tests/test_riscv_docs_pages.py +0 -0
  163. {simdref-0.0.15 → simdref-0.0.16}/tests/test_search_pushdown.py +0 -0
  164. {simdref-0.0.15 → simdref-0.0.16}/tests/test_source_kind_filter.py +0 -0
  165. {simdref-0.0.15 → simdref-0.0.16}/tests/test_source_validation.py +0 -0
  166. {simdref-0.0.15 → simdref-0.0.16}/tests/test_storage_payload.py +0 -0
  167. {simdref-0.0.15 → simdref-0.0.16}/tests/test_storage_schema.py +0 -0
  168. {simdref-0.0.15 → simdref-0.0.16}/tests/test_tui.py +0 -0
  169. {simdref-0.0.15 → simdref-0.0.16}/tests/test_ui_labels_parity.py +0 -0
  170. {simdref-0.0.15 → simdref-0.0.16}/tests/test_vendor_riscv_categories.py +0 -0
  171. {simdref-0.0.15 → simdref-0.0.16}/tests/test_x86_linking.py +0 -0
@@ -1,6 +1,6 @@
1
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  Metadata-Version: 2.4
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  Name: simdref
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- Version: 0.0.15
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+ Version: 0.0.16
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  Summary: Searchable SIMD intrinsic and instruction reference with CLI, manpages, TUI, and LSP.
5
5
  Author: Marco
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  License: GPL-3.0-or-later
@@ -10,27 +10,27 @@ Classifier: Intended Audience :: Developers
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  Classifier: License :: OSI Approved :: GNU General Public License v3 or later (GPLv3+)
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  Classifier: Operating System :: OS Independent
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  Classifier: Programming Language :: Python :: 3
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- Classifier: Programming Language :: Python :: 3.10
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  Classifier: Programming Language :: Python :: 3.11
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  Classifier: Programming Language :: Python :: 3.12
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  Classifier: Programming Language :: Python :: 3.13
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  Classifier: Programming Language :: Python :: 3.14
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  Classifier: Topic :: Software Development :: Documentation
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  Classifier: Topic :: Software Development :: Libraries :: Python Modules
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- Requires-Python: >=3.10
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+ Requires-Python: >=3.11
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  Description-Content-Type: text/markdown
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  License-File: LICENSE
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- Requires-Dist: click<9,>=8.5
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- Requires-Dist: httpx<1,>=0.28
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- Requires-Dist: msgpack<2,>=1.2.1
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- Requires-Dist: pdfplumber<1,>=0.11.10
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- Requires-Dist: PyMuPDF<2,>=1.28
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+ Requires-Dist: click<9,>=8.5.0
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+ Requires-Dist: httpx<1,>=0.28.1
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+ Requires-Dist: msgpack<2,>=1.2.4
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  Requires-Dist: PyYAML<7,>=6.0.3
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- Requires-Dist: rapidfuzz<4,>=3.14
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- Requires-Dist: rich<16,>=15
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+ Requires-Dist: rapidfuzz<4,>=3.14.6
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+ Requires-Dist: rich<16,>=15.0.0
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  Requires-Dist: simdref-llvm-mc==23.1.4; (sys_platform == "linux" and (platform_machine == "x86_64" or platform_machine == "aarch64")) or (sys_platform == "darwin" and (platform_machine == "arm64" or platform_machine == "x86_64")) or (sys_platform == "win32" and platform_machine == "AMD64")
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- Requires-Dist: textual<9,>=8.2
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- Requires-Dist: typer<1,>=0.27
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+ Requires-Dist: textual<9,>=8.2.8
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+ Requires-Dist: typer<1,>=0.27.3
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+ Provides-Extra: ingest
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+ Requires-Dist: pdfplumber<1,>=0.11.10; extra == "ingest"
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+ Requires-Dist: PyMuPDF<3,>=2.1; platform_python_implementation == "CPython" and extra == "ingest"
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  Dynamic: license-file
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36
36
  # simdref
@@ -68,8 +68,11 @@ isa # open the TUI
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  ```
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69
 
70
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  The package installs two equivalent executables, `isa` and `simdref`. The
71
- catalog download does not use `llvm-mca`. Only `isa build` uses
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- `llvm-mca` 18+ on `PATH`.
71
+ catalog download does not use `llvm-mca`. Python 3.11 or newer is
72
+ necessary. The plain `pip install simdref` covers queries, the LSP and
73
+ `isa update`. `isa build` uses the ingest extra:
74
+ `pip install 'simdref[ingest]'`, or `uv tool install 'simdref[ingest]'`
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+ with uv. Only `isa build` uses `llvm-mca` 18+ on `PATH`.
73
76
 
74
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  Pre-release builds live on TestPyPI:
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78
 
@@ -86,7 +89,6 @@ isa VPADDD # exact instruction -> detailed view
86
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  isa _mm_add # fuzzy -> ranked search results
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  isa mm add # tokenized query -> intrinsic-biased search
88
91
  isa ADD # mnemonic-like -> instruction-biased search
89
- isa VADDPS 2 # pick variant #2 from the last result list
90
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  isa # open the TUI
91
93
  ```
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@@ -115,13 +117,13 @@ Editor clients, one for each editor:
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117
  Each client shows a one-line brief at the end of each instruction line and
116
118
  the full manpage on hover, from the local catalog.
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119
 
118
- The LLM interface writes JSON and NDJSON with exit codes 0 (match), 1 (bad
119
- flag), 2 (no match), 3 (ambiguous):
120
+ The LLM interface writes JSON and NDJSON with exit codes 0 (match), 1 (usage
121
+ error), 2 (no match or parser error), 3 (ambiguous):
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122
 
121
123
  ```bash
122
- isa llm query _mm_add_ps --source-kind measured
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+ isa llm query vaddps --source-kind measured
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125
  echo -e "_mm_add_ps\nVPADDD" | isa llm batch
124
- isa llm list --pattern "*gather*" --isa Intel
126
+ isa llm list --pattern "*gather*"
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127
  ```
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128
 
127
129
  See [docs/LLM.md](docs/LLM.md) for the payload shape.
@@ -142,44 +144,53 @@ each instruction line. The output stays valid assembly.
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143
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  Commands
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145
- | Command | Description |
146
- | ----------------------- | ------------------------------------------------------------------------- |
147
- | `isa` | Open the TUI |
148
- | `isa <query>` | Open the TUI with the query in a TTY, else print ranked results to stdout |
149
- | `isa doctor` | Check the install, non-zero exit on failure |
150
- | `isa update` | Download the pre-built catalog, `--from-release` for the GitHub Release |
151
- | `isa annotate <file.s>` | Annotate a `.s` file with summaries and latency/CPI, writes `<file>.sa` |
152
- | `isa man <name>` | Show a manpage, made on demand |
153
- | `isa install-manpages` | Pre-generate man7 pages so plain `man vpaddd` works |
154
- | `isa llm query <q>` | Strict lookup to JSON, NDJSON, or Markdown |
155
- | `isa llm batch` | Resolve many queries from stdin in one invocation |
156
- | `isa llm list` | Write the FilterSpec or stream matching catalog entries |
157
- | `isa llm schema` | Print the JSON schema for `llm` payloads |
147
+ | Command | Description |
148
+ | ----------------------- | ----------------------------------------------------------------------- |
149
+ | `isa` | Open the TUI |
150
+ | `isa <query>` | Fuzzy queries open the TUI in a TTY, else print results to stdout |
151
+ | `isa doctor` | Check the install, non-zero exit on failure |
152
+ | `isa update` | Download the pre-built catalog, `--from-release` for the GitHub Release |
153
+ | `isa annotate <file.s>` | Annotate a `.s` file with summaries and latency/CPI, writes `<file>.sa` |
154
+ | `isa man <name>` | Show a manpage, made on demand |
155
+ | `isa install-manpages` | Pre-generate man7 pages so plain `man vpaddd` works |
156
+ | `isa llm query <q>` | Strict lookup to JSON, NDJSON, or Markdown |
157
+ | `isa llm batch` | Resolve many queries from stdin in one invocation |
158
+ | `isa llm list` | Write the FilterSpec or stream matching catalog entries |
159
+ | `isa llm schema` | Print the JSON schema for `llm` payloads |
158
160
 
159
161
  Dev commands
160
162
 
161
- | Command | Description |
162
- | -------------------------------- | ------------------------------------------------------- |
163
- | `isa build` | Rebuild the catalog from upstream, needs `llvm-mca` 18+ |
164
- | `isa export` | Export the site-data JSON for the `simdref-web` repo |
165
- | `isa completion install [SHELL]` | Install shell completion into the user profile |
166
- | `isa completion show [SHELL]` | Print the completion script |
163
+ | Command | Description |
164
+ | -------------------------------- | ----------------------------------------------------------------------------- |
165
+ | `isa build` | Rebuild the catalog from upstream, needs `simdref[ingest]` and `llvm-mca` 18+ |
166
+ | `isa export` | Export the site-data JSON for the `simdref-web` repo |
167
+ | `isa completion install [SHELL]` | Install shell completion into the user profile |
168
+ | `isa completion show [SHELL]` | Print the completion script |
167
169
 
168
170
  ## Data sources
169
171
 
170
- | Source | What | Entries¹ |
171
- | ----------------------- | ------------------------------------------------------- | ------------------ |
172
- | Intel Intrinsics Guide | Signatures, descriptions, ISA, categories | 7,381 intrinsics |
173
- | uops.info | Instructions, operands, latency, throughput, ports | 2,558 instructions |
174
- | Arm ACLE (NEON, SVE) | Intrinsic signatures and descriptions | 10,791 intrinsics |
175
- | Arm AARCHMRS (A64) | Base instruction forms and operand tables | live-only² |
176
- | riscv-rvv-intrinsic-doc | RVV intrinsics with deterministic instruction refs | 74,289 intrinsics |
177
- | RISC-V unified-db | RVV instruction forms, ISA tags, description, operation | 672 instructions |
172
+ | Source | What | Entries¹ |
173
+ | ----------------------- | ------------------------------------------------------- | ------------------- |
174
+ | Intel Intrinsics Guide | Signatures, descriptions, ISA, categories | 7,757 intrinsics |
175
+ | uops.info | Instructions, operands, latency, throughput, ports | 22,113 instructions |
176
+ | Arm ACLE (NEON, SVE) | Intrinsic signatures and descriptions | 13,493 intrinsics |
177
+ | Arm AARCHMRS (A64) | Base instruction forms and operand tables | live-only² |
178
+ | riscv-rvv-intrinsic-doc | RVV intrinsics with deterministic instruction refs | 77,285 intrinsics |
179
+ | RISC-V unified-db | RVV instruction forms, ISA tags, description, operation | 3,666 instructions |
180
+ | Intel Guide perf tables | Per-core latency and throughput | 9,134 rows |
181
+ | Intel Optimization Ref. | Latency and throughput tables (volume 2) | 3,155 rows |
182
+ | InstLatX64 | Measured latency and throughput dumps | 16,235 rows |
183
+ | AMD Software Opt. Guide | Latency workbooks, Zen 1 to Zen 5 | 8,386 rows |
184
+ | Arm Neoverse SWOPT | Instruction tables for 8 CPUs | 10,213 rows |
178
185
 
179
186
  ¹ Counts from the vendored snapshot. See
180
187
  [`docs/coverage/summary.json`](docs/coverage/summary.json) for parity
181
188
  against upstream and [`docs/SOURCES.md`](docs/SOURCES.md) for licenses.
182
189
 
190
+ ### Removal requests
191
+
192
+ Some sources in [`docs/SOURCES.md`](docs/SOURCES.md) do not state a licence. If you own one of these sources and want simdref to stop using it, open an issue at <https://github.com/simd-labs/simdref/issues>. The maintainers then remove the data and the links from the next release.
193
+
183
194
  ² The full AARCHMRS A64 spec needs a live fetch or a tarball under
184
195
  `vendor/arm/`.
185
196
 
@@ -187,7 +198,10 @@ Each perf row carries a `(measured, <core>)` or `(modeled, <core>)` tag.
187
198
 
188
199
  ### Scope
189
200
 
190
- - Performance data is x86-only.
201
+ - Performance data covers x86, AArch64 and RISC-V. Measured rows come from
202
+ uops.info, InstLatX64 and the Intel Optimization Ref. Modeled rows come
203
+ from the Intel Intrinsics Guide, AMD and Arm vendor guides, and the LLVM
204
+ scheduling models.
191
205
  - RISC-V coverage is RVV only, not scalar or privileged ISA.
192
206
 
193
207
  ## Development
@@ -196,7 +210,7 @@ Each perf row carries a `(measured, <core>)` or `(modeled, <core>)` tag.
196
210
  git clone https://github.com/simd-labs/simdref.git
197
211
  cd simdref
198
212
  python3 -m venv .venv
199
- .venv/bin/pip install -e .
213
+ .venv/bin/pip install -e '.[ingest]'
200
214
  .venv/bin/isa build # needs llvm-mca 18+
201
215
  .venv/bin/python -m pytest tests/ -v
202
216
  ```
@@ -33,8 +33,11 @@ isa # open the TUI
33
33
  ```
34
34
 
35
35
  The package installs two equivalent executables, `isa` and `simdref`. The
36
- catalog download does not use `llvm-mca`. Only `isa build` uses
37
- `llvm-mca` 18+ on `PATH`.
36
+ catalog download does not use `llvm-mca`. Python 3.11 or newer is
37
+ necessary. The plain `pip install simdref` covers queries, the LSP and
38
+ `isa update`. `isa build` uses the ingest extra:
39
+ `pip install 'simdref[ingest]'`, or `uv tool install 'simdref[ingest]'`
40
+ with uv. Only `isa build` uses `llvm-mca` 18+ on `PATH`.
38
41
 
39
42
  Pre-release builds live on TestPyPI:
40
43
 
@@ -51,7 +54,6 @@ isa VPADDD # exact instruction -> detailed view
51
54
  isa _mm_add # fuzzy -> ranked search results
52
55
  isa mm add # tokenized query -> intrinsic-biased search
53
56
  isa ADD # mnemonic-like -> instruction-biased search
54
- isa VADDPS 2 # pick variant #2 from the last result list
55
57
  isa # open the TUI
56
58
  ```
57
59
 
@@ -80,13 +82,13 @@ Editor clients, one for each editor:
80
82
  Each client shows a one-line brief at the end of each instruction line and
81
83
  the full manpage on hover, from the local catalog.
82
84
 
83
- The LLM interface writes JSON and NDJSON with exit codes 0 (match), 1 (bad
84
- flag), 2 (no match), 3 (ambiguous):
85
+ The LLM interface writes JSON and NDJSON with exit codes 0 (match), 1 (usage
86
+ error), 2 (no match or parser error), 3 (ambiguous):
85
87
 
86
88
  ```bash
87
- isa llm query _mm_add_ps --source-kind measured
89
+ isa llm query vaddps --source-kind measured
88
90
  echo -e "_mm_add_ps\nVPADDD" | isa llm batch
89
- isa llm list --pattern "*gather*" --isa Intel
91
+ isa llm list --pattern "*gather*"
90
92
  ```
91
93
 
92
94
  See [docs/LLM.md](docs/LLM.md) for the payload shape.
@@ -107,44 +109,53 @@ each instruction line. The output stays valid assembly.
107
109
 
108
110
  Commands
109
111
 
110
- | Command | Description |
111
- | ----------------------- | ------------------------------------------------------------------------- |
112
- | `isa` | Open the TUI |
113
- | `isa <query>` | Open the TUI with the query in a TTY, else print ranked results to stdout |
114
- | `isa doctor` | Check the install, non-zero exit on failure |
115
- | `isa update` | Download the pre-built catalog, `--from-release` for the GitHub Release |
116
- | `isa annotate <file.s>` | Annotate a `.s` file with summaries and latency/CPI, writes `<file>.sa` |
117
- | `isa man <name>` | Show a manpage, made on demand |
118
- | `isa install-manpages` | Pre-generate man7 pages so plain `man vpaddd` works |
119
- | `isa llm query <q>` | Strict lookup to JSON, NDJSON, or Markdown |
120
- | `isa llm batch` | Resolve many queries from stdin in one invocation |
121
- | `isa llm list` | Write the FilterSpec or stream matching catalog entries |
122
- | `isa llm schema` | Print the JSON schema for `llm` payloads |
112
+ | Command | Description |
113
+ | ----------------------- | ----------------------------------------------------------------------- |
114
+ | `isa` | Open the TUI |
115
+ | `isa <query>` | Fuzzy queries open the TUI in a TTY, else print results to stdout |
116
+ | `isa doctor` | Check the install, non-zero exit on failure |
117
+ | `isa update` | Download the pre-built catalog, `--from-release` for the GitHub Release |
118
+ | `isa annotate <file.s>` | Annotate a `.s` file with summaries and latency/CPI, writes `<file>.sa` |
119
+ | `isa man <name>` | Show a manpage, made on demand |
120
+ | `isa install-manpages` | Pre-generate man7 pages so plain `man vpaddd` works |
121
+ | `isa llm query <q>` | Strict lookup to JSON, NDJSON, or Markdown |
122
+ | `isa llm batch` | Resolve many queries from stdin in one invocation |
123
+ | `isa llm list` | Write the FilterSpec or stream matching catalog entries |
124
+ | `isa llm schema` | Print the JSON schema for `llm` payloads |
123
125
 
124
126
  Dev commands
125
127
 
126
- | Command | Description |
127
- | -------------------------------- | ------------------------------------------------------- |
128
- | `isa build` | Rebuild the catalog from upstream, needs `llvm-mca` 18+ |
129
- | `isa export` | Export the site-data JSON for the `simdref-web` repo |
130
- | `isa completion install [SHELL]` | Install shell completion into the user profile |
131
- | `isa completion show [SHELL]` | Print the completion script |
128
+ | Command | Description |
129
+ | -------------------------------- | ----------------------------------------------------------------------------- |
130
+ | `isa build` | Rebuild the catalog from upstream, needs `simdref[ingest]` and `llvm-mca` 18+ |
131
+ | `isa export` | Export the site-data JSON for the `simdref-web` repo |
132
+ | `isa completion install [SHELL]` | Install shell completion into the user profile |
133
+ | `isa completion show [SHELL]` | Print the completion script |
132
134
 
133
135
  ## Data sources
134
136
 
135
- | Source | What | Entries¹ |
136
- | ----------------------- | ------------------------------------------------------- | ------------------ |
137
- | Intel Intrinsics Guide | Signatures, descriptions, ISA, categories | 7,381 intrinsics |
138
- | uops.info | Instructions, operands, latency, throughput, ports | 2,558 instructions |
139
- | Arm ACLE (NEON, SVE) | Intrinsic signatures and descriptions | 10,791 intrinsics |
140
- | Arm AARCHMRS (A64) | Base instruction forms and operand tables | live-only² |
141
- | riscv-rvv-intrinsic-doc | RVV intrinsics with deterministic instruction refs | 74,289 intrinsics |
142
- | RISC-V unified-db | RVV instruction forms, ISA tags, description, operation | 672 instructions |
137
+ | Source | What | Entries¹ |
138
+ | ----------------------- | ------------------------------------------------------- | ------------------- |
139
+ | Intel Intrinsics Guide | Signatures, descriptions, ISA, categories | 7,757 intrinsics |
140
+ | uops.info | Instructions, operands, latency, throughput, ports | 22,113 instructions |
141
+ | Arm ACLE (NEON, SVE) | Intrinsic signatures and descriptions | 13,493 intrinsics |
142
+ | Arm AARCHMRS (A64) | Base instruction forms and operand tables | live-only² |
143
+ | riscv-rvv-intrinsic-doc | RVV intrinsics with deterministic instruction refs | 77,285 intrinsics |
144
+ | RISC-V unified-db | RVV instruction forms, ISA tags, description, operation | 3,666 instructions |
145
+ | Intel Guide perf tables | Per-core latency and throughput | 9,134 rows |
146
+ | Intel Optimization Ref. | Latency and throughput tables (volume 2) | 3,155 rows |
147
+ | InstLatX64 | Measured latency and throughput dumps | 16,235 rows |
148
+ | AMD Software Opt. Guide | Latency workbooks, Zen 1 to Zen 5 | 8,386 rows |
149
+ | Arm Neoverse SWOPT | Instruction tables for 8 CPUs | 10,213 rows |
143
150
 
144
151
  ¹ Counts from the vendored snapshot. See
145
152
  [`docs/coverage/summary.json`](docs/coverage/summary.json) for parity
146
153
  against upstream and [`docs/SOURCES.md`](docs/SOURCES.md) for licenses.
147
154
 
155
+ ### Removal requests
156
+
157
+ Some sources in [`docs/SOURCES.md`](docs/SOURCES.md) do not state a licence. If you own one of these sources and want simdref to stop using it, open an issue at <https://github.com/simd-labs/simdref/issues>. The maintainers then remove the data and the links from the next release.
158
+
148
159
  ² The full AARCHMRS A64 spec needs a live fetch or a tarball under
149
160
  `vendor/arm/`.
150
161
 
@@ -152,7 +163,10 @@ Each perf row carries a `(measured, <core>)` or `(modeled, <core>)` tag.
152
163
 
153
164
  ### Scope
154
165
 
155
- - Performance data is x86-only.
166
+ - Performance data covers x86, AArch64 and RISC-V. Measured rows come from
167
+ uops.info, InstLatX64 and the Intel Optimization Ref. Modeled rows come
168
+ from the Intel Intrinsics Guide, AMD and Arm vendor guides, and the LLVM
169
+ scheduling models.
156
170
  - RISC-V coverage is RVV only, not scalar or privileged ISA.
157
171
 
158
172
  ## Development
@@ -161,7 +175,7 @@ Each perf row carries a `(measured, <core>)` or `(modeled, <core>)` tag.
161
175
  git clone https://github.com/simd-labs/simdref.git
162
176
  cd simdref
163
177
  python3 -m venv .venv
164
- .venv/bin/pip install -e .
178
+ .venv/bin/pip install -e '.[ingest]'
165
179
  .venv/bin/isa build # needs llvm-mca 18+
166
180
  .venv/bin/python -m pytest tests/ -v
167
181
  ```
@@ -4,10 +4,10 @@ build-backend = "setuptools.build_meta"
4
4
 
5
5
  [project]
6
6
  name = "simdref"
7
- version = "0.0.15"
7
+ version = "0.0.16"
8
8
  description = "Searchable SIMD intrinsic and instruction reference with CLI, manpages, TUI, and LSP."
9
9
  readme = "README.md"
10
- requires-python = ">=3.10"
10
+ requires-python = ">=3.11"
11
11
  license = {text = "GPL-3.0-or-later"}
12
12
  authors = [
13
13
  {name = "Marco"}
@@ -19,7 +19,6 @@ classifiers = [
19
19
  "License :: OSI Approved :: GNU General Public License v3 or later (GPLv3+)",
20
20
  "Operating System :: OS Independent",
21
21
  "Programming Language :: Python :: 3",
22
- "Programming Language :: Python :: 3.10",
23
22
  "Programming Language :: Python :: 3.11",
24
23
  "Programming Language :: Python :: 3.12",
25
24
  "Programming Language :: Python :: 3.13",
@@ -27,27 +26,36 @@ classifiers = [
27
26
  "Topic :: Software Development :: Documentation",
28
27
  "Topic :: Software Development :: Libraries :: Python Modules",
29
28
  ]
30
- # `requires-python` tracks the non-EOL CPython range; 3.10 goes EOL 2026-10-31.
31
- # Lower dependency bound is the version CI resolves and tests; anything older is
32
- # an untested compatibility claim. Upper bound is the next major (next minor for
33
- # 0.x, where that is the compatibility unit). msgpack floors above its own
34
- # advisory: 1.2.0 and earlier carry GHSA-6v7p-g79w-8964.
29
+ # `requires-python` tracks the non-EOL CPython range. Lower dependency
30
+ # bound is the version CI resolves and tests; anything older is an untested
31
+ # compatibility claim. Upper bound is the next major (next minor for 0.x,
32
+ # where that is the compatibility unit). msgpack floors at 1.2.4 for
33
+ # GHSA-j8c6-9vc5-hj6x; 1.2.0 and earlier also carry GHSA-6v7p-g79w-8964.
35
34
  dependencies = [
36
- "click>=8.5,<9",
37
- "httpx>=0.28,<1",
38
- "msgpack>=1.2.1,<2",
39
- "pdfplumber>=0.11.10,<1",
40
- "PyMuPDF>=1.28,<2",
35
+ "click>=8.5.0,<9",
36
+ "httpx>=0.28.1,<1",
37
+ "msgpack>=1.2.4,<2",
41
38
  "PyYAML>=6.0.3,<7",
42
- "rapidfuzz>=3.14,<4",
43
- "rich>=15,<16",
39
+ "rapidfuzz>=3.14.6,<4",
40
+ "rich>=15.0.0,<16",
44
41
  # Pinned to the LLVM the catalog build used. Wheels exist only for
45
42
  # manylinux x86_64 aarch64, macOS arm64 x86_64 and win_amd64, so the
46
43
  # marker keeps the dependency off every other platform (musl included),
47
44
  # where pip must see no candidate instead of failing to resolve.
48
45
  'simdref-llvm-mc==23.1.4; (sys_platform == "linux" and (platform_machine == "x86_64" or platform_machine == "aarch64")) or (sys_platform == "darwin" and (platform_machine == "arm64" or platform_machine == "x86_64")) or (sys_platform == "win32" and platform_machine == "AMD64")',
49
- "textual>=8.2,<9",
50
- "typer>=0.27,<1",
46
+ "textual>=8.2.8,<9",
47
+ "typer>=0.27.3,<1",
48
+ ]
49
+
50
+ [project.optional-dependencies]
51
+ # PDF ingest for `simdref build` only. pdfplumber parses the Intel SDM;
52
+ # PyMuPDF is its fast path. Both stay out of the plain install, which then
53
+ # works on PyPy and needs no C toolchain.
54
+ ingest = [
55
+ "pdfplumber>=0.11.10,<1",
56
+ # PyMuPDF (guarded import, pdfplumber falls back) pulls onnxruntime,
57
+ # which ships no PyPy wheels: CPython only (issue #61).
58
+ "PyMuPDF>=2.1,<3; platform_python_implementation == 'CPython'",
51
59
  ]
52
60
 
53
61
  [project.scripts]
@@ -63,4 +71,4 @@ where = ["src"]
63
71
 
64
72
  [tool.ruff]
65
73
  line-length = 100
66
- target-version = "py310"
74
+ target-version = "py311"