simdref 0.0.12__tar.gz → 0.0.13__tar.gz

{simdref-0.0.12/src/simdref.egg-info → simdref-0.0.13}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: simdref
-Version: 0.0.12
+Version: 0.0.13
 Summary: Searchable SIMD intrinsic and instruction reference with CLI, manpages, TUI, and LSP.
 Author: Marco
 License: GPL-3.0-or-later
@@ -67,7 +67,7 @@ isa            # open the TUI
 ```
 
 The package installs two equivalent executables, `isa` and `simdref`. The
-catalog download does not need `llvm-mca`. Only `isa build` needs
+catalog download does not use `llvm-mca`. Only `isa build` uses
 `llvm-mca` 18+ on `PATH`.
 
 Pre-release builds live on TestPyPI:
@@ -98,7 +98,7 @@ reads the JSON site data this repo exports:
 isa export --out-dir ./site-data
 ```
 
-The LSP server speaks JSON-RPC over stdio:
+The LSP server speaks JSON-RPC on stdio:
 
 ```bash
 simdref-lsp
@@ -114,7 +114,7 @@ Editor clients, one for each editor:
 Each client shows a one-line brief at the end of each instruction line and
 the full manpage on hover, from the local catalog.
 
-The LLM interface emits JSON and NDJSON with exit codes 0 (match), 1 (bad
+The LLM interface writes JSON and NDJSON with exit codes 0 (match), 1 (bad
 flag), 2 (no match), 3 (ambiguous):
 
 ```bash
@@ -148,11 +148,11 @@ Commands
 | `isa doctor`            | Check the install, non-zero exit on failure                               |
 | `isa update`            | Download the pre-built catalog, `--from-release` for the GitHub Release   |
 | `isa annotate <file.s>` | Annotate a `.s` file with summaries and latency/CPI, writes `<file>.sa`   |
-| `isa man <name>`        | Show a manpage, rendered on demand                                        |
+| `isa man <name>`        | Show a manpage, made on demand                                            |
 | `isa install-manpages`  | Pre-generate man7 pages so plain `man vpaddd` works                       |
 | `isa llm query <q>`     | Strict lookup to JSON, NDJSON, or Markdown                                |
 | `isa llm batch`         | Resolve many queries from stdin in one invocation                         |
-| `isa llm list`          | Emit the FilterSpec or stream matching catalog entries                    |
+| `isa llm list`          | Write the FilterSpec or stream matching catalog entries                   |
 | `isa llm schema`        | Print the JSON schema for `llm` payloads                                  |
 
 Dev commands

{simdref-0.0.12 → simdref-0.0.13}/README.md

@@ -33,7 +33,7 @@ isa            # open the TUI
 ```
 
 The package installs two equivalent executables, `isa` and `simdref`. The
-catalog download does not need `llvm-mca`. Only `isa build` needs
+catalog download does not use `llvm-mca`. Only `isa build` uses
 `llvm-mca` 18+ on `PATH`.
 
 Pre-release builds live on TestPyPI:
@@ -64,7 +64,7 @@ reads the JSON site data this repo exports:
 isa export --out-dir ./site-data
 ```
 
-The LSP server speaks JSON-RPC over stdio:
+The LSP server speaks JSON-RPC on stdio:
 
 ```bash
 simdref-lsp
@@ -80,7 +80,7 @@ Editor clients, one for each editor:
 Each client shows a one-line brief at the end of each instruction line and
 the full manpage on hover, from the local catalog.
 
-The LLM interface emits JSON and NDJSON with exit codes 0 (match), 1 (bad
+The LLM interface writes JSON and NDJSON with exit codes 0 (match), 1 (bad
 flag), 2 (no match), 3 (ambiguous):
 
 ```bash
@@ -114,11 +114,11 @@ Commands
 | `isa doctor`            | Check the install, non-zero exit on failure                               |
 | `isa update`            | Download the pre-built catalog, `--from-release` for the GitHub Release   |
 | `isa annotate <file.s>` | Annotate a `.s` file with summaries and latency/CPI, writes `<file>.sa`   |
-| `isa man <name>`        | Show a manpage, rendered on demand                                        |
+| `isa man <name>`        | Show a manpage, made on demand                                            |
 | `isa install-manpages`  | Pre-generate man7 pages so plain `man vpaddd` works                       |
 | `isa llm query <q>`     | Strict lookup to JSON, NDJSON, or Markdown                                |
 | `isa llm batch`         | Resolve many queries from stdin in one invocation                         |
-| `isa llm list`          | Emit the FilterSpec or stream matching catalog entries                    |
+| `isa llm list`          | Write the FilterSpec or stream matching catalog entries                   |
 | `isa llm schema`        | Print the JSON schema for `llm` payloads                                  |
 
 Dev commands

{simdref-0.0.12 → simdref-0.0.13}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "simdref"
-version = "0.0.12"
+version = "0.0.13"
 description = "Searchable SIMD intrinsic and instruction reference with CLI, manpages, TUI, and LSP."
 readme = "README.md"
 requires-python = ">=3.10"

{simdref-0.0.12 → simdref-0.0.13}/src/simdref/cli.py

@@ -659,9 +659,7 @@ def _maybe_auto_update_for_version_change() -> None:
             "[bold yellow]warning:[/bold yellow] auto-update failed; continuing with the existing catalog. "
             "Some features may not work correctly until `simdref update` succeeds.",
         )
-        # Stamp anyway so we don't retry on every invocation; the user has
-        # been warned and can re-run `simdref update` once back online.
-        write_installed_version_stamp(__version__)
+        # Keep the old stamp so the next invocation retries the download.
 
 
 def _catalog_meta(catalog) -> dict:

{simdref-0.0.12 → simdref-0.0.13}/src/simdref/ingest_catalog.py

@@ -85,12 +85,13 @@ def _canonical_instruction_key(name: str, form: str) -> str:
 
 
 @lru_cache(maxsize=128)
-def _normalize_operand_xtype(value: str) -> str:
+def _normalize_operand_xtype(value: str, width: str = "") -> str:
     xtype = value.strip()
     if not xtype:
         return xtype
     if xtype == "int":
-        return "i32"
+        # uops.info marks every scalar integer operand xtype=int; the width holds the size
+        return f"i{width}" if width in {"8", "16", "32", "64"} else "i32"
     match = re.fullmatch(r"\d+([iu]\d+)", xtype)
     if match:
         return match.group(1)
@@ -1020,7 +1021,9 @@ def parse_uops_xml(source: str | Path) -> list[InstructionRecord]:
         arch_details: dict[str, dict[str, Any]] = {}
         for child in node:
             if child.tag == "operand":
-                xtype = _normalize_operand_xtype(child.attrib.get("xtype", "").strip())
+                xtype = _normalize_operand_xtype(
+                    child.attrib.get("xtype", "").strip(), child.attrib.get("width", "").strip()
+                )
                 operand_payload = {
                     key: (
                         _intern_small(value.strip())

{simdref-0.0.12 → simdref-0.0.13}/src/simdref/lsp.py

@@ -113,31 +113,286 @@ def _line_prefix(text: str, line: int, character: int) -> str:
     return match.group(0) if match else ""
 
 
-def _match_form(matches, operand_count: int | None = None, operand_text: str = ""):
-    """Pick the same form the line names: exact operand count, then width, then smallest."""
+_ATT_SUFFIX_WIDTH = {"b": 8, "w": 16, "l": 32, "q": 64}
+_ACCUMULATOR = {"al": "r8", "ax": "r16", "eax": "r32", "rax": "r64"}
+# x86 numbers only r8-r15; r0-r7 are ARM registers.
+_GPR_PATTERNS = (
+    (64, r"r(ax|bx|cx|dx|si|di|bp|sp|8|9|1[0-5])"),
+    (32, r"e(ax|bx|cx|dx|si|di|bp|sp)|r(8|9|1[0-5])d"),
+    (16, r"(ax|bx|cx|dx|si|di|bp|sp)|r(8|9|1[0-5])w"),
+    (8, r"[a-d][lh]|(si|di|bp|sp)l|r(8|9|1[0-5])b"),
+)
+_STRING_OP_RE = re.compile(r"(movs|cmps|scas|lods|stos|ins|outs)[bwdq]", re.IGNORECASE)
+_X86_VECTOR_WIDTHS = {"xmm": "v128", "ymm": "v256", "zmm": "v512"}
+_X86_VECTOR_RE = re.compile(r"(?:[xyz]mm(?:[12]?[0-9]|3[01])|k[0-7]|mm[0-7])\Z")
+_A64_ARRANGEMENT_RE = re.compile(r"[bdhqsvz](?:[0-9]|[12][0-9]|3[01])\.[0-9]*[bhsdq]\Z")
+_A64_SCALAR_RE = re.compile(r"(?:x(?:[0-9]|[12][0-9]|30)|w(?:[0-9]|[12][0-9]|30)|xzr|wzr)\Z")
+_A64_SCALAR_FP_RE = re.compile(r"[bhsdq](?:[0-9]|[12][0-9]|3[01])\Z")
+# A bare v register is a vector spelling ARM and RISC-V share.
+_A64_VECTOR_BARE_RE = re.compile(r"v(?:[0-9]|[12][0-9]|3[01])\Z")
+_ARM32_SCALAR_RE = re.compile(r"(?:r(?:[0-9]|1[0-5])|ip|pc)\Z")
+# ARM has "sp" and "fp"; RISC-V shares both spellings and adds these scalar aliases.
+_RISCV_SCALARS = frozenset(
+    {f"a{i}" for i in range(8)}
+    | {f"s{i}" for i in range(12)}
+    | {f"t{i}" for i in range(7)}
+    | {"zero", "ra", "gp", "tp"}
+)
+
+
+def _lookup_mnemonic(conn, mnemonic: str, arch: frozenset = frozenset()):
+    """Return (forms, width). The exact mnemonic wins, else drop an AT&T size suffix (addq -> add).
+
+    The suffix strip runs on an x86 or undecided line only: "addw" on a RISC-V
+    or ARM32 line must not land on x86 "add". Rows of other architectures stay
+    in the result; _match_form filters them by the line's candidates.
+    """
+    forms = load_instructions_by_mnemonic_from_db(conn, mnemonic)
+    width = _ATT_SUFFIX_WIDTH.get(mnemonic[-1:].casefold())
+    # movsbl is a sign-extend, not the string op movsb.
+    if forms or not width or _STRING_OP_RE.fullmatch(mnemonic[:-1]):
+        return forms, None
+    if arch and "x86" not in arch:
+        return [], None
+    stripped = load_instructions_by_mnemonic_from_db(conn, mnemonic[:-1])
+    return [form for form in stripped if form.architecture == "x86"], width
+
+
+def _classify_line(operands: str, intel: bool) -> tuple[frozenset, list[str | None], bool]:
+    """One pass over the line: (candidate architecture buckets, one class per operand, reverse).
+
+    A strong vote (a %- or Intel-style register, an x86 vector, an AArch64
+    arrangement, an AArch64/ARM32/RISC-V-only scalar) names one bucket. A
+    spelling two architectures share ("sp", "fp", s0-s11, a bare v) votes for
+    every bucket it can mean and only counts when no strong vote fired. Empty
+    candidates mean undecided; callers then keep today's unfiltered behaviour.
+    "reverse" is True when the line's operand order flips into key order
+    (AT&T x86). A register of a non-candidate architecture reads as a symbol.
+    """
+    parts = re.split(r",(?![^(\[{]*[)\]}])", operands)
+    strong, weak = set(), set()
+    for raw in parts:
+        op = raw.strip()
+        name = op.lstrip("*").lstrip("%").casefold()
+        prefixed = op.lstrip("*").startswith("%")
+        reg = next((w for w, pattern in _GPR_PATTERNS if re.fullmatch(pattern, name)), None)
+        if op.startswith("$"):
+            strong.add("x86")
+        elif _X86_VECTOR_RE.fullmatch(name):
+            strong.add("x86")
+        elif prefixed and reg:
+            strong.add("x86")
+        elif not name or "(" in op or "[" in op or "{" in op:
+            continue
+        elif _A64_ARRANGEMENT_RE.fullmatch(name) or _A64_SCALAR_RE.fullmatch(name) or name == "wsp":
+            strong.add("arm")
+        elif _ARM32_SCALAR_RE.fullmatch(name):
+            strong.add("arm")
+        elif _A64_SCALAR_FP_RE.fullmatch(name):
+            # s0-s11 are also RISC-V saved registers: a weak vote there, and
+            # the mnemonic's catalog rows arbitrate between arm and riscv.
+            if name in _RISCV_SCALARS:
+                weak.update(("arm", "riscv"))
+            else:
+                strong.add("arm")
+        elif name in _RISCV_SCALARS:
+            strong.add("riscv")
+        elif _A64_VECTOR_BARE_RE.fullmatch(name):
+            weak.update(("arm", "riscv"))
+        elif name in ("sp", "fp"):
+            weak.update(("arm", "riscv"))
+        elif name == "lr":
+            weak.add("arm")
+    arch = frozenset({"x86"}) if intel or "x86" in strong else frozenset(strong or weak)
+    classes = [_operand_class(op.strip(), intel, arch) for op in parts]
+    reverse = not intel and ("x86" in arch or not arch)
+    return arch, classes, reverse
+
+
+def _operand_class(op: str, intel: bool, arch: frozenset) -> str | None:
+    """Classify one operand on a line whose candidates are arch, or None.
+
+    Classes: r8..r64, v128/v256/v512/k/mm, av (AArch64 vector with an
+    arrangement), x/w/xzr/wzr/sp/wsp (AArch64 scalars; fp and lr read as x),
+    b/h/s/d/q (AArch64 scalar FP by width), ar (ARM32), rv (RISC-V), and
+    i, lit0/lit1, m, rel. A bare symbol is a memory reference in AT&T and a
+    rel target in Intel syntax.
+    """
+    if not op:
+        return None
+    name = op.lstrip("*").lstrip("%").casefold()
+    if re.fullmatch(r"\$?0+", op):
+        return "lit0"
+    if re.fullmatch(r"\$?0*1", op):
+        return "lit1"
+    if op.startswith("$") or re.fullmatch(r"-?(0x[0-9a-f]+|\d+)", op, re.IGNORECASE):
+        return "i"
+    if "{1to" in op:
+        return "mbc"
+    if "{" in op:
+        op = re.sub(r"\{[^}]*\}", "", op).strip()
+        name = op.lstrip("*").lstrip("%").casefold()
+    if "(" in op or "[" in op:
+        return "m"
+    reg = next((w for w, pattern in _GPR_PATTERNS if re.fullmatch(pattern, name)), None)
+    # In AT&T a bare "sp" is the ARM stack pointer or a symbol, never the r16.
+    if reg and (intel or op.lstrip("*").startswith("%") or name not in ("sp", "bp", "si", "di")):
+        if intel or arch.isdisjoint({"arm", "riscv"}):
+            return f"r{reg}"
+    if _X86_VECTOR_RE.fullmatch(name):
+        if name[0] == "k":
+            return "k"
+        if name[0] == "m":
+            return "mm"
+        return _X86_VECTOR_WIDTHS[name[:3]]
+    if not intel and op.startswith("*"):
+        return "m"
+    if "arm" in arch:
+        if _A64_ARRANGEMENT_RE.fullmatch(name) or _A64_VECTOR_BARE_RE.fullmatch(name):
+            return "av"
+        if _A64_SCALAR_FP_RE.fullmatch(name):
+            return name[0]
+        if _A64_SCALAR_RE.fullmatch(name):
+            return {"xzr": "xzr", "wzr": "wzr"}.get(name, name[0])
+        if name in ("sp", "wsp", "fp", "lr"):
+            return {"sp": "sp", "wsp": "wsp"}.get(name, "x")
+        if _ARM32_SCALAR_RE.fullmatch(name):
+            return "ar"
+    if "riscv" in arch and (name in _RISCV_SCALARS or _A64_VECTOR_BARE_RE.fullmatch(name)):
+        return "rv"
+    if "x86" in arch or not arch:
+        return "rel" if intel else "m"
+    return None
+
+
+_IMMEDIATE_ACCEPT = frozenset({"i", "lit0", "lit1"})
+_LITERAL_ACCEPT = {frozenset({"lit0"}), frozenset({"lit1"})}
+_CLASS_KIND = dict(
+    [(c, "register") for c in ("r8", "r16", "r32", "r64")]
+    + [(c, "vector") for c in ("v128", "v256", "v512", "k", "mm", "av", "dfp", "pred")]
+    + [(c, "memory") for c in ("m", "moffs", "mbc")]
+    + [(c, "immediate") for c in ("i", "lit0", "lit1")]
+    + [
+        (c, "scalar")
+        for c in ("x", "w", "xzr", "wzr", "sp", "wsp", "b", "h", "s", "d", "q", "ar", "rv")
+    ]
+    + [("rel", "rel")]
+)
+
+
+def _form_accept(op: str) -> frozenset:
+    """The line classes a catalog-key operand accepts, as one frozenset.
+
+    An immediate-width key (i8..i64) takes every immediate class. A literal 0/1
+    takes only its own value: a fixed-1 shift is not the line's "2". An AArch64
+    placeholder maps to the register family it encodes (<XNSP> = x or sp).
+    """
+    o = op.casefold()
+    if o in ("0", "1"):
+        return frozenset({"lit" + o})
+    if re.fullmatch(r"i\d+", o):
+        return _IMMEDIATE_ACCEPT
+    if o in _ACCUMULATOR or o == "cl":
+        return frozenset({_ACCUMULATOR.get(o, "r8")})
+    m = re.fullmatch(r"r(8|16|32|64)[hl]?", o)
+    if m:
+        return frozenset({"r" + m.group(1)})
+    if o in _X86_VECTOR_WIDTHS or o in ("k", "mm"):
+        return frozenset({_X86_VECTOR_WIDTHS.get(o, o)})
+    if re.fullmatch(r"m\d+_\d+to\d+", o):
+        return frozenset({"mbc"})
+    if re.fullmatch(r"m\d+", o):
+        return frozenset({"m"})
+    if re.fullmatch(r"moffs\d+", o):
+        return frozenset({"moffs"})
+    if re.fullmatch(r"rel\d*", o):
+        return frozenset({"rel"})
+    if op.startswith("["):
+        return frozenset({"m"})
+    name = re.sub(r"(#\d+)+$", "", op.upper())
+    if "<HASH>" in name:
+        return _IMMEDIATE_ACCEPT
+    if re.match(r"V\d+<|^[ZV]\d+\.|^\{|^<ZA>", name):
+        return frozenset({"av"})
+    # Numbered scalar FP placeholders: D0 or S1 style numbers, <BT> or <QT1> style aliases.
+    if re.fullmatch(r"[BHSDQ]\d+", name):
+        return frozenset({name[0].lower()})
+    if re.fullmatch(r"<[BHSDQ]T\d*>", name):
+        return frozenset({name[1].lower()})
+    if re.match(r"^D<|^<FPFAR_DT>$", name):
+        return frozenset({"dfp"})
+    if re.match(r"^P\d", name):
+        return frozenset({"pred"})
+    if "WORX" in name or "R_OPTION" in name:
+        return frozenset({"w", "x"})
+    if "WZR" in name:
+        return frozenset({"w", "wzr"})
+    if "XZR" in name:
+        return frozenset({"x", "xzr"})
+    if "WSP" in name:
+        return frozenset({"w", "wsp"})
+    if "SP" in name:
+        return frozenset({"x", "sp"})
+    return frozenset()
+
+
+def _match_form(
+    matches,
+    operand_count: int | None,
+    line: tuple,
+    suffix_bits: int | None,
+):
+    """Pick the form the line names, under one total order.
+
+    line is _classify_line's (arch candidates, ordered classes, reverse). Rows
+    of a non-candidate architecture drop out before ranking; an undecided line
+    keeps every row. Rank: class-set score (accepted +1 / same kind 0 / else
+    -1, a literal scores only on its own value), position score, iN over a
+    literal 0/1, match with the AT&T suffix width, fewer operands, key name.
+    The no-same-count fallback uses the same key.
+    """
+    arch, classes, reverse = line
+    if arch:
+        matches = [m for m in matches if m.architecture in arch]
     if operand_count is None:
         return matches[0] if matches else None
-    # ponytail: a line has no architecture, so take the first form with the same operand count.
-    # The fallback takes the first form with fewest operands, never a form with more
-    # operands than the line: a zero-operand "movsd" must not get the MOVSD_XMM hint.
-    same_count = [m for m in matches if len(_operands_of_key(m.key)) == operand_count]
-    if not same_count:
-        return min(matches, key=lambda m: len(_operands_of_key(m.key)), default=None)
-    # Score candidates by how many operands agree with the register width the
-    # line names ("ymm0" vs "YMM, YMM, M128"). Skip the tiebreak on a tie.
-    tokens = re.findall(r"\b(zmm|ymm|xmm|m512|m256|m128|m64|m32)\d*\b", operand_text.casefold())
-    if tokens:
-        width = tokens[0].rstrip("0123456789")
-        if width.startswith(("x", "y", "z")):
-
-            def _score(item):
-                operands = [op.casefold().rstrip("0123456789") for op in _operands_of_key(item.key)]
-                return sum(1 for op in operands if op == width)
-
-            scored = sorted(same_count, key=lambda m: (-_score(m), m.key))
-            if _score(scored[0]) > _score(scored[-1]):
-                return scored[0]
-    return same_count[0]
+    same = [m for m in matches if len(_operands_of_key(m.key)) == operand_count]
+    pool = same or matches
+    if not pool:
+        return None
+    ordered = list(reversed(classes)) if reverse else classes
+    line_set = {c for c in classes if c}
+    line_kinds = {_CLASS_KIND[c] for c in line_set if c in _CLASS_KIND}
+
+    def _rank(form):
+        accepts = [_form_accept(op) for op in _operands_of_key(form.key)]
+        set_score = position = in_over_lit = width = 0
+        for acc in accepts:
+            if acc in _LITERAL_ACCEPT:
+                set_score += 0 if acc & line_set else -1
+            elif acc & line_set:
+                set_score += 1
+            elif {_CLASS_KIND[a] for a in acc} & line_kinds:
+                pass
+            else:
+                set_score -= 1
+            if any(
+                c in line_set and int(c[1:]) == suffix_bits
+                for c in acc
+                if re.fullmatch(r"[rv]\d+", c)
+            ):
+                width += 1
+        for cls, acc in zip(ordered, accepts):
+            if cls in acc:
+                position += 1
+            if cls in ("i", "lit0", "lit1"):
+                if acc == _IMMEDIATE_ACCEPT:
+                    in_over_lit += 1
+                elif acc in _LITERAL_ACCEPT:
+                    in_over_lit -= 1
+        return (-set_score, -position, -in_over_lit, -width, len(accepts), form.key)
+
+    return min(pool, key=_rank)
 
 
 def _hover_markdown(
@@ -146,6 +401,7 @@ def _hover_markdown(
     allow_instruction: bool = True,
     operand_count: int | None = None,
     operand_text: str = "",
+    intel: bool = False,
 ) -> str | None:
     intrinsic = load_intrinsic_from_db(conn, word)
     if intrinsic is not None:
@@ -186,12 +442,22 @@ def _hover_markdown(
 
     if not allow_instruction:
         return None
+    line = _classify_line(operand_text, intel)
     instruction = load_instruction_from_db(conn, word)
+    # An exact name can name a row with a different operand count (a bare
+    # "movsd" is the string move), or a row from the wrong architecture
+    # (a bare "nop" picks AArch64 NOP over x86 in an Intel file).
+    # In both cases, fall back to _match_form so hover and hint agree.
+    if instruction is not None:
+        if line[0] and instruction.architecture not in line[0]:
+            instruction = None
+        elif operand_count is not None and len(_operands_of_key(instruction.key)) != operand_count:
+            instruction = None
     if instruction is None:
-        matches = load_instructions_by_mnemonic_from_db(conn, word)
         # Match the form on the source line like _hint_label does, so
         # "vaddps ymm0, ymm1, ymm2" gets the YMM form, not the first row.
-        instruction = _match_form(matches, operand_count, operand_text)
+        matches, width = _lookup_mnemonic(conn, word, line[0])
+        instruction = _match_form(matches, operand_count, line, width)
     if instruction is not None:
         body = instruction_markdown(instruction, conn=conn)
         links = [f"Full page: {web_deep_link('instruction', instruction.key)}"]
@@ -304,7 +570,7 @@ def _operand_count(operands: str) -> int:
 
 
 def _mnemonic_from_asm_line(line: str, semicolon_is_comment: bool = False):
-    """Return (mnemonic, operand_count) for an asm line, or None."""
+    """Return (mnemonic, operand_count, operands) for an asm line, or None."""
     line = ASM_COMMENT_RE.sub("", line)
     if semicolon_is_comment:
         line = ASM_SEMICOLON_COMMENT_RE.sub("", line)
@@ -319,7 +585,8 @@ def _mnemonic_from_asm_line(line: str, semicolon_is_comment: bool = False):
         parts = line.split(None, 1)
     if not MNEMONIC_RE.match(parts[0]):
         return None
-    return parts[0], _operand_count(parts[1] if len(parts) > 1 else "")
+    operands = parts[1] if len(parts) > 1 else ""
+    return parts[0], _operand_count(operands), operands
 
 
 def _operands_of_key(key: str) -> list[str]:
@@ -333,24 +600,32 @@ def _cut_label(text: str) -> str:
 
 
 @functools.lru_cache(maxsize=1024)
-def _mnemonic_matches(db_path: str, mnemonic: str) -> tuple:
+def _mnemonic_matches(db_path: str, mnemonic: str, arch: frozenset = frozenset()) -> tuple:
     # The inlay-hint loop asks the same mnemonics for every line, so query once
-    # per (catalog, mnemonic) and reuse. The key carries the path, not the
-    # connection, so a reloaded catalog at the same path would keep stale rows;
-    # clear the cache if catalog reload lands.
+    # per (catalog, mnemonic, arch candidates) and reuse. The key carries the
+    # path, not the connection, so a reloaded catalog at the same path would
+    # keep stale rows; clear the cache if catalog reload lands.
     conn = open_db(path=Path(db_path))
     try:
-        return tuple(load_instructions_by_mnemonic_from_db(conn, mnemonic))
+        forms, width = _lookup_mnemonic(conn, mnemonic, arch)
+        return tuple(forms), width
     finally:
         conn.close()
 
 
-def _hint_label(db_path: str, mnemonic: str, operand_count: int) -> str | None:
-    matches = _mnemonic_matches(db_path, mnemonic)
+def _hint_label(
+    db_path: str,
+    mnemonic: str,
+    operand_count: int,
+    operands: str = "",
+    intel: bool = False,
+) -> str | None:
+    line = _classify_line(operands, intel)
+    matches, width = _mnemonic_matches(db_path, mnemonic, line[0])
     if not matches:
         return None
-    chosen = _match_form(matches, operand_count)
-    return _cut_label(chosen.summary or "")
+    chosen = _match_form(matches, operand_count, line, width)
+    return _cut_label(chosen.summary or "") if chosen else None
 
 
 def _inlay_hints(conn, text: str, language_id: str, uri: str, start: int, end: int) -> list[dict]:
@@ -371,7 +646,7 @@ def _inlay_hints(conn, text: str, language_id: str, uri: str, start: int, end: i
         if not start <= line <= end:
             continue
         parsed = _mnemonic_from_asm_line(segment, semicolon_is_comment)
-        label = _hint_label(db_path, *parsed) if parsed else None
+        label = _hint_label(db_path, *parsed, intel=semicolon_is_comment) if parsed else None
         if label is not None:
             hints.setdefault(line, []).append(label)
     return [
@@ -454,7 +729,8 @@ def main() -> int:
             line, character = params["position"]["line"], params["position"]["character"]
             word = _word_at(text, line, character)
             # In C/C++ only the asm strings hold instructions; intrinsics hover everywhere.
-            is_c_doc = _is_c_doc(session.languages.get(uri, ""), uri)
+            language_id = session.languages.get(uri, "")
+            is_c_doc = _is_c_doc(language_id, uri)
             allow_instruction = not is_c_doc or (_in_asm_string(text, line, character))
             operand_count = None
             operand_text = ""
@@ -462,16 +738,15 @@ def main() -> int:
                 offset = sum(len(item) + 1 for item in text.split("\n")[:line]) + _code_point_index(
                     text.split("\n")[line], character
                 )
-                language_id = session.languages.get(uri, "")
                 segment = _asm_line_at(text, language_id, uri, offset)
                 if segment:
-                    operand_text = segment
                     # The C-escape pair "\t" starts a segment in asm("...\n\t...").
                     # Strip the backslash so the mnemonic survives.
                     parsed = _mnemonic_from_asm_line(
                         segment.lstrip("\\"), _semicolon_is_comment(language_id, uri)
                     )
                     if parsed:
+                        operand_text = parsed[2]
                         if parsed[0].casefold() == word.casefold():
                             operand_count = parsed[1]
                         elif word.casefold().endswith(parsed[0].casefold()):
@@ -487,6 +762,7 @@ def main() -> int:
                     allow_instruction,
                     operand_count=operand_count,
                     operand_text=operand_text,
+                    intel=_semicolon_is_comment(language_id, uri),
                 )
                 if conn and word
                 else None

{simdref-0.0.12 → simdref-0.0.13}/src/simdref/tui.py

@@ -150,6 +150,12 @@ _INITIAL_RESULT_BATCH = 50
 _RESULT_BATCH_SIZE = 10
 _RESULT_PREFETCH_THRESHOLD = 5
 
+
+def _NO_DATA(text: str) -> tuple[str, str]:
+    """Detail line that marks a section with no data, instead of omitting it."""
+    return ("static_markup", f"  [dim]{text}[/]")
+
+
 _ISA_FAMILIES: list[str] = [
     name for name, _ in sorted(ISA_FAMILY_ORDER.items(), key=lambda item: item[1])
 ]
@@ -1781,6 +1787,8 @@ class SimdrefApp(App):
         if linked:
             self._append_operand_section(payload, linked)
             self._append_perf_sections(payload, linked)
+        else:
+            payload.append(_NO_DATA("no linked instruction: no operands or performance data"))
         if intrinsic.doc_sections:
             self._append_description_sections(payload, intrinsic.doc_sections)
         if linked and linked.description:
@@ -1816,6 +1824,7 @@ class SimdrefApp(App):
 
     def _append_operand_section(self, payload: list[tuple], item: InstructionRecord) -> None:
         if not item.operand_details:
+            payload.append(_NO_DATA("operands: no data"))
             return
         table = Table(header_style="bold blue")
         table.add_column("idx", width=4)
@@ -1844,6 +1853,8 @@ class SimdrefApp(App):
                 payload.append(
                     ("static_markup", f"  [green]latency:[/] {lat}  [green]CPI:[/] {cpi}")
                 )
+            else:
+                payload.append(_NO_DATA("performance: no data"))
             return
         label_map = {
             "uarch": "microarch",