siligent 0.1.0__tar.gz

siligent-0.1.0/LICENSE

@@ -0,0 +1,202 @@
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siligent-0.1.0/PKG-INFO

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+Metadata-Version: 2.4
+Name: siligent
+Version: 0.1.0
+Summary: Lets AI agents flash, test and measure real microcontroller boards, behind safety rules.
+Author: Uwa Uwa Agbai
+License-Expression: Apache-2.0
+Project-URL: Homepage, https://github.com/uwaagbai1/siligent
+Project-URL: Issues, https://github.com/uwaagbai1/siligent/issues
+Keywords: embedded,stm32,ai-agents,mcp,hardware-in-the-loop
+Requires-Python: >=3.11
+Description-Content-Type: text/markdown
+License-File: LICENSE
+Requires-Dist: pyocd>=0.36
+Requires-Dist: mcp>=2.0
+Provides-Extra: ina219
+Requires-Dist: smbus2>=0.4; extra == "ina219"
+Provides-Extra: dev
+Requires-Dist: pytest>=8; extra == "dev"
+Dynamic: license-file
+
+# Siligent
+
+An open-source framework that lets AI coding agents flash, test and measure
+real microcontroller boards, behind safety rules, so a firmware change is
+proven on the chip, not just compiled.
+
+## Try it in a minute (no hardware)
+
+```sh
+python3 -m venv .venv && .venv/bin/pip install -e ".[dev]"
+nice -n 19 make -j3 -C firmware/l476     # needs arm-none-eabi-gcc
+.venv/bin/python scripts/demo.py         # needs Renode, see "Virtual board"
+```
+
+## Status: early alpha, working on a real NUCLEO-L476RG
+
+One board so far (STM32L476RG over ST-LINK). Expect the interfaces to change.
+
+- Detects the ST-LINK by USB ID and the chip by its device ID, then loads that board's rules.
+- Flashes through a safety gate; refusals say which rule fired and why.
+- Runs on-device tests and reports pass/fail and CPU cycles per test.
+- Backs up flash before every write; `siligent restore` puts a backup back.
+- Logs every action, allowed or refused.
+- MCP server so agents (Claude Code, Cursor, others) can use all of the above.
+
+Not done yet: energy numbers on real hardware. Two meter drivers are written
+and unit-tested but have not run on a real meter: the INA219 (active current
+only) and the Nordic PPK2 (down to sub-microamp, see `plugins/siligent-ppk2`,
+a separate GPL-2.0 package because its library is GPL).
+
+Meters are plugins: a package registers a factory under the
+`siligent.meters` entry-point group. When a meter powers the board, the core
+checks the voltage against the board's supply range before any plugin runs.
+
+## Virtual board (Renode)
+
+Add `--virtual` to any command to use a simulated L476 instead of real
+hardware (agent tools take `virtual: true`). The same safety rules apply.
+
+```sh
+.venv/bin/siligent --virtual test firmware/l476/build/tests.elf
+```
+
+- Needs [Renode](https://github.com/renode/renode/releases) (tested with
+  1.17.0). It is found on PATH, in `~/.local/opt/renode-*/`, or via `RENODE=`.
+- Renode has no STM32L4 model, so `src/siligent/boards/renode/stm32l476rg.repl`
+  describes the core, cycle counter, flash, SRAM and ID registers. Peripherals
+  are not modelled yet.
+- Cycle counts are simulated: within about 10-30% of the real chip for the
+  example tests (the real chip is slower, mostly flash wait states). No energy.
+
+## Quick start
+
+```sh
+python3 -m venv .venv
+.venv/bin/pip install -e ".[dev]"
+.venv/bin/pyocd pack install stm32l476rg
+nice -n 19 make -j3 -C firmware/l476
+cp bench.example.toml bench.toml   # then set flash_allowed = true when the bench is safe to flash
+
+.venv/bin/siligent detect
+.venv/bin/siligent test firmware/l476/build/tests.elf
+.venv/bin/siligent flash firmware/l476/build/demo_refused.elf   # refused on purpose
+.venv/bin/siligent log
+```
+
+Every command prints JSON. Other commands: `rules`, `check` (image checks
+without hardware), `read`, `write`, `restore`.
+
+Agent access (MCP, stdio): run `siligent-mcp`. Tools: `detect_hardware`,
+`board_rules`, `check_image`, `flash`, `run_tests`, `read_memory`,
+`write_memory`, `action_log`.
+
+## What the safety gate enforces (NUCLEO-L476RG)
+
+Rules live in `src/siligent/boards/stm32l476rg.toml`.
+
+- Flash only after a person confirms the bench is safe to flash (`flash_allowed = true` in `bench.toml`).
+- Flash only if the chip matches the rules (device ID 0x415) and read protection is level 0.
+- Firmware must sit inside flash, start with a valid vector table, and must not
+  contain the option-byte unlock keys (heuristic: catches firmware that could lock the chip).
+- Host writes only to RAM, peripherals and core debug registers; never to the
+  flash controller, option bytes or OTP.
+- SWD pins (PA13, PA14) cannot be switched out of debug mode by a host write.
+- The core is halted (with a reset) before erasing: erasing under running
+  firmware locks the core up.
+
+## Writing on-device tests
+
+See `firmware/l476/tests.c`:
+
+```c
+#include "bp_test.h"
+BP_TEST(my_test) { BP_ASSERT_EQ(add(2, 2), 4); }
+```
+
+Results go to a RAM mailbox (`bp_results`) that the host reads after the run.
+
+## Tests
+
+```sh
+.venv/bin/pytest -q
+```
+
+The virtual-board tests skip if Renode or the built firmware is missing. Set
+`SILIGENT_REQUIRE_RENODE=1` to make them fail instead, as CI does. CI
+(`.github/workflows/ci.yml`) runs the unit tests on Python 3.11-3.13 and runs
+the example firmware on the virtual board.
+
+## Licence
+
+Apache-2.0 (see `LICENSE`). The PPK2 plugin in `plugins/siligent-ppk2` is a
+separate package under GPL-2.0, because the library it uses is GPL-2.0.

siligent-0.1.0/README.md

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+# Siligent
+
+An open-source framework that lets AI coding agents flash, test and measure
+real microcontroller boards, behind safety rules, so a firmware change is
+proven on the chip, not just compiled.
+
+## Try it in a minute (no hardware)
+
+```sh
+python3 -m venv .venv && .venv/bin/pip install -e ".[dev]"
+nice -n 19 make -j3 -C firmware/l476     # needs arm-none-eabi-gcc
+.venv/bin/python scripts/demo.py         # needs Renode, see "Virtual board"
+```
+
+## Status: early alpha, working on a real NUCLEO-L476RG
+
+One board so far (STM32L476RG over ST-LINK). Expect the interfaces to change.
+
+- Detects the ST-LINK by USB ID and the chip by its device ID, then loads that board's rules.
+- Flashes through a safety gate; refusals say which rule fired and why.
+- Runs on-device tests and reports pass/fail and CPU cycles per test.
+- Backs up flash before every write; `siligent restore` puts a backup back.
+- Logs every action, allowed or refused.
+- MCP server so agents (Claude Code, Cursor, others) can use all of the above.
+
+Not done yet: energy numbers on real hardware. Two meter drivers are written
+and unit-tested but have not run on a real meter: the INA219 (active current
+only) and the Nordic PPK2 (down to sub-microamp, see `plugins/siligent-ppk2`,
+a separate GPL-2.0 package because its library is GPL).
+
+Meters are plugins: a package registers a factory under the
+`siligent.meters` entry-point group. When a meter powers the board, the core
+checks the voltage against the board's supply range before any plugin runs.
+
+## Virtual board (Renode)
+
+Add `--virtual` to any command to use a simulated L476 instead of real
+hardware (agent tools take `virtual: true`). The same safety rules apply.
+
+```sh
+.venv/bin/siligent --virtual test firmware/l476/build/tests.elf
+```
+
+- Needs [Renode](https://github.com/renode/renode/releases) (tested with
+  1.17.0). It is found on PATH, in `~/.local/opt/renode-*/`, or via `RENODE=`.
+- Renode has no STM32L4 model, so `src/siligent/boards/renode/stm32l476rg.repl`
+  describes the core, cycle counter, flash, SRAM and ID registers. Peripherals
+  are not modelled yet.
+- Cycle counts are simulated: within about 10-30% of the real chip for the
+  example tests (the real chip is slower, mostly flash wait states). No energy.
+
+## Quick start
+
+```sh
+python3 -m venv .venv
+.venv/bin/pip install -e ".[dev]"
+.venv/bin/pyocd pack install stm32l476rg
+nice -n 19 make -j3 -C firmware/l476
+cp bench.example.toml bench.toml   # then set flash_allowed = true when the bench is safe to flash
+
+.venv/bin/siligent detect
+.venv/bin/siligent test firmware/l476/build/tests.elf
+.venv/bin/siligent flash firmware/l476/build/demo_refused.elf   # refused on purpose
+.venv/bin/siligent log
+```
+
+Every command prints JSON. Other commands: `rules`, `check` (image checks
+without hardware), `read`, `write`, `restore`.
+
+Agent access (MCP, stdio): run `siligent-mcp`. Tools: `detect_hardware`,
+`board_rules`, `check_image`, `flash`, `run_tests`, `read_memory`,
+`write_memory`, `action_log`.
+
+## What the safety gate enforces (NUCLEO-L476RG)
+
+Rules live in `src/siligent/boards/stm32l476rg.toml`.
+
+- Flash only after a person confirms the bench is safe to flash (`flash_allowed = true` in `bench.toml`).
+- Flash only if the chip matches the rules (device ID 0x415) and read protection is level 0.
+- Firmware must sit inside flash, start with a valid vector table, and must not
+  contain the option-byte unlock keys (heuristic: catches firmware that could lock the chip).
+- Host writes only to RAM, peripherals and core debug registers; never to the
+  flash controller, option bytes or OTP.
+- SWD pins (PA13, PA14) cannot be switched out of debug mode by a host write.
+- The core is halted (with a reset) before erasing: erasing under running
+  firmware locks the core up.
+
+## Writing on-device tests
+
+See `firmware/l476/tests.c`:
+
+```c
+#include "bp_test.h"
+BP_TEST(my_test) { BP_ASSERT_EQ(add(2, 2), 4); }
+```
+
+Results go to a RAM mailbox (`bp_results`) that the host reads after the run.
+
+## Tests
+
+```sh
+.venv/bin/pytest -q
+```
+
+The virtual-board tests skip if Renode or the built firmware is missing. Set
+`SILIGENT_REQUIRE_RENODE=1` to make them fail instead, as CI does. CI
+(`.github/workflows/ci.yml`) runs the unit tests on Python 3.11-3.13 and runs
+the example firmware on the virtual board.
+
+## Licence
+
+Apache-2.0 (see `LICENSE`). The PPK2 plugin in `plugins/siligent-ppk2` is a
+separate package under GPL-2.0, because the library it uses is GPL-2.0.

siligent-0.1.0/pyproject.toml

@@ -0,0 +1,38 @@
+[build-system]
+requires = ["setuptools>=77"]
+build-backend = "setuptools.build_meta"
+
+[project]
+name = "siligent"
+version = "0.1.0"
+description = "Lets AI agents flash, test and measure real microcontroller boards, behind safety rules."
+readme = "README.md"
+requires-python = ">=3.11"
+license = "Apache-2.0"
+authors = [{ name = "Uwa Uwa Agbai" }]
+keywords = ["embedded", "stm32", "ai-agents", "mcp", "hardware-in-the-loop"]
+dependencies = [
+    "pyocd>=0.36",
+    "mcp>=2.0",
+]
+
+[project.optional-dependencies]
+ina219 = ["smbus2>=0.4"]
+dev = ["pytest>=8"]
+
+[project.urls]
+Homepage = "https://github.com/uwaagbai1/siligent"
+Issues = "https://github.com/uwaagbai1/siligent/issues"
+
+[project.scripts]
+siligent = "siligent.cli:main"
+siligent-mcp = "siligent.mcp_server:main"
+
+[tool.setuptools.packages.find]
+where = ["src"]
+
+[tool.setuptools.package-data]
+siligent = ["boards/*.toml", "boards/renode/*.repl"]
+
+[tool.pytest.ini_options]
+testpaths = ["tests"]

siligent-0.1.0/setup.cfg

@@ -0,0 +1,4 @@
+[egg_info]
+tag_build = 
+tag_date = 0
+

siligent-0.1.0/src/siligent/__init__.py

@@ -0,0 +1,3 @@
+"""Siligent: safe, measured access to real hardware for AI agents."""
+
+__version__ = "0.1.0"

siligent-0.1.0/src/siligent/api.py

@@ -0,0 +1,127 @@
+"""Plain functions shared by the CLI and the MCP server. Each returns a JSON-ready dict."""
+
+from __future__ import annotations
+
+from .bench import Bench, BenchConfig
+from .detect import scan_meters, scan_usb
+from .errors import SiligentError, SafetyRefusal
+from .image import load_image
+from .rules import load_rules
+from .runner import run_tests as _run_tests
+from .safety import BenchState, SafetyGate
+
+
+def _guard(fn):
+    """Turn refusals and errors into structured results an agent can act on."""
+
+    def wrapper(*args, **kwargs):
+        try:
+            return fn(*args, **kwargs)
+        except SafetyRefusal as e:
+            return e.to_dict()
+        except SiligentError as e:
+            return {"ok": False, "error": str(e)}
+        except Exception as e:  # hardware and library errors: report, don't crash the agent's tool call
+            return {"ok": False, "error": f"{type(e).__name__}: {e}"}
+
+    wrapper.__name__ = fn.__name__
+    wrapper.__doc__ = fn.__doc__
+    return wrapper
+
+
+@_guard
+def detect(config: BenchConfig | None = None, connect: bool = True) -> dict:
+    """List debug probes and, for supported ones, identify the board and its rules."""
+    probes = [p.to_dict() for p in scan_usb()]
+    result: dict = {"ok": True, "probes": probes, "meters": scan_meters()}
+    if connect and any(p["supported"] for p in probes):
+        try:
+            with Bench(config) as bench:
+                result["board"] = {
+                    "name": bench.rules.name,
+                    "chip": bench.rules.chip,
+                    "dev_id": hex(bench.probe.device_id()),
+                    "probe_uid": bench.probe.backend.unique_id,
+                    "rules": bench.rules.source,
+                }
+        except SafetyRefusal as e:
+            result["board"] = e.to_dict()
+    return result
+
+
+@_guard
+def rules(board: str = "stm32l476rg") -> dict:
+    """Show the safety rules for a board."""
+    return {"ok": True, **load_rules(board).summary()}
+
+
+@_guard
+def check_image(path: str, board: str = "stm32l476rg", config: BenchConfig | None = None) -> dict:
+    """Check a firmware image against a board's rules without touching hardware."""
+    cfg = config or BenchConfig.load()
+    image = load_image(path)
+    gate = SafetyGate(load_rules(cfg.board or board), BenchState(cfg.flash_allowed))
+    gate.check_image(image)
+    return {"ok": True, "image": path, "sha256": image.sha256, "bytes": image.size, "detail": "passes image checks"}
+
+
+@_guard
+def flash(path: str, config: BenchConfig | None = None) -> dict:
+    """Flash a firmware image through the safety gate."""
+    with Bench(config) as bench:
+        return bench.probe.flash(load_image(path))
+
+
+@_guard
+def restore(path: str, config: BenchConfig | None = None) -> dict:
+    """Put a saved full-flash snapshot (raw .bin from the start of flash) back on the chip.
+
+    The same safety checks apply as for any flash. Trailing erased bytes are skipped.
+    """
+    from pathlib import Path
+
+    from .image import Image, Segment
+
+    raw = Path(path).read_bytes().rstrip(b"\xff")
+    raw += b"\xff" * (-len(raw) % 8)  # flash programs in 8-byte double words
+    with Bench(config) as bench:
+        image = Image(path, [Segment(bench.rules.flash.start, raw)])
+        return bench.probe.flash(image)
+
+
+@_guard
+def run_tests(path: str, timeout_s: float = 10.0, config: BenchConfig | None = None) -> dict:
+    """Flash test firmware, run it, and return pass/fail, cycles and energy."""
+    with Bench(config) as bench:
+        return _run_tests(bench.probe, load_image(path), meter=bench.meter, timeout_s=timeout_s)
+
+
+@_guard
+def read_memory(address: int, length: int, config: BenchConfig | None = None) -> dict:
+    """Read memory from the chip."""
+    if not 0 < length <= 4096:
+        raise SiligentError("length must be between 1 and 4096 bytes")
+    with Bench(config) as bench:
+        data, halted = bench.probe.read_memory_checked(address, length)
+    out = {"ok": True, "address": hex(address), "length": length, "hex": data.hex()}
+    if halted:
+        out["note"] = "the core was asleep, so it was halted briefly for this read and then resumed"
+    return out
+
+
+@_guard
+def write_memory(address: int, data_hex: str, config: BenchConfig | None = None) -> dict:
+    """Write bytes to RAM or a peripheral register, subject to the board's rules."""
+    data = bytes.fromhex(data_hex)
+    with Bench(config) as bench:
+        bench.probe.write_memory(address, data)
+    return {"ok": True, "address": hex(address), "length": len(data)}
+
+
+@_guard
+def action_log(n: int = 20, config: BenchConfig | None = None) -> dict:
+    """The most recent bench actions, allowed and refused."""
+    cfg = config or BenchConfig.load()
+    from .log import ActionLog
+
+    return {"ok": True, "entries": ActionLog(cfg.log_path).tail(n)}