siliconcompiler 0.36.2__tar.gz → 0.36.3__tar.gz

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/Changes

@@ -8,6 +8,18 @@ The changes in each SiliconCompiler release version are described below. Commit
 version shown in (). Where applicable, the contributors that suggested a given
 feature are shown in [].
 
+SiliconCompiler 0.36.3 (2026-01-21)
+=========================================
+
+**Minor:**
+
+ * Tools:
+
+  * builtin: added wait task to better handle stalling flow progress
+  * klayout: added merge task to provide a simple interface for merging multiple GDSs
+  * pyslang: updated to v10.0.0
+
+
 SiliconCompiler 0.36.2 (2026-01-16)
 =========================================
 

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: siliconcompiler
-Version: 0.36.2
+Version: 0.36.3
 Summary: A compiler framework that automates translation from source code to silicon.
 Author: Zero ASIC
 License: Apache License 2.0
@@ -43,7 +43,7 @@ Requires-Dist: fasteners>=0.20
 Requires-Dist: pandas>=1.1.5
 Requires-Dist: psutil>=5.8.0
 Requires-Dist: Jinja2>=2.11.3
-Requires-Dist: pyslang==9.1.0
+Requires-Dist: pyslang==10.0.0
 Requires-Dist: importlib_metadata; python_version < "3.10"
 Requires-Dist: streamlit==1.46.1; python_full_version != "3.9.7"
 Requires-Dist: streamlit_agraph==0.0.45; python_full_version != "3.9.7"

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/pyproject.toml

@@ -52,7 +52,7 @@ dependencies = [
     "psutil >= 5.8.0",
     "Jinja2 >= 2.11.3",
 
-    "pyslang == 9.1.0",
+    "pyslang == 10.0.0",
 
     "importlib_metadata; python_version < '3.10'",
 

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/scripts/.gitignore

@@ -1,4 +1,5 @@
 /build
 /*.png
+/*.dot
 /*.xlsx
 /*#

siliconcompiler-0.36.3/scripts/class_hierarchy.py

@@ -0,0 +1,128 @@
+#!/usr/bin/env python3
+import inspect
+import importlib
+from argparse import ArgumentParser
+
+try:
+    import graphviz
+    _has_graphviz = True
+except ModuleNotFoundError:
+    _has_graphviz = False
+
+
+# Import all the classes
+from siliconcompiler import (Project, ASIC, FPGA, Lint, Sim, Design, PDK,
+                             Flowgraph, Checklist, StdCellLibrary, FPGADevice,
+                             Task, ShowTask, ScreenshotTask, Schematic)
+from siliconcompiler.asic import ASICTask
+from siliconcompiler.constraints import (ASICTimingConstraintSchema, ASICAreaConstraint,
+                                         ASICComponentConstraints, ASICPinConstraints,
+                                         FPGAComponentConstraints, FPGAPinConstraints,
+                                         FPGATimingConstraintSchema)
+from siliconcompiler.schema_support import metric, record, option
+from siliconcompiler.library import ToolLibrarySchema
+
+
+def generate_class_hierarchy(classes, output_file="class_hierarchy"):
+    """
+    Generates a class inheritance graph using graphviz.
+    """
+    if not _has_graphviz:
+        raise RuntimeError("Graphviz is not installed."
+                           " Please install it to generate class hierarchy graphs.")
+
+    dot = graphviz.Digraph('SiliconCompiler Class Hierarchy',
+                           comment='SiliconCompiler Class Hierarchy')
+    dot.attr('graph', rankdir='RL', concentrate='true')
+    dot.attr('node', shape='box', style='rounded,filled')
+
+    SCHEMA_COLOR = "#fff8dc"  # cornsilk
+    SCHEMA_SUPPORT_COLOR = "#add8e6"  # lightblue
+    DEFAULT_COLOR = "#d3d3d3"  # lightgrey
+
+    # Classes exposed at the top-level of the siliconcompiler package
+    TOP_LEVEL_CLASSES = {
+        'Project', 'ASIC', 'FPGA', 'Lint', 'Sim', 'Design', 'PDK',
+        'Flowgraph', 'Checklist', 'StdCellLibrary', 'FPGADevice',
+        'Task', 'ShowTask', 'ScreenshotTask', 'Schematic'
+    }
+
+    added_nodes = set()
+
+    all_mro_classes = set()
+    for cls in classes:
+        mro = [c for c in inspect.getmro(cls) if 'siliconcompiler' in c.__module__ or c is cls]
+        all_mro_classes.update(mro)
+
+    # Create a subgraph for top-level classes to cluster them
+    with dot.subgraph(name='cluster_api') as c:
+        c.attr(label='SiliconCompiler API', style='filled', color='#f0f0f0', fontcolor='black')
+
+        for cls in all_mro_classes:
+            if cls.__name__ not in added_nodes:
+                module_name = cls.__module__
+                if module_name.startswith('siliconcompiler.schema.'):
+                    color = SCHEMA_COLOR
+                elif module_name.startswith('siliconcompiler.schema_support.'):
+                    color = SCHEMA_SUPPORT_COLOR
+                else:
+                    color = DEFAULT_COLOR
+
+                # Add node to the cluster or the main graph
+                if cls.__name__ in TOP_LEVEL_CLASSES:
+                    c.node(cls.__name__, fillcolor=color)
+                else:
+                    dot.node(cls.__name__, fillcolor=color)
+                added_nodes.add(cls.__name__)
+    edges = []
+    for cls in all_mro_classes:
+        for base in cls.__bases__:
+            if 'siliconcompiler' not in base.__module__:
+                continue
+            if (base.__name__, cls.__name__) in edges:
+                continue
+            edges.append((base.__name__, cls.__name__))
+            # Add edge
+            dot.edge(f"{base.__name__}:w", f"{cls.__name__}:e")
+    # Save the dot file and render a PNG
+    try:
+        dot.render(output_file, view=False, format='png', cleanup=True)
+        print(f"Generated class hierarchy graph at {output_file}.png")
+    except graphviz.ExecutableNotFound:
+        print("Graphviz executable not found. Please install it and add it to your PATH.")
+        print("On Debian/Ubuntu: sudo apt-get install graphviz")
+        print("On macOS (with Homebrew): brew install graphviz")
+
+    with open(f"{output_file}.dot", 'w') as f:
+        f.write(dot.source)
+    print(f"Generated dot file at {output_file}.dot")
+
+
+if __name__ == "__main__":
+    parser = ArgumentParser(
+        description="Generate a class inheritance graph for SiliconCompiler classes.")
+    parser.add_argument("cls", nargs="?",
+                        help="A specific class to graph in module/ClassName format "
+                             "(e.g., siliconcompiler/Project).")
+    parser.add_argument("--output", default="class_hierarchy",
+                        help="Output file name without extension.")
+    args = parser.parse_args()
+
+    if args.cls:
+        module, cls_name = args.cls.split("/")
+        classes_to_graph = [getattr(importlib.import_module(module), cls_name)]
+    else:
+        # The list of classes from methods.py
+        classes_to_graph = [
+            Project, ASIC, FPGA, Lint, Sim,
+            Design, PDK, Flowgraph, Checklist, StdCellLibrary, FPGADevice, Schematic,
+            Task, ShowTask, ScreenshotTask,
+            ASICTask,
+            ASICTimingConstraintSchema, ASICAreaConstraint, ASICComponentConstraints,
+            ASICPinConstraints, FPGAComponentConstraints, FPGAPinConstraints,
+            FPGATimingConstraintSchema,
+            metric.MetricSchema, record.RecordSchema, option.OptionSchema,
+            ToolLibrarySchema
+        ]
+
+    generate_class_hierarchy(classes_to_graph, args.output)

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.36.2'
+version = '0.36.3'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler/project.py

@@ -4,7 +4,7 @@ import uuid
 
 import os.path
 
-from typing import Union, List, Tuple, TextIO, Optional, Dict, Set
+from typing import Type, Union, List, Tuple, TextIO, Optional, Dict, Set, TypeVar
 
 from siliconcompiler.schema import BaseSchema, NamedSchema, EditableSchema, Parameter, Scope, \
     __version__ as schema_version, \
@@ -33,6 +33,8 @@ from siliconcompiler.utils.multiprocessing import MPManager
 from siliconcompiler.utils.paths import jobdir, workdir
 from siliconcompiler.flows.showflow import ShowFlow
 
+TProject = TypeVar("TProject", bound="Project")
+
 
 class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
     """
@@ -236,7 +238,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
         return self.get("option", field="schema")
 
     @classmethod
-    def convert(cls, obj: "Project") -> "Project":
+    def convert(cls: Type[TProject], obj: "Project") -> TProject:
         """
         Converts a project from one type to another (e.g., Project to Sim).
 
@@ -526,7 +528,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
                                  f"{', '.join([f'{step}/{index}' for step, index in breakpoints])}")
                 self.__dashboard.stop()
 
-    def run(self) -> "Project":
+    def run(self) -> TProject:
         '''
         Executes the compilation flow defined in the project's flowgraph.
 
@@ -1238,7 +1240,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
             return None
 
         # Create copy of project to avoid changing user project
-        proj: Project = self.copy()
+        proj = self.copy()
         proj.set_flow(ShowFlow(task))
 
         # Setup options:

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler/schema/baseschema.py

@@ -26,12 +26,15 @@ import os.path
 
 from enum import Enum, auto
 from functools import cache
-from typing import Dict, Type, Tuple, Union, Set, Callable, List, Optional, TextIO, Iterable, Any
+from typing import Dict, Type, Tuple, TypeVar, Union, Set, Callable, List, Optional, \
+    TextIO, Iterable, Any
 
 from .parameter import Parameter, NodeValue
 from .journal import Journal
 from ._metadata import version
 
+TSchema = TypeVar('TSchema', bound='BaseSchema')
+
 
 class LazyLoad(Enum):
     """
@@ -286,10 +289,10 @@ class BaseSchema:
 
     # Manifest methods
     @classmethod
-    def from_manifest(cls,
+    def from_manifest(cls: Type[TSchema],
                       filepath: Union[None, str] = None,
                       cfg: Union[None, Dict] = None,
-                      lazyload: bool = True) -> "BaseSchema":
+                      lazyload: bool = True) -> TSchema:
         '''
         Create a new schema based on the provided source files.
 
@@ -849,7 +852,7 @@ class BaseSchema:
         return manifest
 
     # Utility functions
-    def copy(self, key: Optional[Tuple[str, ...]] = None) -> "BaseSchema":
+    def copy(self: TSchema, key: Optional[Tuple[str, ...]] = None) -> TSchema:
         """
         Returns a copy of this schema.
 

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler/schema/docschema.py

@@ -1,6 +1,6 @@
-from typing import Union, List
+from typing import Type, Union, List
 
-from .baseschema import BaseSchema
+from .baseschema import BaseSchema, TSchema
 
 
 class DocsSchema(BaseSchema):
@@ -11,7 +11,7 @@ class DocsSchema(BaseSchema):
     """
 
     @classmethod
-    def make_docs(cls) -> Union[BaseSchema, List[BaseSchema]]:
+    def make_docs(cls: Type[TSchema]) -> Union[TSchema, List[TSchema]]:
         """Generate the documentation representation for this schema.
 
         By default, this method returns a standard instance of the class itself.

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler/schema/editableschema.py

@@ -163,7 +163,7 @@ class EditableSchema:
             new_schema._BaseSchema__parent = None
         return new_schema
 
-    def rename(self, name: str):
+    def rename(self, name: str) -> None:
         '''
         Renames a named schema
         '''

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler/schema/namedschema.py

@@ -4,9 +4,9 @@
 # SC dependencies outside of its directory, since it may be used by tool drivers
 # that have isolated Python environments.
 
-from typing import Dict, Tuple, Optional, Set, Union, List
+from typing import Dict, Tuple, Optional, Set, Type, Union, List
 
-from .baseschema import BaseSchema, LazyLoad
+from .baseschema import BaseSchema, LazyLoad, TSchema
 
 
 class NamedSchema(BaseSchema):
@@ -76,11 +76,11 @@ class NamedSchema(BaseSchema):
         return cfg.get("__meta__", {}).get("name", None)
 
     @classmethod
-    def from_manifest(cls,
+    def from_manifest(cls: Type[TSchema],
                       filepath: Union[None, str] = None,
                       cfg: Union[None, Dict] = None,
                       lazyload: bool = True,
-                      name: Optional[str] = None):
+                      name: Optional[str] = None) -> TSchema:
         '''
         Create a new schema based on the provided source files.
 
@@ -115,8 +115,8 @@ class NamedSchema(BaseSchema):
 
         return super()._from_dict(manifest, keypath, version=version, lazyload=lazyload)
 
-    def copy(self, key: Optional[Tuple[str, ...]] = None) -> "NamedSchema":
-        copy: NamedSchema = super().copy(key=key)
+    def copy(self: TSchema, key: Optional[Tuple[str, ...]] = None) -> TSchema:
+        copy = super().copy(key=key)
 
         if key and key[-1] != "default":
             copy.__name = key[-1]

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler/schema_support/cmdlineschema.py

@@ -4,12 +4,14 @@ import sys
 
 import os.path
 
-from typing import Set, List, Optional, Union
+from typing import Set, List, Optional, Type, Union, TypeVar
 
 from siliconcompiler.schema import BaseSchema, EditableSchema, Parameter, Scope, PerNode
 from siliconcompiler.schema.utils import trim
 from siliconcompiler import _metadata
 
+TCmdSchema = TypeVar("TCmdSchema", bound="CommandLineSchema")
+
 
 class CommandLineSchema(BaseSchema):
     '''
@@ -68,14 +70,14 @@ class CommandLineSchema(BaseSchema):
         EditableSchema(self).insert("cmdarg", name, Parameter(type, **kwargs))
 
     @classmethod
-    def create_cmdline(cls,
+    def create_cmdline(cls: Type[TCmdSchema],
                        progname: Optional[str] = None,
                        description: Optional[str] = None,
                        switchlist: Optional[Union[List[str], Set[str]]] = None,
                        version: Optional[str] = None,
                        print_banner: bool = True,
                        use_cfg: bool = False,
-                       use_sources: bool = True) -> BaseSchema:
+                       use_sources: bool = True) -> TCmdSchema:
         """
         Creates an SC command line interface.
 

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler/tool.py

@@ -53,7 +53,8 @@ if TYPE_CHECKING:
     from siliconcompiler.scheduler import SchedulerNode
     from siliconcompiler import Project
 
-TTask = TypeVar('TTask')
+TTask = TypeVar('TTask', bound='Task')
+TShowTask = TypeVar('TShowTask', bound='ShowTask')
 
 
 class TaskError(Exception):
@@ -2177,7 +2178,8 @@ class ShowTask(Task):
             cls.register_task(c)
 
     @classmethod
-    def get_task(cls, ext: Optional[str]) -> Union[Optional["ShowTask"], Set[Type["ShowTask"]]]:
+    def get_task(cls: Type[TShowTask], ext: Optional[str]) -> \
+            Union[Optional[TShowTask], Set[Type[TShowTask]]]:
         """
         Retrieves a suitable show task instance for a given file extension.
 

siliconcompiler-0.36.3/siliconcompiler/tools/builtin/wait.py

@@ -0,0 +1,16 @@
+from siliconcompiler.tools.builtin import BuiltinTask
+
+
+class Wait(BuiltinTask):
+    '''
+    A wait task that stalls the flow until all inputs are available.
+    '''
+    def __init__(self):
+        super().__init__()
+
+    def _set_io_files(self):
+        # No file IO needed for wait task
+        return
+
+    def task(self):
+        return "wait"

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler/tools/klayout/export.py

@@ -79,8 +79,6 @@ class ExportTask(KLayoutTask, ScreenshotParams):
         self.add_output_file(ext="lyt")
         self.add_output_file(ext="lyp")
 
-        self.add_required_key("var", "stream")
-
         sc_stream_order = [default_stream, *[s for s in ("gds", "oas") if s != default_stream]]
         req_set = False
         for s in sc_stream_order:

siliconcompiler-0.36.3/siliconcompiler/tools/klayout/merge.py

@@ -0,0 +1,95 @@
+from typing import Optional, Union
+
+from siliconcompiler.tools.klayout import KLayoutTask
+
+
+class Merge(KLayoutTask):
+    """
+    Klayout task to merge multiple GDS files and provide prefixing for cell names.
+    """
+    def __init__(self):
+        super().__init__()
+
+        self.add_parameter("reference", "(<fs,input>,str,str)",
+                           "Reference fileset or input node for merge operation, structured as "
+                           "(fs, library name, fileset) or (input, step, index)")
+        self.add_parameter("merge", "[(<fs,input>,str,str,str)]",
+                           "Fileset or input node to be merge with prefix, structured as "
+                           "(fs, library name, fileset) or (input, step, index) along with prefix "
+                           "string")
+
+    def __fix_type(self, type: str) -> str:
+        if type == "fileset":
+            return "fs"
+        return type
+
+    def set_klayout_reference(self, type: str, source0: str, source1: str,
+                              step: Optional[str] = None,
+                              index: Optional[Union[str, int]] = None):
+        """
+        Sets the reference file for the merge operation.
+        Args:
+            type (str): The reference fileset or input node.
+            source0 (str): The first part of the source (library name or step).
+            source1 (str): The second part of the source (fileset name or index).
+            step (Optional[str]): The specific step to apply this configuration to.
+            index (Optional[Union[str, int]]): The specific index to apply this configuration to.
+        """
+        self.set("var", "reference", (self.__fix_type(type), source0, source1),
+                 step=step, index=index)
+
+    def add_klayout_merge(self, type: str, source0: str, source1: str, prefix: str,
+                          step: Optional[str] = None,
+                          index: Optional[Union[str, int]] = None, clobber: bool = False):
+        """
+        Adds a file to be merged with the reference file.
+        Args:
+            type (str): The fileset or input node to be merged.
+            prefix (str): The prefix to apply during the merge.
+            source0 (str): The first part of the source (library name or step).
+            source1 (str): The second part of the source (fileset name or index).
+            step (Optional[str]): The specific step to apply this configuration to.
+            index (Optional[Union[str, int]]): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list of merge files.
+                                      If False, appends to the list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "merge", (self.__fix_type(type), source0, source1, prefix),
+                     step=step, index=index)
+        else:
+            self.add("var", "merge", (self.__fix_type(type), source0, source1, prefix),
+                     step=step, index=index)
+
+    def task(self) -> str:
+        return 'merge'
+
+    def setup(self) -> None:
+        super().setup()
+
+        self.set_script("klayout_merge.py")
+
+        self.add_required_key("var", "reference")
+        self.add_required_key("var", "merge")
+
+        if self.get("var", "reference"):
+            ref_type, ref_source0, ref_source1 = self.get("var", "reference")
+            if ref_type == 'input':
+                step, index = ref_source0, ref_source1
+                self.add_input_file(
+                    self.compute_input_file_node_name(f"{self.design_topmodule}.gds",
+                                                      step, index))
+            else:
+                lib_name, fileset = ref_source0, ref_source1
+                self.add_required_key("library", lib_name, "fileset", fileset, "file", "gds")
+        for merge_entry in self.get("var", "merge"):
+            merge_type, merge_source0, merge_source1, _ = merge_entry
+            if merge_type == 'input':
+                step, index = merge_source0, merge_source1
+                self.add_input_file(
+                    self.compute_input_file_node_name(f"{self.design_topmodule}.gds",
+                                                      step, index))
+            else:
+                lib_name, fileset = merge_source0, merge_source1
+                self.add_required_key("library", lib_name, "fileset", fileset, "file", "gds")
+
+        self.add_output_file(ext="gds")

siliconcompiler-0.36.3/siliconcompiler/tools/klayout/scripts/klayout_merge.py

@@ -0,0 +1,79 @@
+import pya
+import sys
+
+import os.path
+
+
+if __name__ == "__main__":
+    # SC_ROOT provided by CLI
+    sys.path.append(SC_KLAYOUT_ROOT)  # noqa: F821
+    sys.path.append(SC_TOOLS_ROOT)  # noqa: F821
+    sys.path.append(SC_ROOT)  # noqa: F821
+
+    from klayout_utils import (
+        technology,
+        get_schema,
+        generate_metrics
+    )
+
+    from klayout_operations import (
+        read_layout,
+        write_stream
+    )
+
+    schema = get_schema(manifest='sc_manifest.json')
+
+    # Extract info from manifest
+    sc_step = schema.get('arg', 'step')
+    sc_index = schema.get('arg', 'index')
+    sc_tool = 'klayout'
+    sc_task = 'merge'
+
+    design_name = schema.get('option', 'design')
+    fileset = schema.get("option", "fileset")[0]
+    design = schema.get("library", design_name, "fileset", fileset, "topmodule")
+
+    ref_type, ref_source0, ref_source1 = schema.get("tool", sc_tool, "task", sc_task,
+                                                    "var", "reference",
+                                                    step=sc_step, index=sc_index)
+    if ref_type == 'input':
+        step, index = ref_source0, ref_source1
+        input_file = os.path.join('inputs', f"{design}.{ref_source0}{ref_source1}.gds")
+    else:
+        input_file = schema.get("library", ref_source0, "fileset", ref_source1, "file", "gds")[0]
+
+    merge_files = []
+    for merge_type, merge_source0, merge_source1, prefix in \
+            schema.get("tool", sc_tool, "task", sc_task, "var", "merge",
+                       step=sc_step, index=sc_index):
+        if merge_type == 'input':
+            merge_file = os.path.join('inputs', f"{design}.{merge_source0}{merge_source1}.gds")
+        else:
+            merge_file = schema.get("library", merge_source0, "fileset", merge_source1,
+                                    "file", "gds")[0]
+        merge_files.append((prefix, merge_file))
+
+    tech = technology(design, schema)
+    base_layout = read_layout(input_file)
+    top_cell = base_layout.top_cell()
+    base_layout.technology_name = tech.name
+
+    for prefix, merge_file in merge_files:
+        print(f"[INFO] Merging file '{merge_file}' with prefix '{prefix}'")
+        merge_layout = read_layout(merge_file)
+
+        merge_top = merge_layout.top_cell()
+
+        new_cell_name = f"{prefix}{merge_top.name}"
+        if base_layout.cell(new_cell_name):
+            print(f"[WARN] Cell '{new_cell_name}' already exists in base layout. Skipping.")
+            continue
+        print(f"[INFO] Adding cell '{merge_top.name}' as '{new_cell_name}'")
+        new_cell = base_layout.create_cell(new_cell_name)
+        new_cell.copy_tree(merge_top)
+        cell_inst = pya.CellInstArray(new_cell.cell_index(), pya.Trans())
+        top_cell.insert(cell_inst)
+
+    write_stream(base_layout, f"outputs/{design}.gds", True)
+
+    generate_metrics()

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "e7da048335b841ec917d0c421200f2b0eda54f2c",
+    "git-commit": "11bd3ead9d12211b72706ac7c8653234cc136b8b",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "0429ac324b2cd4a12783e053b9c85f5d40f4cde8",
+    "git-commit": "dda887bc6e5160fd7c15489cc5845eaff72b5252",
     "auto-update": true
   },
   "netgen": {
@@ -168,7 +168,7 @@
   },
   "keplerformal": {
     "git-url": "https://github.com/keplertech/kepler-formal.git",
-    "git-commit": "c1edd4a196536385255f4c882e4001d534d4638b",
+    "git-commit": "d647673f3b3960256069a79e8d92d36a3b89d9a4",
     "auto-update": false
   }
-}
+}

{siliconcompiler-0.36.2 → siliconcompiler-0.36.3}/siliconcompiler.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: siliconcompiler
-Version: 0.36.2
+Version: 0.36.3
 Summary: A compiler framework that automates translation from source code to silicon.
 Author: Zero ASIC
 License: Apache License 2.0
@@ -43,7 +43,7 @@ Requires-Dist: fasteners>=0.20
 Requires-Dist: pandas>=1.1.5
 Requires-Dist: psutil>=5.8.0
 Requires-Dist: Jinja2>=2.11.3
-Requires-Dist: pyslang==9.1.0
+Requires-Dist: pyslang==10.0.0
 Requires-Dist: importlib_metadata; python_version < "3.10"
 Requires-Dist: streamlit==1.46.1; python_full_version != "3.9.7"
 Requires-Dist: streamlit_agraph==0.0.45; python_full_version != "3.9.7"