siliconcompiler 0.36.1__tar.gz → 0.36.2__tar.gz

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/Changes

@@ -8,6 +8,20 @@ The changes in each SiliconCompiler release version are described below. Commit
 version shown in (). Where applicable, the contributors that suggested a given
 feature are shown in [].
 
+SiliconCompiler 0.36.2 (2026-01-16)
+=========================================
+
+**Minor:**
+
+ * Corrected auto dataroot behavior when setting abs paths.
+ * Corrected logging during check_filepaths on design objects to ensure errors are printed.
+ * Added `.get_library` to Project to allow access to imported libraries.
+
+ * Tools:
+
+  * openroad: added option to bypass SDC loading.
+
+
 SiliconCompiler 0.36.1 (2026-01-10)
 =========================================
 

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: siliconcompiler
-Version: 0.36.1
+Version: 0.36.2
 Summary: A compiler framework that automates translation from source code to silicon.
 Author: Zero ASIC
 License: Apache License 2.0
@@ -38,7 +38,7 @@ Requires-Dist: PyYAML<7.0.0,>=6.0.0
 Requires-Dist: GitPython<3.2,>=3.1.44
 Requires-Dist: PyGithub<2.9.0,>=2.8.0
 Requires-Dist: urllib3>=1.26.0
-Requires-Dist: lambdapdk>=0.2.6
+Requires-Dist: lambdapdk>=0.2.7
 Requires-Dist: fasteners>=0.20
 Requires-Dist: pandas>=1.1.5
 Requires-Dist: psutil>=5.8.0

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/pyproject.toml

@@ -45,7 +45,7 @@ dependencies = [
     "PyGithub >= 2.8.0, < 2.9.0",
     "urllib3 >= 1.26.0", # Required for PyGithub
 
-    "lambdapdk >= 0.2.6",
+    "lambdapdk >= 0.2.7",
 
     "fasteners >= 0.20",
     "pandas >= 1.1.5",

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.36.1'
+version = '0.36.2'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/asic.py

@@ -244,7 +244,7 @@ class ASIC(Project):
             if pdk not in self.getkeys("library"):
                 error = True
                 self.logger.error(f"{pdk} library has not been loaded")
-            elif not isinstance(self.get("library", pdk, field="schema"), PDK):
+            elif not isinstance(self.get_library(pdk), PDK):
                 error = True
                 self.logger.error(f"{pdk} must be a PDK")
 
@@ -432,7 +432,7 @@ class ASIC(Project):
         if not self.get("asic", "pdk") and self.get("asic", "mainlib"):
             mainlib = None
             if self._has_library(self.get("asic", "mainlib")):
-                mainlib = self.get("library", self.get("asic", "mainlib"), field="schema")
+                mainlib = self.get_library(self.get("asic", "mainlib"))
             if mainlib:
                 mainlib_pdk = mainlib.get("asic", "pdk")
                 if mainlib_pdk:
@@ -530,7 +530,7 @@ class ASICTask(Task):
             raise ValueError("mainlib has not been defined in [asic,mainlib]")
         if mainlib not in self.project.getkeys("library"):
             raise LookupError(f"{mainlib} has not been loaded")
-        return self.project.get("library", mainlib, field="schema")
+        return self.project.get_library(mainlib)
 
     @property
     def pdk(self) -> PDK:
@@ -540,7 +540,7 @@ class ASICTask(Task):
             raise ValueError("pdk has not been defined in [asic,pdk]")
         if pdk not in self.project.getkeys("library"):
             raise LookupError(f"{pdk} has not been loaded")
-        return self.project.get("library", pdk, field="schema")
+        return self.project.get_library(pdk)
 
     def set_asic_var(self,
                      key: str,

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/design.py

@@ -694,7 +694,12 @@ class Design(DependencySchema, LibrarySchema):
         if dataroot is ...:
             dataroot = None
         else:
-            dataroot = self._get_active_dataroot(dataroot)
+            if option in ['idir', 'libdir']:
+                try:
+                    dataroot = self._get_active_dataroot(dataroot)
+                except ValueError as e:
+                    if any(not os.path.isabs(v) for v in value):
+                        raise e
 
         with self.active_dataroot(dataroot):
             if list in typelist and not clobber:

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/package/__init__.py

@@ -72,9 +72,10 @@ class Resolver:
         self.__cacheid = None
 
         if self.__root and hasattr(self.__root, "logger"):
-            self.__logger = self.__root.logger.getChild(f"resolver-{self.name}")
+            rootlogger = self.__root.logger
         else:
-            self.__logger = logging.getLogger(f"resolver-{self.name}")
+            rootlogger = MPManager.logger()
+        self.__logger = rootlogger.getChild(f"resolver-{self.name}")
 
     @staticmethod
     def populate_resolvers() -> None:

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/project.py

@@ -1,6 +1,5 @@
 import logging
 import os
-import sys
 import uuid
 
 import os.path
@@ -28,7 +27,7 @@ from siliconcompiler.schema_support.pathschema import PathSchemaBase
 
 from siliconcompiler.report.dashboard.cli import CliDashboard
 from siliconcompiler.scheduler import Scheduler, SCRuntimeError
-from siliconcompiler.utils.logging import SCColorLoggerFormatter, SCLoggerFormatter
+from siliconcompiler.utils.logging import get_stream_handler
 from siliconcompiler.utils import get_file_ext
 from siliconcompiler.utils.multiprocessing import MPManager
 from siliconcompiler.utils.paths import jobdir, workdir
@@ -143,12 +142,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
         self.__logger = MPManager.logger().getChild(f"project_{uuid.uuid4().hex}")
         self.__logger.setLevel(logging.INFO)
 
-        self._logger_console = logging.StreamHandler(stream=sys.stdout)
-        if SCColorLoggerFormatter.supports_color(sys.stdout):
-            self._logger_console.setFormatter(SCColorLoggerFormatter(SCLoggerFormatter()))
-        else:
-            self._logger_console.setFormatter(SCLoggerFormatter())
-
+        self._logger_console = get_stream_handler(self, in_run=False, step=None, index=None)
         self.__logger.addHandler(self._logger_console)
 
     def __init_dashboard(self):
@@ -225,7 +219,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
         if not self.valid("library", design_name):
             raise KeyError(f"{design_name} design has not been loaded")
 
-        return self.get("library", design_name, field="schema")
+        return self.get_library(design_name)
 
     @property
     def option(self) -> OptionSchema:
@@ -482,7 +476,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
             if not self._has_library(src_lib):
                 continue
 
-            if not self.get("library", src_lib, field="schema").has_fileset(src_fileset):
+            if not self.get_library(src_lib).has_fileset(src_fileset):
                 self.logger.error(f"{src_fileset} is not a valid fileset in {src_lib}")
                 error = True
                 continue
@@ -496,7 +490,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
                 continue
 
             if dst_fileset and \
-                    not self.get("library", dst_lib, field="schema").has_fileset(dst_fileset):
+                    not self.get_library(dst_lib).has_fileset(dst_fileset):
                 self.logger.error(f"{dst_fileset} is not a valid fileset in {dst_lib}")
                 error = True
                 continue
@@ -715,7 +709,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
             if dst_lib:
                 if not self._has_library(dst_lib):
                     raise KeyError(f"{dst_lib} is not a loaded library")
-                dst_obj = self.get("library", dst_lib, field="schema")
+                dst_obj = self.get_library(dst_lib)
             else:
                 dst_obj = None
             if not dst_fileset:
@@ -844,7 +838,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
 
         if isinstance(src_dep, str):
             if self._has_library(src_dep):
-                src_dep = self.get("library", src_dep, field="schema")
+                src_dep = self.get_library(src_dep)
             else:
                 src_dep_name = src_dep
                 src_dep = None
@@ -875,7 +869,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
                 if not self._has_library(alias_dep):
                     raise KeyError(f"{alias_dep} has not been loaded")
 
-                alias_dep = self.get("library", alias_dep, field="schema")
+                alias_dep = self.get_library(alias_dep)
 
         if alias_dep is not None:
             if isinstance(alias_dep, Design):
@@ -894,6 +888,28 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
         else:
             return self.add("option", "alias", alias)
 
+    def get_library(self, library: str) -> NamedSchema:
+        """
+        Retrieves a library by name from the project.
+
+        Args:
+            library (str): The name of the library to retrieve.
+
+        Returns:
+            NamedSchema: The `NamedSchema` object representing the library.
+
+        Raises:
+            KeyError: If the specified library is not found in the project.
+            TypeError: If the provided `library` is not a string.
+        """
+        if not isinstance(library, str):
+            raise TypeError("library must be a string")
+
+        if not self._has_library(library):
+            raise KeyError(f"{library} is not a valid library")
+
+        return self.get("library", library, field="schema")
+
     def _has_library(self, library: Union[str, NamedSchema]) -> bool:
         """
         Checks if a library with the given name exists and is loaded in the project.

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/schema_support/filesetschema.py

@@ -1,5 +1,7 @@
 import contextlib
 
+import os.path
+
 from pathlib import Path
 
 from typing import List, Tuple, Optional, Union, Iterable, Set
@@ -118,8 +120,14 @@ class FileSetSchema(PathSchema):
             ext = utils.get_file_ext(filename)
             filetype = utils.get_default_iomap().get(ext, ext)
 
+        try:
+            dataroot = self._get_active_dataroot(dataroot)
+        except ValueError as e:
+            if not os.path.isabs(filename):
+                raise e
+
         # adding files to dictionary
-        with self.active_dataroot(self._get_active_dataroot(dataroot)):
+        with self.active_dataroot(dataroot):
             if clobber:
                 return self.set('fileset', fileset, 'file', filetype, filename)
             else:

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/schema_support/pathschema.py

@@ -11,7 +11,9 @@ from siliconcompiler.schema.parameter import Parameter, Scope
 from siliconcompiler.schema.utils import trim
 
 from siliconcompiler.package import Resolver
+from siliconcompiler.utils.logging import get_stream_handler
 from siliconcompiler.utils.paths import collectiondir, cwdirsafe
+from siliconcompiler.utils.multiprocessing import MPManager
 
 
 class PathSchemaBase(BaseSchema):
@@ -19,6 +21,15 @@ class PathSchemaBase(BaseSchema):
     Schema extension to add simpler find_files and check_filepaths
     '''
 
+    def __getlogger(self, logger_name: str) -> logging.Logger:
+        schema_root = self._parent(root=True)
+        root_logger = getattr(schema_root, "logger", MPManager.logger())
+        logger = root_logger.getChild(logger_name)
+        if not logger.handlers:
+            logger.addHandler(get_stream_handler(schema_root, in_run=False, step=None, index=None))
+            logger.setLevel(logging.INFO)
+        return logger
+
     def find_files(self, *keypath: str,
                    missing_ok: bool = False,
                    step: Optional[str] = None, index: Optional[Union[int, str]] = None) \
@@ -69,13 +80,10 @@ class PathSchemaBase(BaseSchema):
             True if all file paths are valid, otherwise False.
         '''
         schema_root = self._parent(root=True)
-        logger = getattr(schema_root,
-                         "logger",
-                         logging.getLogger("siliconcompiler.check_filepaths"))
 
         return super()._check_filepaths(
             ignore_keys=ignore_keys,
-            logger=logger,
+            logger=self.__getlogger("check_filepaths"),
             collection_dir=collectiondir(schema_root),
             cwd=cwdirsafe(schema_root))
 
@@ -121,13 +129,11 @@ class PathSchemaBase(BaseSchema):
             >>> hashlist = hash_files('input', 'rtl', 'verilog')
             Computes, stores, and returns hashes of files in :keypath:`input, rtl, verilog`.
         '''
-        schema_root = self._parent(root=True)
-        logger = getattr(schema_root,
-                         "logger",
-                         logging.getLogger("siliconcompiler.hash_files"))
-
         if verbose:
-            logger.info(f"Computing hash value for [{','.join([*self._keypath, *keypath])}]")
+            self.__getlogger("hash_files").info(
+                f"Computing hash value for [{','.join([*self._keypath, *keypath])}]")
+
+        schema_root = self._parent(root=True)
 
         hashes = super()._hash_files(*keypath,
                                      missing_ok=missing_ok,

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/tool.py

@@ -997,7 +997,7 @@ class Task(NamedSchema, PathSchema, DocsSchema):
                      open(stderr_file, 'w') as stderr_writer:
                     if stderr_file == stdout_file:
                         stderr_writer.close()
-                        stderr_writer = sys.stdout
+                        stderr_writer = stdout_writer
 
                     with contextlib.redirect_stderr(stderr_writer), \
                          contextlib.redirect_stdout(stdout_writer):
@@ -1009,6 +1009,8 @@ class Task(NamedSchema, PathSchema, DocsSchema):
             finally:
                 with sc_open(stdout_file) as stdout_reader, \
                      sc_open(stderr_file) as stderr_reader:
+                    if stdout_file == stderr_file:
+                        stderr_reader = None
                     read_stdio(stdout_reader, stderr_reader)
 
                 if resource:

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/tools/keplerformal/lec.py

@@ -37,7 +37,7 @@ class LECTask(Task):
         libcorners = scenario.get_libcorner(self.step, self.index)
         delay_model = self.project.get("asic", "delaymodel")
         for asiclib in self.project.get("asic", "asiclib"):
-            lib = self.project.get("library", asiclib, field="schema")
+            lib = self.project.get_library(asiclib)
             for corner in libcorners:
                 if not lib.valid("asic", "libcornerfileset", corner, delay_model):
                     continue
@@ -64,7 +64,7 @@ class LECTask(Task):
             libcorners = scenario.get_libcorner(self.step, self.index)
             delay_model = self.project.get("asic", "delaymodel")
             for asiclib in self.project.get("asic", "asiclib"):
-                lib = self.project.get("library", asiclib, field="schema")
+                lib = self.project.get_library(asiclib)
                 for corner in libcorners:
                     if not lib.valid("asic", "libcornerfileset", corner, delay_model):
                         continue

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/tools/klayout/export.py

@@ -98,7 +98,7 @@ class ExportTask(KLayoutTask, ScreenshotParams):
                 lib_requires_stream = False
 
             req_set = False
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             for s in sc_stream_order:
                 for fileset in libobj.get("asic", "aprfileset"):
                     if libobj.valid("fileset", fileset, "file", s):

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/tools/openroad/_apr.py

@@ -1218,6 +1218,10 @@ class APRTask(OpenROADTask):
                            "used to indicate if global routing information should be loaded",
                            defvalue=False)
 
+        self.add_parameter("load_sdcs", "bool",
+                           "used to indicate if SDC files should be loaded before APR",
+                           defvalue=True)
+
         self.add_parameter("global_connect_fileset", "[(str,str)]",
                            "list of libraries and filesets to generate connects from")
 
@@ -1264,6 +1268,18 @@ class APRTask(OpenROADTask):
         """
         self.set("var", "ord_heatmap_bins", (x, y), step=step, index=index)
 
+    def set_openroad_loadsdcs(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None) -> None:
+        """
+        Enables or disables loading SDC files before APR.
+
+        Args:
+            enable: True to load SDC files, False to disable.
+            step: The specific step to apply this configuration to.
+            index: The specific index to apply this configuration to.
+        """
+        self.set("var", "load_sdcs", enable, step=step, index=index)
+
     def set_openroad_powercorner(self, corner: str,
                                  step: Optional[str] = None, index: Optional[str] = None) -> None:
         """
@@ -1334,6 +1350,7 @@ class APRTask(OpenROADTask):
         self.add_required_key("var", "ord_enable_images")
         self.add_required_key("var", "ord_heatmap_bins")
         self.add_required_key("var", "load_grt_setup")
+        self.add_required_key("var", "load_sdcs")
 
         if not self.get("var", "global_connect_fileset"):
             self.__import_globalconnect_filesets()
@@ -1346,9 +1363,20 @@ class APRTask(OpenROADTask):
         libcorners = set()
         for scenario in self.project.constraint.timing.get_scenario().values():
             libcorners.update(scenario.get_libcorner(self.step, self.index))
+            self.add_required_key(scenario, "pexcorner")
+            self.add_required_key(scenario, "libcorner")
+            if scenario.get_check(self.step, self.index):
+                self.add_required_key(scenario, "check")
+            mode = scenario.get_mode(self.step, self.index)
+            if mode:
+                self.add_required_key(scenario, "mode")
+                if self.get("var", "load_sdcs"):
+                    mode_obj = self.project.constraint.timing.get_mode(mode)
+                    self.add_required_key(mode_obj, "sdcfileset")
+
         delay_model = self.project.get("asic", "delaymodel")
         for asiclib in self.project.get("asic", "asiclib"):
-            lib = self.project.get("library", asiclib, field="schema")
+            lib = self.project.get_library(asiclib)
             for corner in libcorners:
                 if not lib.valid("asic", "libcornerfileset", corner, delay_model):
                     continue
@@ -1362,24 +1390,53 @@ class APRTask(OpenROADTask):
 
     def __import_globalconnect_filesets(self):
         for lib in self.project.get("asic", "asiclib"):
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             if libobj.valid("tool", "openroad", "global_connect_fileset"):
                 for fileset in libobj.get("tool", "openroad", "global_connect_fileset"):
                     self.add_openroad_globalconnectfileset(lib, fileset)
 
     def _set_reports(self, task_reports: List[str]):
-        self.set("var", "reports", set(task_reports).difference(self.get("var", "skip_reports")))
+        skip_reports = set(self.get("var", "skip_reports"))
+
+        if not self.get("var", "load_sdcs"):
+            skip_reports.update((
+                "setup",
+                "hold",
+                "unconstrained",
+                "clock_skew",
+                "fmax",
+                "check_setup",
+                "clock_placement",
+                "clock_trees"))
+
+        self.set("var", "reports", set(task_reports).difference(skip_reports))
 
         if "power" in self.get("var", "reports"):
             self.add_required_key("var", "power_corner")
 
     def _add_pnr_inputs(self):
-        if f"{self.design_topmodule}.sdc" in self.get_files_from_input_nodes():
-            self.add_input_file(ext="sdc")
-        else:
-            for lib, fileset in self.project.get_filesets():
-                if lib.has_file(fileset=fileset, filetype="sdc"):
-                    self.add_required_key(lib, "fileset", fileset, "file", "sdc")
+        if self.get("var", "load_sdcs"):
+            if f"{self.design_topmodule}.sdc" in self.get_files_from_input_nodes():
+                self.add_input_file(ext="sdc")
+            else:
+                for lib, fileset in self.project.get_filesets():
+                    if lib.has_file(fileset=fileset, filetype="sdc"):
+                        self.add_required_key(lib, "fileset", fileset, "file", "sdc")
+
+                modes = set()
+                for scenario in self.project.constraint.timing.get_scenario().values():
+                    mode = scenario.get_mode(self.step, self.index)
+                    if mode:
+                        modes.add(mode)
+                        self.add_required_key(scenario, "mode")
+                        mode_obj = self.project.constraint.timing.get_mode(mode)
+                        self.add_required_key(mode_obj, "sdcfileset")
+
+                for mode in modes:
+                    mode_obj = self.project.constraint.timing.get_mode(mode)
+                    for lib, fileset in mode_obj.get_sdcfileset():
+                        libobj = self.project.get_library(lib)
+                        self.add_required_key(libobj, "fileset", fileset, "file", "sdc")
 
         if f"{self.design_topmodule}.odb" in self.get_files_from_input_nodes():
             self.add_input_file(ext="odb")
@@ -1389,14 +1446,15 @@ class APRTask(OpenROADTask):
             pass
 
     def _add_pnr_outputs(self):
-        self.add_output_file(ext="sdc")
+        if self.get("var", "load_sdcs"):
+            self.add_output_file(ext="sdc")
         self.add_output_file(ext="vg")
         self.add_output_file(ext="lec.vg")
         self.add_output_file(ext="def")
         self.add_output_file(ext="odb")
 
         for lib in self.project.get("asic", "asiclib"):
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             for celltype in ["decap", "tie", "filler", "tap", "endcap", "antenna", "physicalonly"]:
                 if libobj.valid("asic", "cells", celltype) and \
                         libobj.get("asic", "cells", celltype):

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/tools/openroad/power_grid.py

@@ -94,7 +94,7 @@ class PowerGridTask(APRTask, OpenROADSTAParameter, OpenROADPSMParameter):
 
     def __import_pdn_filesets(self):
         for lib in self.project.get("asic", "asiclib"):
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             if libobj.valid("tool", "openroad", "power_grid_fileset"):
                 for fileset in libobj.get("tool", "openroad", "power_grid_fileset"):
                     self.add_openroad_powergridfileset(lib, fileset)

siliconcompiler-0.36.2/siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl

@@ -0,0 +1,25 @@
+###############################
+# Read timing constraints
+###############################
+
+if { [sc_cfg_tool_task_get var load_sdcs] } {
+    if { [file exists "inputs/${sc_topmodule}.sdc"] } {
+        set sdc "inputs/${sc_topmodule}.sdc"
+        puts "Reading SDC: ${sdc}"
+        read_sdc $sdc
+    } else {
+        set sdcs [sc_cfg_get_fileset $sc_designlib [sc_cfg_get option fileset] sdc]
+        if { [llength $sdcs] > 0 } {
+            foreach sdc $sdcs {
+                puts "Reading SDC: ${sdc}"
+                read_sdc $sdc
+            }
+        } else {
+            # fall back on default auto generated constraints file
+            set sdc [sc_cfg_tool_task_get var opensta_generic_sdc]
+            puts "Reading SDC: ${sdc}"
+            utl::warn FLW 1 "Defaulting back to default SDC"
+            read_sdc "${sdc}"
+        }
+    }
+}

siliconcompiler-0.36.2/siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl

@@ -0,0 +1,3 @@
+if { [sc_cfg_tool_task_get var load_sdcs] } {
+    write_sdc "outputs/${sc_topmodule}.sdc"
+}

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/tools/vpr/__init__.py

@@ -273,7 +273,7 @@ class VPRTask(Task):
                 self.add_required_key(lib, "fileset", fileset, "file", "sdc")
                 self.set("var", "enable_timing_analysis", True)
 
-        fpga = self.project.get("library", self.project.get("fpga", "device"), field="schema")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
         self.add_required_key(fpga, "tool", "vpr", "devicecode")
         self.add_required_key(fpga, "tool", "vpr", "clock_model")
         self.add_required_key(fpga, "tool", "vpr", "archfile")
@@ -287,7 +287,7 @@ class VPRTask(Task):
     def runtime_options(self):
         options = super().runtime_options()
 
-        fpga = self.project.get("library", self.project.get("fpga", "device"), field="schema")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         options.extend(["--device", fpga.get("tool", "vpr", "devicecode")])
 
@@ -393,17 +393,17 @@ class VPRTask(Task):
         for report in glob.glob("*.rpt"):
             shutil.move(report, 'reports')
 
-        fpga = self.project.get("fpga", "device")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         dff_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "registers"):
-            dff_cells = self.project.get("library", fpga, "tool", "yosys", "registers")
+        if fpga.valid("tool", "yosys", "registers"):
+            dff_cells = fpga.get("tool", "yosys", "registers")
         brams_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "brams"):
-            brams_cells = self.project.get("library", fpga, "tool", "yosys", "brams")
+        if fpga.valid("tool", "yosys", "brams"):
+            brams_cells = fpga.get("tool", "yosys", "brams")
         dsps_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "dsps"):
-            dsps_cells = self.project.get("library", fpga, "tool", "yosys", "dsps")
+        if fpga.valid("tool", "yosys", "dsps"):
+            dsps_cells = fpga.get("tool", "yosys", "dsps")
 
         stat_extract = re.compile(r'  \s*(.*)\s*:\s*([0-9]+)')
         lut_match = re.compile(r'([0-9]+)-LUT')

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/tools/vpr/place.py

@@ -48,8 +48,7 @@ class PlaceTask(VPRTask):
             if files:
                 pcf_file = files[0]
 
-                fpga = self.project.get("library", self.project.get("fpga", "device"),
-                                        field="schema")
+                fpga = self.project.get_library(self.project.get("fpga", "device"))
                 map_file = fpga.find_files("tool", "vpr", "constraintsmap")
 
                 constraints_map = load_constraints_map(map_file)

{siliconcompiler-0.36.1 → siliconcompiler-0.36.2}/siliconcompiler/tools/yosys/syn_asic.py

@@ -39,7 +39,7 @@ class _ASICTask(ASICTask, YosysTask):
 
         delaymodel = self.project.get("asic", "delaymodel")
         for lib in self.project.get("asic", "asiclib"):
-            lib_obj = self.project.get("library", lib, field="schema")
+            lib_obj = self.project.get_library(lib)
             for corner in self.get("var", "synthesis_corner"):
                 if lib_obj.get("asic", "libcornerfileset", corner, delaymodel):
                     self.add_required_key(lib_obj, "asic", "libcornerfileset", corner, delaymodel)
@@ -81,7 +81,7 @@ class _ASICTask(ASICTask, YosysTask):
         # Generate synthesis_libraries for Yosys use
         fileset_map = []
         for lib in self.project.get("asic", "asiclib"):
-            lib_obj = self.project.get("library", lib, field="schema")
+            lib_obj = self.project.get_library(lib)
             for corner in self.get("var", "synthesis_corner"):
                 for fileset in lib_obj.get("asic", "libcornerfileset", corner, delaymodel):
                     fileset_map.append((lib_obj, fileset))
@@ -696,7 +696,7 @@ class ASICSynthesis(_ASICTask, YosysTask):
         self.add_output_file(ext="vg", clobber=True)
         self.add_output_file(ext="netlist.json")
 
-        mainlib = self.project.get("library", self.project.get("asic", "mainlib"), field="schema")
+        mainlib = self.project.get_library(self.project.get("asic", "mainlib"))
 
         if self.get('var', 'abc_constraint_driver') is not None:
             self.add_required_key("var", "abc_constraint_driver")
@@ -799,7 +799,7 @@ class ASICSynthesis(_ASICTask, YosysTask):
 
     def _get_clock_period(self):
         mainlib = self.project.get("asic", "mainlib")
-        clock_units_multiplier = self.project.get("library", mainlib, field="schema").get(
+        clock_units_multiplier = self.project.get_library(mainlib).get(
             "tool", "yosys", "abc_clock_multiplier") / 1000
 
         _, period = self.get_clock()