siliconcompiler 0.36.0__tar.gz → 0.36.1__tar.gz

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/Changes

@@ -8,6 +8,18 @@ The changes in each SiliconCompiler release version are described below. Commit
 version shown in (). Where applicable, the contributors that suggested a given
 feature are shown in [].
 
+SiliconCompiler 0.36.1 (2026-01-10)
+=========================================
+
+**Minor:**
+
+ * Expanded parameter setters for tasks.
+
+ * Tools:
+
+  * openroad: fixed pin constraints handling, added support for editing halos.
+
+
 SiliconCompiler 0.36.0 (2026-01-06)
 =========================================
 

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: siliconcompiler
-Version: 0.36.0
+Version: 0.36.1
 Summary: A compiler framework that automates translation from source code to silicon.
 Author: Zero ASIC
 License: Apache License 2.0
@@ -31,7 +31,7 @@ Requires-Dist: docker<8.0.0,>=7.1.0
 Requires-Dist: fastjsonschema<2.22.0,>=2.20.0
 Requires-Dist: graphviz<0.22,>=0.20
 Requires-Dist: orjson<4,>=3.11.0
-Requires-Dist: packaging<25,>=21.3
+Requires-Dist: packaging<26,>=21.3
 Requires-Dist: requests<2.33.0,>=2.32.0
 Requires-Dist: Pillow<11.4.0,>=11.3.0
 Requires-Dist: PyYAML<7.0.0,>=6.0.0

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/pyproject.toml

@@ -36,7 +36,7 @@ dependencies = [
     "fastjsonschema >= 2.20.0, < 2.22.0",
     "graphviz >= 0.20, < 0.22",
     "orjson >= 3.11.0, < 4",
-    "packaging >= 21.3, < 25",
+    "packaging >= 21.3, < 26",
     "requests >= 2.32.0, < 2.33.0",
     "Pillow >= 11.3.0, < 11.4.0",
     "PyYAML >= 6.0.0, < 7.0.0",

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.36.0'
+version = '0.36.1'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/siliconcompiler/tools/chisel/convert.py

@@ -4,6 +4,8 @@ import glob
 
 import os.path
 
+from typing import Optional, List, Union
+
 from siliconcompiler import sc_open
 
 from siliconcompiler import Task
@@ -18,6 +20,48 @@ class ConvertTask(Task):
         self.add_parameter("targetdir", "str", "Output target directory name",
                            defvalue="chisel-output")
 
+    def set_chisel_application(self, application: str,
+                               step: Optional[str] = None, index: Optional[str] = None) -> None:
+        """
+        Sets the application name of the chisel program.
+
+        Args:
+            application (str): The application name.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "application", application, step=step, index=index)
+
+    def add_chisel_argument(self, argument: Union[str, List[str]],
+                            step: Optional[str] = None, index: Optional[str] = None,
+                            clobber: bool = False) -> None:
+        """
+        Adds arguments for the chisel build.
+
+        Args:
+            argument (Union[str, List[str]]): The argument(s) to add.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "argument", argument, step=step, index=index)
+        else:
+            self.add("var", "argument", argument, step=step, index=index)
+
+    def set_chisel_targetdir(self, targetdir: str,
+                             step: Optional[str] = None,
+                             index: Optional[str] = None) -> None:
+        """
+        Sets the output target directory name.
+
+        Args:
+            targetdir (str): The target directory name.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "targetdir", targetdir, step=step, index=index)
+
     def tool(self):
         return "chisel"
 

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/siliconcompiler/tools/ghdl/convert.py

@@ -1,3 +1,4 @@
+from typing import Optional
 from siliconcompiler import Task
 
 
@@ -12,10 +13,44 @@ class ConvertTask(Task):
         self.add_parameter("use_latches", "bool", "add the --latches flag", defvalue=False)
 
     def set_usefsynopsys(self, value: bool):
-        self.set("var", "use_fsynopsys", value)
+        """Deprecated: use set_ghdl_usefsynopsys instead."""
+        import warnings
+        warnings.warn("set_usefsynopsys is deprecated, use set_ghdl_usefsynopsys instead.",
+                      DeprecationWarning, stacklevel=2)
+        self.set_ghdl_usefsynopsys(value)
+
+    def set_ghdl_usefsynopsys(self, value: bool,
+                              step: Optional[str] = None,
+                              index: Optional[str] = None):
+        """
+        Adds the -fsynopsys flag to the GHDL command.
+
+        Args:
+            value (bool): Whether to add the flag.
+            step (str, optional): The step to associate with this setting.
+            index (str, optional): The index to associate with this setting.
+        """
+        self.set("var", "use_fsynopsys", value, step=step, index=index)
 
     def set_uselatches(self, value: bool):
-        self.set("var", "use_latches", value)
+        """Deprecated: use set_ghdl_uselatches instead."""
+        import warnings
+        warnings.warn("set_uselatches is deprecated, use set_ghdl_uselatches instead.",
+                      DeprecationWarning, stacklevel=2)
+        self.set_ghdl_uselatches(value)
+
+    def set_ghdl_uselatches(self, value: bool,
+                            step: Optional[str] = None,
+                            index: Optional[str] = None):
+        """
+        Adds the --latches flag to the GHDL command.
+
+        Args:
+            value (bool): Whether to add the flag.
+            step (str, optional): The step to associate with this setting.
+            index (str, optional): The index to associate with this setting.
+        """
+        self.set("var", "use_latches", value, step=step, index=index)
 
     def tool(self):
         return "ghdl"

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/siliconcompiler/tools/icarus/compile.py

@@ -1,3 +1,4 @@
+from typing import Optional
 from siliconcompiler import Task
 
 
@@ -14,6 +15,19 @@ class CompileTask(Task):
                            'See the corresponding "-g" flags in the Icarus manual for more "'
                            '"information.')
 
+    def set_icarus_veriloggeneration(self, gen: str,
+                                     step: Optional[str] = None,
+                                     index: Optional[str] = None):
+        """
+        Sets the Verilog language generation for Icarus.
+
+        Args:
+            gen (str): The Verilog generation to use.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "verilog_generation", gen, step=step, index=index)
+
     def tool(self):
         return "icarus"
 

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/siliconcompiler/tools/klayout/drc.py

@@ -2,6 +2,7 @@ import shlex
 
 import os.path
 
+from typing import Optional
 from xml.etree import ElementTree
 
 from siliconcompiler.tools.klayout import KLayoutTask
@@ -14,6 +15,19 @@ class DRCTask(KLayoutTask):
 
         self.add_parameter("drc_name", "str", "name of the DRC deck to run")
 
+    def set_klayout_drcname(self, name: str,
+                            step: Optional[str] = None,
+                            index: Optional[str] = None):
+        """
+        Sets the name of the DRC deck to run.
+
+        Args:
+            name (str): The name of the DRC deck.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "drc_name", name, step=step, index=index)
+
     def task(self):
         return "drc"
 

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/siliconcompiler/tools/klayout/export.py

@@ -1,3 +1,4 @@
+from typing import Optional
 from siliconcompiler.tools.klayout import KLayoutTask
 from siliconcompiler.tools.klayout.screenshot import ScreenshotParams
 
@@ -13,6 +14,45 @@ class ExportTask(KLayoutTask, ScreenshotParams):
                            "true/false: true will cause KLayout to generate a screenshot of "
                            "the layout", defvalue=True)
 
+    def set_klayout_stream(self, stream: str,
+                           step: Optional[str] = None,
+                           index: Optional[str] = None):
+        """
+        Sets the stream format for generation.
+
+        Args:
+            stream (str): The stream format to use.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "stream", stream, step=step, index=index)
+
+    def set_klayout_timestamps(self, enable: bool,
+                               step: Optional[str] = None,
+                               index: Optional[str] = None):
+        """
+        Enables or disables exporting GDSII with timestamps.
+
+        Args:
+            enable (bool): Whether to enable timestamps.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "timestamps", enable, step=step, index=index)
+
+    def set_klayout_screenshot(self, enable: bool,
+                               step: Optional[str] = None,
+                               index: Optional[str] = None):
+        """
+        Enables or disables generating a screenshot of the layout.
+
+        Args:
+            enable (bool): Whether to generate a screenshot.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "screenshot", enable, step=step, index=index)
+
     def task(self):
         return "export"
 

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/siliconcompiler/tools/klayout/operations.py

@@ -1,3 +1,4 @@
+from typing import Optional, List, Tuple
 from siliconcompiler.tools.klayout import KLayoutTask
 
 
@@ -15,6 +16,45 @@ class OperationsTask(KLayoutTask):
         self.add_parameter("timestamps", "bool",
                            "Export GDSII with timestamps", defvalue=True)
 
+    def set_klayout_operations(self, operations: List[Tuple[str, str]],
+                               step: Optional[str] = None,
+                               index: Optional[str] = None):
+        """
+        Sets the list of operations to perform.
+
+        Args:
+            operations (List[Tuple[str, str]]): The list of operations.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "operations", operations, step=step, index=index)
+
+    def set_klayout_stream(self, stream: str,
+                           step: Optional[str] = None,
+                           index: Optional[str] = None):
+        """
+        Sets the stream format for generation.
+
+        Args:
+            stream (str): The stream format to use.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "stream", stream, step=step, index=index)
+
+    def set_klayout_timestamps(self, enable: bool,
+                               step: Optional[str] = None,
+                               index: Optional[str] = None):
+        """
+        Enables or disables exporting GDSII with timestamps.
+
+        Args:
+            enable (bool): Whether to enable timestamps.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "timestamps", enable, step=step, index=index)
+
     def task(self):
         return "operations"
 

{siliconcompiler-0.36.0 → siliconcompiler-0.36.1}/siliconcompiler/tools/openroad/__init__.py

@@ -51,6 +51,8 @@ class OpenROADPDK(PDK):
                                    "router and only uses the specified tech vias")
         self.define_tool_parameter("openroad", "drt_repair_pdn_vias", "str",
                                    "Via layer to repair after detailed routing")
+        self.define_tool_parameter("openroad", "drt_via_in_pin_layers", "(str,str)",
+                                   "Tuple of layers for vias in pin layers")
 
     def set_openroad_rclayers(self, signal: str = None, clock: str = None):
         """
@@ -155,6 +157,15 @@ class OpenROADPDK(PDK):
         """
         self.set("tool", "openroad", "drt_repair_pdn_vias", layer)
 
+    def set_openroad_detailedrouteviainpinlayers(self, layer1: str, layer2: str):
+        """Sets the via layers used in pin layers during detailed routing.
+
+        Args:
+            layer1 (str): The first layer for vias in pin layers.
+            layer2 (str): The second layer for vias in pin layers.
+        """
+        self.set("tool", "openroad", "drt_via_in_pin_layers", (layer1, layer2))
+
 
 class OpenROADStdCellLibrary(StdCellLibrary):
     """