siliconcompiler 0.35.3__tar.gz → 0.36.0__tar.gz

{siliconcompiler-0.35.3 → siliconcompiler-0.36.0}/Changes

@@ -8,6 +8,53 @@ The changes in each SiliconCompiler release version are described below. Commit
 version shown in (). Where applicable, the contributors that suggested a given
 feature are shown in [].
 
+SiliconCompiler 0.36.0 (2026-01-06)
+=========================================
+
+**Major:**
+
+ * Changed schema to better handle timing constraints, by splitting out mode specific information from the scenarios.
+
+**Minor:**
+
+ * Reimplemented flowgraph rendering with file IO information.
+ * Fixed tool version checking to support threaded runs.
+ * Reworked use of pipes during execution to avoid creating more pipes than needed.
+ * Fixed flowgraph IO checks to only check required files.
+
+ * Tools:
+
+  * klayout: fixed handling of GDS generation when foreign is specified in lef.
+  * openroad: added support for halo constraints.
+  * kelper-formal: added initial support for LEC with kepler-formal.
+
+
+SiliconCompiler 0.35.4 (2025-12-08)
+=========================================
+
+**Major:**
+
+ * Added support for `settings.json` to allow users to set defaults and persistent options and controls for slurm nodes.
+
+**Minor:**
+
+ * Added limit to the number of warnings/errors that will be printed to the terminal.
+ * Added `copy_*` methods to timing constraints to better support building multiple modes.
+ * Added support for flow to run collection if the specific node requires it.
+ * Added check for conflicting flow tasks and generate an error if one is found.
+ * Added Python 3.14 to testing matrix.
+ * Improved logging to help identify specific log files.
+ * Ensured data is cleaned up when a failure occurs while downloading remote data.
+ * Corrected missing history when failures occur in the flow.
+ * Fixed bug causing skipped tasks to not get re-executed when restarting flow.
+
+ * Tools:
+
+  * yosys: added warning to indicate that slang was not found, added controls for undefined signals, and buffer insertion.
+  * openroad: added support for using bmaps to place bumps, added IR drop task to provide better "what-if" analysis.
+  * vivado: added support for pre/post scripts.
+
+
 SiliconCompiler 0.35.3 (2025-11-10)
 =========================================
 

{siliconcompiler-0.35.3 → siliconcompiler-0.36.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: siliconcompiler
-Version: 0.35.3
+Version: 0.36.0
 Summary: A compiler framework that automates translation from source code to silicon.
 Author: Zero ASIC
 License: Apache License 2.0
@@ -16,6 +16,7 @@ Classifier: Programming Language :: Python :: 3.10
 Classifier: Programming Language :: Python :: 3.11
 Classifier: Programming Language :: Python :: 3.12
 Classifier: Programming Language :: Python :: 3.13
+Classifier: Programming Language :: Python :: 3.14
 Classifier: Operating System :: POSIX :: Linux
 Classifier: Operating System :: MacOS
 Classifier: Operating System :: Microsoft :: Windows
@@ -37,7 +38,7 @@ Requires-Dist: PyYAML<7.0.0,>=6.0.0
 Requires-Dist: GitPython<3.2,>=3.1.44
 Requires-Dist: PyGithub<2.9.0,>=2.8.0
 Requires-Dist: urllib3>=1.26.0
-Requires-Dist: lambdapdk>=0.2.4
+Requires-Dist: lambdapdk>=0.2.6
 Requires-Dist: fasteners>=0.20
 Requires-Dist: pandas>=1.1.5
 Requires-Dist: psutil>=5.8.0
@@ -60,7 +61,7 @@ Requires-Dist: responses==0.25.8; extra == "test"
 Requires-Dist: PyVirtualDisplay==3.0; extra == "test"
 Provides-Extra: lint
 Requires-Dist: flake8==7.3.0; extra == "lint"
-Requires-Dist: tclint==0.6.1; extra == "lint"
+Requires-Dist: tclint==0.7.0; extra == "lint"
 Requires-Dist: codespell==2.4.1; extra == "lint"
 Provides-Extra: docs
 Requires-Dist: Sphinx<8.3,>=7.4; extra == "docs"
@@ -102,7 +103,7 @@ SiliconCompiler is a modular hardware build system ("make for silicon"). The pro
 # Getting Started
 
 SiliconCompiler is available as wheel packages on PyPI for macOS, Windows and
-Linux platforms. For working Python 3.9-3.13 environment, just use pip.
+Linux platforms. For working Python 3.9-3.14 environment, just use pip.
 
 ```sh
 pip install --upgrade siliconcompiler

{siliconcompiler-0.35.3 → siliconcompiler-0.36.0}/README.md

@@ -29,7 +29,7 @@ SiliconCompiler is a modular hardware build system ("make for silicon"). The pro
 # Getting Started
 
 SiliconCompiler is available as wheel packages on PyPI for macOS, Windows and
-Linux platforms. For working Python 3.9-3.13 environment, just use pip.
+Linux platforms. For working Python 3.9-3.14 environment, just use pip.
 
 ```sh
 pip install --upgrade siliconcompiler

{siliconcompiler-0.35.3 → siliconcompiler-0.36.0}/pyproject.toml

@@ -21,6 +21,7 @@ classifiers = [
     "Programming Language :: Python :: 3.11",
     "Programming Language :: Python :: 3.12",
     "Programming Language :: Python :: 3.13",
+    "Programming Language :: Python :: 3.14",
     "Operating System :: POSIX :: Linux",
     "Operating System :: MacOS",
     "Operating System :: Microsoft :: Windows",
@@ -44,7 +45,7 @@ dependencies = [
     "PyGithub >= 2.8.0, < 2.9.0",
     "urllib3 >= 1.26.0", # Required for PyGithub
 
-    "lambdapdk >= 0.2.4",
+    "lambdapdk >= 0.2.6",
 
     "fasteners >= 0.20",
     "pandas >= 1.1.5",
@@ -111,7 +112,7 @@ test = [
 ]
 lint = [
     "flake8 == 7.3.0",
-    "tclint == 0.6.1",
+    "tclint == 0.7.0",
     "codespell == 2.4.1"
 ]
 docs = [
@@ -156,7 +157,10 @@ filterwarnings = [
     'ignore:The distutils\.sysconfig module is deprecated, use sysconfig instead',
     'ignore:The distutils package is deprecated and slated for removal in Python 3\.12',
     'ignore:Creating a LegacyVersion has been deprecated and will be removed in the next major release',
-    'ignore:.* is multi-threaded, use of fork\(\) may lead to deadlocks in the child.:DeprecationWarning'
+    'ignore:.* is multi-threaded, use of fork\(\) may lead to deadlocks in the child.:DeprecationWarning',
+    'ignore:This function is deprecated and will be removed in a future version, use cls\.find_task instead:DeprecationWarning',
+    'ignore:This function is deprecated and will be removed in a future version, use TimingModeSchema instead:DeprecationWarning',
+    'ignore:Python 3\.14 will, by default, filter extracted tar archives and reject files or modify their metadata\. Use the filter argument to control this behavior\.:DeprecationWarning'
 ]
 
 [tool.tclint]
@@ -178,7 +182,7 @@ spaces-in-braces = true
 skip = '*/build/*,./docs/_build/*,*.json,*.xml,*.v,./siliconcompiler/data/templates/report/bootstrap.min.js,./tests/utils/test_utils.py,./tests/tools/data/klayout_pdk/interposer.drc'
 count = true
 quiet-level = 3
-ignore-words-list = 'synopsys,inout,subtile,FRAM,dffer,dffers'
+ignore-words-list = 'synopsys,inout,subtile,FRAM,dffer,dffers,thirdparty'
 
 [tool.check-wheel-contents]
 ignore = [

{siliconcompiler-0.35.3 → siliconcompiler-0.36.0}/siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.35.3'
+version = '0.36.0'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

{siliconcompiler-0.35.3 → siliconcompiler-0.36.0}/siliconcompiler/apps/sc_issue.py

@@ -72,6 +72,21 @@ To run a testcase, use:
     if not issue.get("cmdarg", "run"):
         project: Project = Project.from_manifest(filepath=issue.get("cmdarg", "cfg"))
 
+        # Determine abs path for build dir
+        builddir = project.option.get_builddir()
+        if isinstance(builddir, str) and not os.path.isabs(builddir):
+            builddirname = os.path.basename(builddir)
+            fullpath = os.path.dirname(os.path.abspath(issue.get("cmdarg", "cfg")))
+            while True:
+                if os.path.basename(fullpath) == builddirname:
+                    project.option.set_builddir(fullpath)
+                    break
+                parent = os.path.dirname(fullpath)
+                if parent == fullpath:
+                    # Reached filesystem root without finding a match
+                    break
+                fullpath = parent
+
         if issue.get("arg", "step"):
             project.set("arg", "step", issue.get("arg", "step"))
         if issue.get("arg", "index"):
@@ -143,8 +158,9 @@ To run a testcase, use:
 
         # Modify run environment to point to extracted files
         builddir_key = ['option', 'builddir']
-        new_builddir = f"{test_dir}/{project.get(*builddir_key)}"
-        project.logger.info(f"Changing {builddir_key} to '{new_builddir}'")
+        new_builddir = os.path.abspath(
+            os.path.join(test_dir, f"{os.path.basename(project.get(*builddir_key))}"))
+        project.logger.info(f"Changing [{','.join(builddir_key)}] to '{new_builddir}'")
         project.set(*builddir_key, new_builddir)
 
         # Run task

{siliconcompiler-0.35.3 → siliconcompiler-0.36.0}/siliconcompiler/checklist.py

@@ -6,6 +6,7 @@ from typing import Tuple, List, Optional, Union, Dict, Iterable
 from siliconcompiler.schema import NamedSchema, EditableSchema, Parameter, Scope, BaseSchema
 from siliconcompiler.schema.utils import trim
 from siliconcompiler import NodeStatus, utils
+from siliconcompiler.utils.paths import cwdirsafe
 
 
 class Criteria(NamedSchema):
@@ -328,7 +329,7 @@ class Checklist(NamedSchema):
 
         schema_root = self._parent(root=True)
         logger = getattr(schema_root, "logger", None)
-        cwd = getattr(schema_root, "_Project__cwd", os.getcwd())
+        cwd = cwdirsafe(schema_root)
 
         assert hasattr(schema_root, "history"), f"{schema_root}"
 

{siliconcompiler-0.35.3 → siliconcompiler-0.36.0}/siliconcompiler/constraints/__init__.py

@@ -1,5 +1,7 @@
 from siliconcompiler.schema import BaseSchema
 
+from siliconcompiler.constraints.timing_mode import TimingModeSchema
+
 from siliconcompiler.constraints.asic_timing import \
     ASICTimingConstraintSchema, ASICTimingScenarioSchema
 from siliconcompiler.constraints.asic_floorplan import ASICAreaConstraint
@@ -29,5 +31,6 @@ __all__ = [
     "ASICComponentConstraint",
     "ASICComponentConstraints",
     "FPGATimingConstraintSchema",
-    "FPGATimingScenarioSchema"
+    "FPGATimingScenarioSchema",
+    "TimingModeSchema"
 ]

{siliconcompiler-0.35.3 → siliconcompiler-0.36.0}/siliconcompiler/constraints/asic_component.py

@@ -1,4 +1,4 @@
-from typing import Tuple, Union
+from typing import Tuple, Union, Optional
 
 from siliconcompiler.schema import BaseSchema, NamedSchema, EditableSchema, Parameter, \
     PerNode, Scope
@@ -13,7 +13,7 @@ class ASICComponentConstraint(NamedSchema):
     keepout halo, and rotation.
     """
 
-    def __init__(self, name: str = None):
+    def __init__(self, name: Optional[str] = None):
         super().__init__()
         self.set_name(name)
 
@@ -113,7 +113,8 @@ class ASICComponentConstraint(NamedSchema):
                     270 deg ccw
                     """))
 
-    def set_placement(self, x: float, y: float, step: str = None, index: Union[str, int] = None):
+    def set_placement(self, x: float, y: float,
+                      step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the placement constraint for the component.
 
@@ -134,7 +135,8 @@ class ASICComponentConstraint(NamedSchema):
             raise TypeError("y must be a number")
         return self.set("placement", (x, y), step=step, index=index)
 
-    def get_placement(self, step: str = None, index: Union[str, int] = None) -> Tuple[float, float]:
+    def get_placement(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
+            -> Tuple[float, float]:
         """
         Retrieves the current placement constraint of the component.
 
@@ -148,7 +150,8 @@ class ASICComponentConstraint(NamedSchema):
         """
         return self.get("placement", step=step, index=index)
 
-    def set_partname(self, name: str, step: str = None, index: Union[str, int] = None):
+    def set_partname(self, name: str,
+                     step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the part name (cell name) constraint for the component.
 
@@ -165,7 +168,8 @@ class ASICComponentConstraint(NamedSchema):
             raise ValueError("a partname is required")
         return self.set("partname", name, step=step, index=index)
 
-    def get_partname(self, step: str = None, index: Union[str, int] = None) -> str:
+    def get_partname(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
+            -> str:
         """
         Retrieves the current part name (cell name) constraint of the component.
 
@@ -178,7 +182,8 @@ class ASICComponentConstraint(NamedSchema):
         """
         return self.get("partname", step=step, index=index)
 
-    def set_halo(self, x: float, y: float, step: str = None, index: Union[str, int] = None):
+    def set_halo(self, x: float, y: float,
+                 step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the placement keepout halo constraint around the component.
 
@@ -204,7 +209,8 @@ class ASICComponentConstraint(NamedSchema):
             raise ValueError("y must be a positive number")
         return self.set("halo", (x, y), step=step, index=index)
 
-    def get_halo(self, step: str = None, index: Union[str, int] = None) -> Tuple[float, float]:
+    def get_halo(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
+            -> Tuple[float, float]:
         """
         Retrieves the current placement keepout halo constraint of the component.
 
@@ -218,7 +224,8 @@ class ASICComponentConstraint(NamedSchema):
         """
         return self.get("halo", step=step, index=index)
 
-    def set_rotation(self, rotation: str, step: str = None, index: Union[str, int] = None):
+    def set_rotation(self, rotation: str,
+                     step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the rotation constraint for the component.
 
@@ -231,7 +238,8 @@ class ASICComponentConstraint(NamedSchema):
         """
         return self.set("rotation", rotation, step=step, index=index)
 
-    def get_rotation(self, step: str = None, index: Union[str, int] = None) -> str:
+    def get_rotation(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
+            -> str:
         """
         Retrieves the current rotation constraint of the component.
 
@@ -286,7 +294,7 @@ class ASICComponentConstraints(BaseSchema):
 
         EditableSchema(self).insert(component.name, component, clobber=True)
 
-    def get_component(self, component: str = None):
+    def get_component(self, component: Optional[str] = None):
         """
         Retrieves one or all component constraints from the configuration.
 
@@ -350,6 +358,36 @@ class ASICComponentConstraints(BaseSchema):
         self.add_component(constraint)
         return constraint
 
+    def copy_component(self, component: str, name: str, insert: bool = True) \
+            -> ASICComponentConstraint:
+        """
+        Copies an existing component constraint, renames it, and optionally adds it to the design.
+
+        This method retrieves the component constraint identified by ``component``, creates a
+        deep copy of it, and renames the copy to ``name``. If ``insert`` is True,
+        the new constraint is immediately added to the configuration.
+
+        Args:
+            component (str): The name of the existing component constraint to be copied.
+            name (str): The name to assign to the new copied constraint.
+            insert (bool, optional): Whether to add the newly created constraint
+                to the configuration. Defaults to True.
+
+        Returns:
+            ASICComponentConstraint: The newly created copy of the component constraint.
+
+        Raises:
+            LookupError: If the source component constraint specified by ``component`` does not
+                         exist.
+        """
+        constraint = EditableSchema(self.get_component(component)).copy()
+        EditableSchema(constraint).rename(name)
+        if insert:
+            if self.valid(name):
+                raise ValueError(f"{name} already exists")
+            self.add_component(constraint)
+        return constraint
+
     def remove_component(self, component: str) -> bool:
         """
         Removes a component constraint from the design configuration.

{siliconcompiler-0.35.3 → siliconcompiler-0.36.0}/siliconcompiler/constraints/asic_floorplan.py

@@ -1,4 +1,4 @@
-from typing import Union, List, Tuple
+from typing import Union, List, Tuple, Optional
 
 from siliconcompiler.schema import BaseSchema, EditableSchema, Parameter, PerNode, Scope
 
@@ -99,9 +99,9 @@ class ASICAreaConstraint(BaseSchema):
 
     def set_density(self,
                     density: float,
-                    aspectratio: float = None,
-                    coremargin: float = None,
-                    step: str = None, index: Union[str, int] = None):
+                    aspectratio: Optional[float] = None,
+                    coremargin: Optional[float] = None,
+                    step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the target layout density.
 
@@ -145,7 +145,8 @@ class ASICAreaConstraint(BaseSchema):
             params.append(self.set_coremargin(coremargin, step=step, index=index))
         return params
 
-    def get_density(self, step: str = None, index: Union[str, int] = None) -> float:
+    def get_density(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
+            -> float:
         """
         Retrieves the current target layout density.
 
@@ -162,7 +163,7 @@ class ASICAreaConstraint(BaseSchema):
 
     def set_aspectratio(self,
                         aspectratio: float,
-                        step: str = None, index: Union[str, int] = None):
+                        step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the layout aspect ratio.
 
@@ -192,8 +193,8 @@ class ASICAreaConstraint(BaseSchema):
 
         return self.set("aspectratio", aspectratio, step=step, index=index)
 
-    def get_aspectratio(self,
-                        step: str = None, index: Union[str, int] = None) -> float:
+    def get_aspectratio(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
+            -> float:
         """
         Retrieves the current layout aspect ratio.
 
@@ -210,7 +211,7 @@ class ASICAreaConstraint(BaseSchema):
 
     def set_coremargin(self,
                        coremargin: float,
-                       step: str = None, index: Union[str, int] = None):
+                       step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the core margin.
 
@@ -240,8 +241,8 @@ class ASICAreaConstraint(BaseSchema):
 
         return self.set("coremargin", coremargin, step=step, index=index)
 
-    def get_coremargin(self,
-                       step: str = None, index: Union[str, int] = None) -> float:
+    def get_coremargin(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
+            -> float:
         """
         Retrieves the current core margin.
 
@@ -259,8 +260,8 @@ class ASICAreaConstraint(BaseSchema):
     def set_diearea_rectangle(self,
                               height: float,
                               width: float,
-                              coremargin: Union[float, Tuple[float, float]] = None,
-                              step: str = None, index: Union[str, int] = None):
+                              coremargin: Optional[Union[float, Tuple[float, float]]] = None,
+                              step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the die area as a rectangle with its bottom-left corner at (0,0).
 
@@ -311,7 +312,7 @@ class ASICAreaConstraint(BaseSchema):
                                dieheight: float,
                                diewidth: float,
                                coremargin: Union[float, Tuple[float, float]],
-                               step: str = None, index: Union[str, int] = None):
+                               step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the core area as a rectangle within a die area, based on margins.
 
@@ -378,7 +379,7 @@ class ASICAreaConstraint(BaseSchema):
 
     def set_diearea(self,
                     points: List[Tuple[float, float]],
-                    step: str = None, index: Union[str, int] = None):
+                    step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the die area using a list of points defining its boundary.
 
@@ -396,8 +397,8 @@ class ASICAreaConstraint(BaseSchema):
         """
         return self.set("diearea", points, step=step, index=index)
 
-    def get_diearea(self,
-                    step: str = None, index: Union[str, int] = None) -> List[Tuple[float, float]]:
+    def get_diearea(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
+            -> List[Tuple[float, float]]:
         """
         Retrieves the current die area definition.
 
@@ -415,7 +416,7 @@ class ASICAreaConstraint(BaseSchema):
 
     def set_corearea(self,
                      points: List[Tuple[float, float]],
-                     step: str = None, index: Union[str, int] = None):
+                     step: Optional[str] = None, index: Optional[Union[str, int]] = None):
         """
         Sets the core area using a list of points defining its boundary.
 
@@ -432,8 +433,8 @@ class ASICAreaConstraint(BaseSchema):
         """
         return self.set("corearea", points, step=step, index=index)
 
-    def get_corearea(self,
-                     step: str = None, index: Union[str, int] = None) -> List[Tuple[float, float]]:
+    def get_corearea(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
+            -> List[Tuple[float, float]]:
         """
         Retrieves the current core area definition.
 
@@ -449,7 +450,8 @@ class ASICAreaConstraint(BaseSchema):
         """
         return self.get("corearea", step=step, index=index)
 
-    def calc_diearea(self, step: str = None, index: str = None) -> float:
+    def calc_diearea(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
+            -> float:
         '''Calculates the area of a rectilinear die.
 
         Uses the shoelace formula to calculate the design area from the (x,y)