siliconcompiler 0.29.1__tar.gz → 0.29.2__tar.gz

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/Changes

@@ -8,6 +8,23 @@ The changes in each SiliconCompiler release version are described below. Commit
 version shown in (). Where applicable, the contributors that suggested a given
 feature are shown in [].
 
+SiliconCompiler 0.29.2 (2025-01-16)
+=========================================
+
+**Major:**
+
+ * Added gtkwave show task to allow for vcd viewing.
+ * Removed enablement for conda-eda as this is no longer a supported project.
+
+**Minor:**
+
+ * Allow passing a file path to `.register_source` to make it easier to handle retive path to the current file.
+
+ * Tools:
+
+  * openroad: added support for mutli-bit flipflop mapping and initial support for scan chain insertion, correct pin ordering from constraints.
+
+
 SiliconCompiler 0.29.1 (2025-01-09)
 =========================================
 

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.2
 Name: siliconcompiler
-Version: 0.29.1
+Version: 0.29.2
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -46,7 +46,7 @@ Requires-Dist: fastjsonschema==2.21.1
 Requires-Dist: docker==7.1.0
 Requires-Dist: importlib_metadata; python_version < "3.10"
 Requires-Dist: sc-surelog==1.84.1
-Requires-Dist: orjson==3.10.13
+Requires-Dist: orjson==3.10.14
 Requires-Dist: streamlit==1.40.1; python_version <= "3.8"
 Requires-Dist: streamlit==1.41.1; python_version >= "3.9" and python_full_version != "3.9.7"
 Requires-Dist: streamlit_agraph==0.0.45; python_full_version != "3.9.7"
@@ -58,10 +58,10 @@ Requires-Dist: pytest==8.3.4; extra == "test"
 Requires-Dist: pytest-xdist==3.6.1; extra == "test"
 Requires-Dist: pytest-timeout==2.3.1; extra == "test"
 Requires-Dist: pytest-asyncio==0.24.0; python_version <= "3.8" and extra == "test"
-Requires-Dist: pytest-asyncio==0.25.1; python_version >= "3.9" and extra == "test"
+Requires-Dist: pytest-asyncio==0.25.2; python_version >= "3.9" and extra == "test"
 Requires-Dist: pytest-cov==5.0.0; python_version <= "3.8" and extra == "test"
 Requires-Dist: pytest-cov==6.0.0; python_version >= "3.9" and extra == "test"
-Requires-Dist: responses==0.25.3; extra == "test"
+Requires-Dist: responses==0.25.5; extra == "test"
 Requires-Dist: PyVirtualDisplay==3.0; extra == "test"
 Provides-Extra: lint
 Requires-Dist: flake8==7.1.1; extra == "lint"
@@ -78,7 +78,7 @@ Provides-Extra: examples
 Requires-Dist: migen==0.9.2; extra == "examples"
 Requires-Dist: lambdalib==0.3.2; extra == "examples"
 Provides-Extra: optimizer
-Requires-Dist: google-vizier[jax]==0.1.20; python_version >= "3.10" and extra == "optimizer"
+Requires-Dist: google-vizier[jax]==0.1.21; python_version >= "3.10" and extra == "optimizer"
 
 ![SiliconCompiler](https://raw.githubusercontent.com/siliconcompiler/siliconcompiler/main/docs/_static/sc_logo_with_text.png)
 

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/pyproject.toml

@@ -53,7 +53,7 @@ dependencies = [
     "docker == 7.1.0",
     "importlib_metadata; python_version < '3.10'",
     "sc-surelog == 1.84.1",
-    "orjson == 3.10.13",
+    "orjson == 3.10.14",
 
     # dashboard, streamlit does not support 3.9.7
     "streamlit == 1.40.1; python_version <= '3.8'",
@@ -106,10 +106,10 @@ test = [
     "pytest-xdist == 3.6.1",
     "pytest-timeout == 2.3.1",
     "pytest-asyncio == 0.24.0; python_version <= '3.8'",
-    "pytest-asyncio == 0.25.1; python_version >= '3.9'",
+    "pytest-asyncio == 0.25.2; python_version >= '3.9'",
     "pytest-cov == 5.0.0; python_version <= '3.8'",
     "pytest-cov == 6.0.0; python_version >= '3.9'",
-    "responses == 0.25.3",
+    "responses == 0.25.5",
     "PyVirtualDisplay == 3.0"
 ]
 lint = [
@@ -131,7 +131,7 @@ examples = [
     "lambdalib == 0.3.2"
 ]
 optimizer = [
-    "google-vizier[jax] == 0.1.20; python_version >= '3.10'"
+    "google-vizier[jax] == 0.1.21; python_version >= '3.10'"
 ]
 
 [tool.setuptools]

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.29.1'
+version = '0.29.2'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/apps/sc_install.py

@@ -126,7 +126,7 @@ def _recommended_tool_groups(tools):
     groups = {
         "asic": {"surelog", "sv2v", "yosys", "openroad", "klayout"},
         "fpga": {"surelog", "sv2v", "yosys", "vpr"},
-        "digital-simulation": {"verilator", "icarus"},
+        "digital-simulation": {"verilator", "icarus", "gtkwave"},
         "analog-simulation": {"xyce"}
     }
 

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/core.py

@@ -500,6 +500,9 @@ class Chip:
                     'dependency-caching-rebase')
         """
 
+        if os.path.isfile(path):
+            path = os.path.dirname(os.path.abspath(path))
+
         preset_path = self.get('package', 'source', name, 'path')
         preset_ref = self.get('package', 'source', name, 'ref')
         if preset_path and preset_path != path or preset_ref and preset_ref != ref:
@@ -3200,6 +3203,7 @@ class Chip:
         sc_step = self.get('arg', 'step')
         sc_index = self.get('arg', 'index')
         sc_job = self.get('option', 'jobname')
+        flow = self.get('option', 'flow')
 
         has_filename = filename is not None
         # Finding last layout if no argument specified
@@ -3210,14 +3214,15 @@ class Chip:
             if sc_step and sc_index:
                 search_nodes.append((sc_step, sc_index))
             elif sc_step:
-                for check_step, check_index in nodes_to_execute(self, self.get('option', 'flow')):
+                for check_step, check_index in nodes_to_execute(self, flow):
                     if sc_step == check_step:
                         search_nodes.append((check_step, check_index))
             else:
-                for nodes in _get_flowgraph_execution_order(self,
-                                                            self.get('option', 'flow'),
-                                                            reverse=True):
-                    search_nodes.extend(nodes)
+                if flow is not None:
+                    for nodes in _get_flowgraph_execution_order(self,
+                                                                flow,
+                                                                reverse=True):
+                        search_nodes.extend(nodes)
 
             for ext in self._showtools.keys():
                 if extension and extension != ext:

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/tools/__init__.py

@@ -5,6 +5,7 @@ from siliconcompiler.tools.chisel import chisel
 from siliconcompiler.tools.execute import execute
 from siliconcompiler.tools.genfasm import genfasm
 from siliconcompiler.tools.ghdl import ghdl
+from siliconcompiler.tools import gtkwave
 from siliconcompiler.tools.icarus import icarus
 from siliconcompiler.tools.icepack import icepack
 from siliconcompiler.tools.klayout import klayout
@@ -38,6 +39,7 @@ def get_tools():
             execute,
             genfasm,
             ghdl,
+            gtkwave,
             icarus,
             icepack,
             klayout,

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/tools/_common/asic.py

@@ -135,6 +135,76 @@ def set_tool_task_var(chip,
     return value
 
 
+def set_tool_task_lib_var(chip,
+                          param_key,
+                          default_value=None,
+                          schelp=None,
+                          option_key=None,
+                          lib_key=None):
+    '''
+    Set parameter from libraries -> option -> default_value
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    if schelp:
+        chip.set('tool', tool, 'task', task, 'var', param_key,
+                 schelp, field='help')
+
+    if not option_key:
+        option_key = f'{tool}_{param_key}'
+    require_key, value = pick_key(chip, [('option', 'var', option_key)], step=step, index=index)
+
+    def check_value(val):
+        if isinstance(val, (list, tuple, set)):
+            return len(val) > 0
+        return val is not None
+
+    if check_value(value):
+        chip.set('tool', tool, 'task', task, 'var', param_key, value,
+                 step=step, index=index, clobber=False)
+
+        if require_key:
+            chip.add('tool', tool, 'task', task, 'require',
+                     ','.join(('option', option_key)),
+                     step=step, index=index)
+
+        return value
+
+    # Add library key
+    if not lib_key:
+        lib_key = f'{tool}_{param_key}'
+    lib_keys = []
+    for lib in get_libraries(chip, 'logic'):
+        if chip.valid('library', lib, 'option', 'var', lib_key) and \
+           chip.get('library', lib, 'option', 'var', lib_key):
+            lib_keys.append(('library', lib, 'option', 'var', lib_key))
+
+    values = set()
+    for lib_key in lib_keys:
+        chip.add('tool', tool, 'task', task, 'require', ','.join(lib_key), step=step, index=index)
+
+        get_step = step
+        get_index = index
+
+        if chip.get(*lib_key, field='pernode') == 'never':
+            get_step = None
+            get_index = None
+
+        values.update(chip.get(*lib_key, step=get_step, index=get_index))
+
+    if check_value(values):
+        chip.set('tool', tool, 'task', task, 'var', param_key, values,
+                 step=step, index=index, clobber=False)
+
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', param_key]),
+                 step=step, index=index)
+
+    return values
+
+
 def get_tool_task_var(chip,
                       param_key,
                       option_key=None,

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/tools/_common/tcl/sc_pin_constraints.tcl

@@ -49,8 +49,8 @@ proc sc_collect_pin_constraints {
         }
 
         set side_pin_order []
-        dict for {index pin} $pins {
-            lappend side_pin_order {*}$pin
+        foreach index [lsort -integer [dict keys $pins]] {
+            lappend side_pin_order {*}[dict get $pins $index]
         }
 
         set pin_layer_ordering [dict create]

siliconcompiler-0.29.2/siliconcompiler/tools/gtkwave/__init__.py

@@ -0,0 +1,39 @@
+'''
+GTKWave is a fully featured GTK+ based wave viewer for Unix, Win32, and
+Mac OSX which reads LXT, LXT2, VZT, FST, and GHW files as well as standard
+Verilog VCD/EVCD files and allows their viewing.
+
+Documentation: https://gtkwave.github.io/gtkwave/
+
+Sources: https://github.com/gtkwave/gtkwave
+
+Installation: https://github.com/gtkwave/gtkwave
+'''
+
+from siliconcompiler.tools._common import \
+    get_tool_task
+
+
+def setup(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'exe', 'gtkwave')
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=v3.3.116', clobber=False)
+    chip.set('tool', tool, 'format', 'tcl', clobber=False)
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    # First line: GTKWave Analyzer v3.3.116 (w)1999-2023 BSI
+    return stdout.split()[2]
+
+
+def normalize_version(version):
+    if version[0] == 'v':
+        return version[1:]
+    return version

siliconcompiler-0.29.2/siliconcompiler/tools/gtkwave/scripts/sc_show.tcl

@@ -0,0 +1,34 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+##############################
+# Schema Adapter
+###############################
+
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_tool [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index tool]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+
+###############################
+# Source pre-scripts
+###############################
+
+if { [sc_cfg_tool_task_exists prescript] } {
+    foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+        puts "Sourcing pre script: ${sc_pre_script}"
+        source $sc_pre_script
+    }
+}
+
+###############################
+# Handle exit
+###############################
+
+if { [lindex [sc_cfg_tool_task_get {var} show_exit] 0] == "true" } {
+    exit
+}

siliconcompiler-0.29.2/siliconcompiler/tools/gtkwave/show.py

@@ -0,0 +1,70 @@
+import os
+
+from siliconcompiler.tools.gtkwave import setup as tool_setup
+from siliconcompiler.tools._common import \
+    add_require_input, get_tool_task, input_provides
+
+
+def setup(chip):
+    '''
+    Show a VCD file.
+    '''
+
+    tool_setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'refdir',
+             'tools/gtkwave/scripts',
+             step=step, index=index, package='siliconcompiler')
+
+    chip.set('tool', tool, 'task', task, 'refdir',
+             'tools/gtkwave/scripts',
+             step=step, index=index, package='siliconcompiler')
+    chip.set('tool', tool, 'task', task, 'script', 'sc_show.tcl',
+             step=step, index=index)
+
+    if f'{chip.top()}.vcd' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', f'{chip.top()}.vcd', step=step, index=index)
+    elif chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+            chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'var', 'show_filepath']),
+                 step=step, index=index)
+    else:
+        add_require_input(chip, 'input', 'waveform', 'vcd')
+
+    chip.set('tool', tool, 'task', task, 'var', 'show_exit', False,
+             step=step, index=index, clobber=False)
+
+
+def runtime_options(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    options = []
+
+    threads = chip.get('tool', tool, 'task', task, 'threads', step=step, index=index)
+    if threads:
+        options.append(f'--cpu={threads}')
+
+    script = chip.find_files('tool', tool, 'task', task, 'script', step=step, index=index)[0]
+    options.append(f'--script={script}')
+
+    if os.path.exists(f'inputs/{chip.top()}.vcd'):
+        dump = f'inputs/{chip.top()}.vcd'
+    elif chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+            chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        dump = chip.get('tool', tool, 'task', task, 'var', 'show_filepath',
+                        step=step, index=index)[0]
+    else:
+        dump = chip.find_files('input', 'waveform', 'vcd', step=step, index=index)[0]
+    options.append(f'--dump={dump}')
+
+    return options

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/tools/icarus/compile.py

@@ -75,6 +75,10 @@ def runtime_options(chip):
         cmdlist.append('-I' + value)
     for value in opts['define']:
         cmdlist.append('-D' + value)
+
+    # add siliconcompiler specific defines
+    cmdlist.append(f"-DSILICONCOMPILER_TRACE_FILE=\\\"reports/{design}.vcd\\\"")
+
     for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
         cmdlist.append('-f ' + value)
     for value in get_input_files(chip, 'input', 'rtl', 'netlist'):

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/tools/openroad/_apr.py

@@ -5,7 +5,7 @@ from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, add_common_file, \
     get_tool_task, record_metric
 from siliconcompiler.tools._common.asic import get_mainlib, set_tool_task_var, get_libraries, \
-    CellArea
+    CellArea, set_tool_task_lib_var
 from siliconcompiler.tools.openroad import setup as tool_setup
 
 
@@ -894,6 +894,14 @@ def define_ord_params(chip):
                       require=['key'],
                       schelp='number of Y bins to use for heatmap image generation')
 
+    set_tool_task_lib_var(chip, param_key='scan_chain_cells',
+                          default_value=None,
+                          schelp='cells to use for scan chain insertion')
+
+    set_tool_task_lib_var(chip, param_key='multibit_ff_cells',
+                          default_value=None,
+                          schelp='multibit flipflop cells')
+
 
 def define_ord_files(chip):
     step = chip.get('arg', 'step')

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/tools/openroad/global_placement.py

@@ -1,9 +1,11 @@
 from siliconcompiler.tools._common import get_tool_task
 from siliconcompiler.tools.openroad._apr import setup as apr_setup
-from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs, \
+    set_tool_task_var
 from siliconcompiler.tools.openroad._apr import \
     define_ord_params, define_sta_params, define_sdc_params, \
-    define_gpl_params, define_grt_params, define_rsz_params
+    define_gpl_params, define_grt_params, define_rsz_params, \
+    define_ppl_params
 from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
 from siliconcompiler.tools.openroad._apr import extract_metrics
 
@@ -35,6 +37,7 @@ def setup(chip):
     define_gpl_params(chip)
     define_grt_params(chip)
     define_rsz_params(chip)
+    define_ppl_params(chip)
 
     set_reports(chip, [
         'setup',
@@ -48,6 +51,24 @@ def setup(chip):
         'power_density'
     ])
 
+    set_tool_task_var(chip, param_key='enable_multibit_clustering',
+                      default_value=False,
+                      schelp='true/false, when true multibit clustering will be performed.')
+
+    set_tool_task_var(chip, param_key='enable_scan_chains',
+                      default_value=False,
+                      schelp='true/false, when true scan chains will be inserted.')
+
+    set_tool_task_var(chip, param_key='scan_enable_port_pattern',
+                      schelp='pattern of the scan chain enable port.',
+                      skip=['pdk', 'lib'])
+    set_tool_task_var(chip, param_key='scan_in_port_pattern',
+                      schelp='pattern of the scan chain in port.',
+                      skip=['pdk', 'lib'])
+    set_tool_task_var(chip, param_key='scan_out_port_pattern',
+                      schelp='pattern of the scan chain out port.',
+                      skip=['pdk', 'lib'])
+
 
 def pre_process(chip):
     define_ord_files(chip)

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl

@@ -17,7 +17,7 @@ source -echo "$sc_refdir/apr/preamble.tcl"
 ###############################
 
 if { [llength [all_clocks]] > 0 } {
-    sc_set_dont_use -clock
+    sc_set_dont_use -clock -report dont_use.clock_tree_synthesis
 
     # Clone clock tree inverters next to register loads
     # so cts does not try to buffer the inverted clocks.

siliconcompiler-0.29.2/siliconcompiler/tools/openroad/scripts/apr/sc_global_placement.tcl

@@ -0,0 +1,89 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+###############################
+# Task Preamble
+###############################
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+source -echo "$sc_refdir/apr/preamble.tcl"
+
+set dont_use_args []
+
+if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
+    lappend dont_use_args -scanchain
+}
+if { [lindex [sc_cfg_tool_task_get var enable_multibit_clustering] 0] == "true" } {
+    lappend dont_use_args -multibit
+}
+
+sc_set_dont_use {*}$dont_use_args -report dont_use.global_placement
+
+###############################
+# Scan Chain Preparation
+###############################
+
+if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
+    set dft_args []
+    if { [sc_cfg_tool_task_get var scan_in_port_pattern] != [] } {
+        lappend dft_args -scan_in_name_pattern \
+            [lindex [sc_cfg_tool_task_get var scan_in_port_pattern] 0]
+    }
+    if { [sc_cfg_tool_task_get var scan_out_port_pattern] != [] } {
+        lappend dft_args -scan_out_name_pattern \
+            [lindex [sc_cfg_tool_task_get var scan_out_port_pattern] 0]
+    }
+    if { [sc_cfg_tool_task_get var scan_enable_port_pattern] != [] } {
+        lappend dft_args -scan_enable_name_pattern \
+            [lindex [sc_cfg_tool_task_get var scan_enable_port_pattern] 0]
+    }
+
+    set_dft_config -clock_mixing clock_mix {*}$dft_args
+    tee -file reports/scan_chain_config.rpt {report_dft_config}
+    scan_replace
+}
+
+###############################
+# Perform multi-bit clustering
+###############################
+
+if { [lindex [sc_cfg_tool_task_get var enable_multibit_clustering] 0] == "true" } {
+    cluster_flops
+}
+
+###############################
+# Global Placement
+###############################
+
+sc_global_placement
+
+###############################
+# Scan Chain Finalize
+###############################
+
+if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
+    tee -file reports/scan_chain.rpt {preview_dft -verbose}
+    insert_dft
+
+    set new_ios [sc_get_unplaced_io_nets]
+    if { [llength $new_ios] > 0 } {
+        foreach net $new_ios {
+            utl::report "New IO net [$net getName]"
+        }
+        utl::warn FLW 1 "Scan chain generated new ports, rerunning pin placement"
+        sc_pin_placement
+    }
+}
+
+###############################
+# Task Postamble
+###############################
+
+sc_set_dont_use
+
+estimate_parasitics -placement
+
+source -echo "$sc_refdir/apr/postamble.tcl"

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl

@@ -28,6 +28,8 @@ estimate_parasitics -placement
 # Repair DRVs
 ###############################
 
+sc_set_dont_use -scanchain -multibit -report dont_use.repair_drv
+
 set repair_design_args []
 
 set rsz_cap_margin [lindex [sc_cfg_tool_task_get {var} rsz_cap_margin] 0]
@@ -43,6 +45,8 @@ repair_design \
     -verbose \
     {*}$repair_design_args
 
+sc_set_dont_use
+
 ###############################
 # Tie-off cell insertion
 ###############################

{siliconcompiler-0.29.1 → siliconcompiler-0.29.2}/siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl

@@ -34,6 +34,9 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
     # Setup Repair
     ###############################
 
+    # Enable ffs for resizing
+    sc_set_dont_use -scanchain -multibit -report dont_use.repair_timing.setup
+
     estimate_parasitics -placement
 
     repair_timing \
@@ -45,6 +48,9 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
         {*}$repair_timing_args
 
     sc_detailed_placement
+
+    # Restore dont use
+    sc_set_dont_use
 }
 
 if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
@@ -55,7 +61,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
     estimate_parasitics -placement
 
     # Enable hold cells
-    sc_set_dont_use -hold
+    sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.hold
 
     repair_timing \
         -hold \