siliconcompiler 0.28.8__tar.gz → 0.28.9__tar.gz

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/Changes

@@ -8,6 +8,20 @@ The changes in each SiliconCompiler release version are described below. Commit
 version shown in (). Where applicable, the contributors that suggested a given
 feature are shown in [].
 
+SiliconCompiler 0.28.9 (2024-11-27)
+=========================================
+
+**Minor:**
+
+ * Added option to limit size of emailed logs based on number of lines.
+ * Fixed handling of `find_files` in frontend tools
+ * Removed automatic error when FPGA is not loaded, as this can be handled by the tool/task drivers.
+
+ * Tools:
+
+  * vivado: update tool and task drivers to handle v2024.x and cleaned up output filenames.
+
+
 SiliconCompiler 0.28.8 (2024-11-20)
 =========================================
 

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.8
+Version: 0.28.9
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.28.8'
+version = '0.28.9'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/scheduler/send_messages.py

@@ -81,40 +81,44 @@ def send(chip, msg_type, step, index):
     msg['To'] = ", ".join(to)
     msg['X-Entity-Ref-ID'] = uuid.uuid4().hex  # keep emails from getting grouped
 
-    if msg_type == "summary":
-        layout_img = report_utils._find_summary_image(chip)
-        if layout_img and os.path.isfile(layout_img):
-            with open(layout_img, 'rb') as img_file:
-                img_attach = MIMEApplication(img_file.read())
-                img_attach.add_header('Content-Disposition',
-                                      'attachment',
-                                      filename=os.path.basename(layout_img))
-                msg.attach(img_attach)
-
-        nodes_to_execute = get_executed_nodes(chip, flow)
-        nodes, errors, metrics, metrics_unit, metrics_to_show, _ = \
-            report_utils._collect_data(chip, flow=flow, flowgraph_nodes=nodes_to_execute)
-
-        text_msg = get_file_template('email/summary.j2').render(
-            design=chip.design,
-            nodes=nodes,
-            errors=errors,
-            metrics=metrics,
-            metrics_unit=metrics_unit,
-            metric_keys=metrics_to_show)
-    else:
-        # Attach logs
-        for log in (f'sc_{step}{index}.log', f'{step}.log'):
-            log_file = f'{chip.getworkdir(step=step, index=index)}/{log}'
-            if os.path.exists(log_file):
-                with sc_open(log_file) as f:
-                    log_attach = MIMEApplication(f.read())
-                    log_name, _ = os.path.splitext(log)
-                    # Make attachment a txt file to avoid issues with tools not loading .log
-                    log_attach.add_header('Content-Disposition',
+    if cred["max_file_size"] > 0:
+        if msg_type == "summary":
+            layout_img = report_utils._find_summary_image(chip)
+            if layout_img and os.path.isfile(layout_img):
+                with open(layout_img, 'rb') as img_file:
+                    img_attach = MIMEApplication(img_file.read())
+                    img_attach.add_header('Content-Disposition',
                                           'attachment',
-                                          filename=f'{log_name}.txt')
-                    msg.attach(log_attach)
+                                          filename=os.path.basename(layout_img))
+                    msg.attach(img_attach)
+
+            nodes_to_execute = get_executed_nodes(chip, flow)
+            nodes, errors, metrics, metrics_unit, metrics_to_show, _ = \
+                report_utils._collect_data(chip, flow=flow, flowgraph_nodes=nodes_to_execute)
+
+            text_msg = get_file_template('email/summary.j2').render(
+                design=chip.design,
+                nodes=nodes,
+                errors=errors,
+                metrics=metrics,
+                metrics_unit=metrics_unit,
+                metric_keys=metrics_to_show)
+        else:
+            # Attach logs
+            for log in (f'sc_{step}{index}.log', f'{step}.log'):
+                log_file = f'{chip.getworkdir(step=step, index=index)}/{log}'
+                if os.path.exists(log_file):
+                    with sc_open(log_file) as f:
+                        file_content = f.read().splitlines()
+                        # Limit to max_file_size
+                        file_content = file_content[-cred["max_file_size"]:]
+                        log_attach = MIMEApplication("\n".join(file_content))
+                        log_name, _ = os.path.splitext(log)
+                        # Make attachment a txt file to avoid issues with tools not loading .log
+                        log_attach.add_header('Content-Disposition',
+                                              'attachment',
+                                              filename=f'{log_name}.txt')
+                        msg.attach(log_attach)
 
         records = {}
         for record in chip.getkeys('record'):

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/scheduler/validation/email_credentials.json

@@ -47,6 +47,13 @@
             "examples": [true],
             "type": "boolean",
             "default": true
+        },
+        "max_file_size": {
+            "title": "Max line in log file",
+            "description": "Maximum number of file lines to include in log",
+            "examples": [1000],
+            "type": "integer",
+            "default": 1000
         }
     },
 

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/targets/fpgaflow_demo.py

@@ -16,25 +16,24 @@ def make_docs(chip):
 ####################################################
 # Target Setup
 ####################################################
-def setup(chip):
+def setup(chip, partname=None):
     '''
     Demonstration target for running the open-source fpgaflow.
     '''
 
     # 1. Configure fpga part
-    part_name = chip.get('fpga', 'partname')
-    if not part_name:
+    if not partname:
+        partname = chip.get('fpga', 'partname')
+
+    if not partname:
         raise SiliconCompilerError('FPGA partname has not been set.', chip=chip)
 
     # 2.  Load all available FPGAs
     chip.use(lattice_ice40)
     chip.use(vpr_example)
 
-    if part_name not in chip.getkeys('fpga'):
-        raise SiliconCompilerError(f'{part_name} has not been loaded', chip=chip)
-
     # 3. Load flow
-    chip.use(fpgaflow, partname=part_name)
+    chip.use(fpgaflow, partname=partname)
 
     # 4. Select default flow
     chip.set('option', 'flow', 'fpgaflow', clobber=False)

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/tools/_common/__init__.py

@@ -115,17 +115,17 @@ def get_input_files(chip, *key, add_library_files=True):
         add_library_files (bool): When True, files from library keys
             will be included
     '''
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
 
     files = []
     for key in __get_keys(chip, *key, include_library_files=False):
+        step, index = __get_step_index(chip, *key)
         files.extend(chip.find_files(*key, step=step, index=index))
 
     if add_library_files:
         for item in get_libraries(chip, include_asic=False):
             lib_key = ('library', item, *key)
             if __is_key_valid(chip, *lib_key):
+                step, index = __get_step_index(chip, *lib_key)
                 files.extend(chip.find_files(*lib_key, step=step, index=index))
 
     return __remove_duplicates(chip, files, list(key))

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/tools/vivado/bitstream.py

@@ -11,9 +11,15 @@ def setup(chip):
     vivado.setup_task(chip, task)
 
     design = chip.top()
-    chip.set('tool', tool, 'task', task, 'input', f'{design}_checkpoint.dcp',
+    chip.set('tool', tool, 'task', task, 'input', f'{design}.dcp',
              step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'output', f'{design}.bit',
+    chip.set('tool', tool, 'task', task, 'output', f'{design}.dcp',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.xdc',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.vg',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.bit',
              step=step, index=index)
 
 

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/tools/vivado/place.py

@@ -11,9 +11,13 @@ def setup(chip):
     vivado.setup_task(chip, task)
 
     design = chip.top()
-    chip.set('tool', tool, 'task', task, 'input', f'{design}_checkpoint.dcp',
+    chip.set('tool', tool, 'task', task, 'input', f'{design}.dcp',
              step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'output', f'{design}_checkpoint.dcp',
+    chip.set('tool', tool, 'task', task, 'output', f'{design}.dcp',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.xdc',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.vg',
              step=step, index=index)
 
 

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/tools/vivado/route.py

@@ -11,9 +11,13 @@ def setup(chip):
     vivado.setup_task(chip, task)
 
     design = chip.top()
-    chip.set('tool', tool, 'task', task, 'input', f'{design}_checkpoint.dcp',
+    chip.set('tool', tool, 'task', task, 'input', f'{design}.dcp',
              step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'output', f'{design}_checkpoint.dcp',
+    chip.set('tool', tool, 'task', task, 'output', f'{design}.dcp',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.xdc',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.vg',
              step=step, index=index)
 
 

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl

@@ -1,4 +1,4 @@
-open_checkpoint "inputs/${sc_design}_checkpoint.dcp"
+open_checkpoint "inputs/${sc_design}.dcp"
 if { $sc_constraint != "" } {
     write_bitstream -force -file "outputs/${sc_design}.bit"
 } else {

siliconcompiler-0.28.9/siliconcompiler/tools/vivado/scripts/sc_place.tcl

@@ -0,0 +1,2 @@
+open_checkpoint "inputs/${sc_design}.dcp"
+place_design

siliconcompiler-0.28.9/siliconcompiler/tools/vivado/scripts/sc_route.tcl

@@ -0,0 +1,4 @@
+open_checkpoint "inputs/${sc_design}.dcp"
+phys_opt_design
+power_opt_design
+route_design

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/tools/vivado/scripts/sc_run.tcl

@@ -28,7 +28,9 @@ source $sc_refdir/sc_$sc_task.tcl
 # Checkpoint
 ##############################
 
-write_checkpoint -force "outputs/${sc_design}_checkpoint"
+write_checkpoint -force "outputs/${sc_design}"
+write_xdc "outputs/${sc_design}.xdc"
+write_verilog "outputs/${sc_design}.vg"
 
 ##############################
 # Reports / Metrics
@@ -41,4 +43,4 @@ report_clock_utilization -file "reports/clock_utilization.rpt"
 report_drc -file "reports/drc.rpt"
 report_cdc -details -file "reports/cdc.rpt"
 
-report_design_analysis -qor_summary -json "qor_summary.json"
+report_design_analysis -qor_summary -json "reports/qor_summary.json"

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/tools/vivado/syn_fpga.py

@@ -12,7 +12,11 @@ def setup(chip):
 
     design = chip.top()
     chip.set('tool', tool, 'task', task, 'input', f'{design}.v', step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'output', f'{design}_checkpoint.dcp',
+    chip.set('tool', tool, 'task', task, 'output', f'{design}.dcp',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.xdc',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.vg',
              step=step, index=index)
 
 

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/tools/vivado/vivado.py

@@ -67,36 +67,52 @@ def normalize_version(version):
 
 
 def _parse_qor_summary(chip, step, index):
-    if not os.path.isfile('qor_summary.json'):
+    if not os.path.isfile('reports/qor_summary.json'):
         return
 
-    with sc_open('qor_summary.json') as f:
+    with sc_open('reports/qor_summary.json') as f:
         data = json.load(f)
 
         # Data is organized as list of tasks that Vivado has completed, with
         # metrics associated with each. The tasks appear to be in chronological
         # order, so we pull metrics from the last one.
         task = data['Design QoR Summary'][-1]
-        setup_wns = task['Wns(ns)']
-        setup_tns = task['Tns(ns)']
-        hold_wns = task['Whs(ns)']
-        hold_tns = task['Ths(ns)']
+        setup_wns = None
+        for metric in ('Wns(ns)', 'WNS(ns)'):
+            if metric in task:
+                setup_wns = task[metric]
+                break
+        setup_tns = None
+        for metric in ('Tns(ns)', 'TNS(ns)'):
+            if metric in task:
+                setup_tns = task[metric]
+                break
+        hold_wns = None
+        for metric in ('Whs(ns)', 'WHS(ns)'):
+            if metric in task:
+                hold_wns = task[metric]
+                break
+        hold_tns = None
+        for metric in ('Ths(ns)', 'THS(ns)'):
+            if metric in task:
+                hold_tns = task[metric]
+                break
 
         if setup_wns:
             record_metric(chip, step, index, 'setupwns', setup_wns,
-                          'qor_summary.json',
+                          'reports/qor_summary.json',
                           source_unit='ns')
         if setup_tns:
             record_metric(chip, step, index, 'setuptns', setup_tns,
-                          'qor_summary.json',
+                          'reports/qor_summary.json',
                           source_unit='ns')
         if hold_wns:
             record_metric(chip, step, index, 'holdwns', hold_wns,
-                          'qor_summary.json',
+                          'reports/qor_summary.json',
                           source_unit='ns')
         if hold_tns:
             record_metric(chip, step, index, 'holdtns', hold_tns,
-                          'qor_summary.json',
+                          'reports/qor_summary.json',
                           source_unit='ns')
 
 

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/tools/vpr/vpr.py

@@ -94,6 +94,11 @@ def runtime_options(chip):
 
     options.append(f"--device {device_code[0]}")
 
+    # Medium-term solution:  VPR performs hash digest checks that
+    # fail if file paths are changed between steps.  We wish to
+    # disable the digest checks to work around this
+    options.append("--verify_file_digests off")
+
     options.append(f"--write_block_usage {__block_file}")
     options.append("--outfile_prefix outputs/")
 

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "c3e802e73aa2ca2974874e487ae481fc4f2cb8c3",
+    "git-commit": "8300b5293dec4c0a0ef26cd2ba7ca6101714e155",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -66,7 +66,7 @@
   },
   "vpr": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "9dd5ff66e3ab43238f5a4cb14cafe17bc4afe527",
+    "git-commit": "de31f094aa4f894a5e6e0dc32c66365f4b341190",
     "auto-update": false
   },
   "icepack": {

{siliconcompiler-0.28.8 → siliconcompiler-0.28.9}/siliconcompiler.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.8
+Version: 0.28.9
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0

siliconcompiler-0.28.8/siliconcompiler/tools/vivado/scripts/sc_place.tcl

@@ -1,2 +0,0 @@
-open_checkpoint "inputs/${sc_design}_checkpoint.dcp"
-place_design

siliconcompiler-0.28.8/siliconcompiler/tools/vivado/scripts/sc_route.tcl

@@ -1,4 +0,0 @@
-open_checkpoint "inputs/${sc_design}_checkpoint.dcp"
-phys_opt_design
-power_opt_design
-route_design