siliconcompiler 0.28.7__tar.gz → 0.28.8__tar.gz

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/Changes

@@ -8,6 +8,19 @@ The changes in each SiliconCompiler release version are described below. Commit
 version shown in (). Where applicable, the contributors that suggested a given
 feature are shown in [].
 
+SiliconCompiler 0.28.8 (2024-11-20)
+=========================================
+
+**Minor:**
+
+ * Fixed dashboard handling of graph metrics when job history contains different sets.
+
+ * Tools:
+
+  * openroad: added reporting of module cell areas.
+  * vpr: added options to prevent crashing in designed with dangling ports.
+
+
 SiliconCompiler 0.28.7 (2024-11-12)
 =========================================
 

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.7
+Version: 0.28.8
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -25,7 +25,8 @@ Classifier: Topic :: Software Development :: Build Tools
 Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
-Requires-Dist: aiohttp==3.10.10
+Requires-Dist: aiohttp==3.10.11; python_version <= "3.8"
+Requires-Dist: aiohttp==3.11.2; python_version >= "3.9"
 Requires-Dist: requests==2.32.3
 Requires-Dist: PyYAML==6.0.2
 Requires-Dist: pandas>=1.1.5
@@ -46,7 +47,7 @@ Requires-Dist: docker==7.1.0
 Requires-Dist: importlib_metadata; python_version < "3.10"
 Requires-Dist: sc-surelog==1.84.1
 Requires-Dist: orjson==3.10.11
-Requires-Dist: streamlit==1.40.0; python_full_version != "3.9.7"
+Requires-Dist: streamlit==1.40.1; python_full_version != "3.9.7"
 Requires-Dist: streamlit_agraph==0.0.45; python_full_version != "3.9.7"
 Requires-Dist: streamlit-antd-components==0.3.2; python_full_version != "3.9.7"
 Requires-Dist: streamlit_javascript==0.1.5; python_full_version != "3.9.7"

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/pyproject.toml

@@ -32,7 +32,8 @@ classifiers = [
 ]
 requires-python = ">= 3.8"
 dependencies = [
-    "aiohttp == 3.10.10",
+    "aiohttp == 3.10.11; python_version <= '3.8'",
+    "aiohttp == 3.11.2; python_version >= '3.9'",
     "requests == 2.32.3",
     "PyYAML == 6.0.2",
     "pandas >= 1.1.5",
@@ -55,7 +56,7 @@ dependencies = [
     "orjson == 3.10.11",
 
     # dashboard, streamlit does not support 3.9.7
-    "streamlit == 1.40.0; python_full_version != '3.9.7'",
+    "streamlit == 1.40.1; python_full_version != '3.9.7'",
     "streamlit_agraph == 0.0.45; python_full_version != '3.9.7'",
     "streamlit-antd-components == 0.3.2; python_full_version != '3.9.7'",
     "streamlit_javascript == 0.1.5; python_full_version != '3.9.7'",

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.28.7'
+version = '0.28.8'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/report/dashboard/components/graph.py

@@ -133,7 +133,7 @@ def graph(metrics, nodes, node_to_step_index_map, graph_number):
 
     data, metric_unit = report.get_chart_data(_get_report_chips(), metric, nodes_as_step_and_index)
     if metric_unit:
-        y_axis_label = f'{metric}({metric_unit})'
+        y_axis_label = f'{metric} ({metric_unit})'
 
     # Prepare plot data
     filtered_data = {
@@ -142,7 +142,12 @@ def graph(metrics, nodes, node_to_step_index_map, graph_number):
         color_label: []
     }
 
-    if not nodes.empty:
+    labels = {
+        "runs": state.get_key(state.GRAPH_JOBS),
+        "nodes": [f'{step}{index}' for step, index in data]
+    }
+
+    if nodes:
         # filtering through data
         for job_name in state.get_key(state.GRAPH_JOBS):
             for step, index in data:
@@ -154,7 +159,7 @@ def graph(metrics, nodes, node_to_step_index_map, graph_number):
                     filtered_data[y_axis_label].append(data[(step, index)][job_name])
 
     # Setup chart
-    x_axis = altair.X(x_axis_label, axis=altair.Axis(labelAngle=-75))
+    x_axis = altair.X(x_axis_label, axis=altair.Axis(labelAngle=-75), sort=labels[x_axis_label])
 
     y_axis = y_axis_label
     if log_scale and chart_type != 'bar':
@@ -183,9 +188,9 @@ def graph(metrics, nodes, node_to_step_index_map, graph_number):
     streamlit.altair_chart(chart, use_container_width=True, theme='streamlit')
 
 
-def viewer(metric_dataframe, node_to_step_index_map, metric_to_metric_unit_map):
-    metrics = metric_dataframe.index.map(lambda x: metric_to_metric_unit_map[x])
-    nodes = metric_dataframe.columns
+def viewer(node_to_step_index_map):
+    nodes, metrics = report.get_chart_selection_options(_get_report_chips())
+    metrics = sorted(metrics)
 
     job_selector_col, graph_adder_col = streamlit.columns(2, gap='large')
     with job_selector_col:

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/report/dashboard/layouts/vertical_flowgraph.py

@@ -91,6 +91,6 @@ def layout():
 
     if "Graphs" in tabs:
         with tabs["Graphs"]:
-            graph.viewer(metric_dataframe, node_to_step_index_map, metric_to_metric_unit_map)
+            graph.viewer(node_to_step_index_map)
 
     _common.check_rerun()

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/report/dashboard/layouts/vertical_flowgraph_node_tab.py

@@ -112,6 +112,6 @@ def layout():
         components.file_viewer(chip, f'{chip.getworkdir()}/{chip.design}.png')
 
     if tab_selected == "Graphs":
-        graph.viewer(metric_dataframe, node_to_step_index_map, metric_to_metric_unit_map)
+        graph.viewer(node_to_step_index_map)
 
     _common.check_rerun()

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/report/dashboard/layouts/vertical_flowgraph_sac_tabs.py

@@ -105,6 +105,6 @@ def layout():
         components.file_viewer(chip, f'{chip.getworkdir()}/{chip.design}.png')
 
     if tab_selected == "Graphs":
-        graph.viewer(metric_dataframe, node_to_step_index_map, metric_to_metric_unit_map)
+        graph.viewer(node_to_step_index_map)
 
     _common.check_rerun()

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/report/report.py

@@ -335,9 +335,28 @@ def get_files(chip, step, index):
     return logs_and_reports
 
 
+def get_chart_selection_options(chips):
+    '''
+    Returns all the nodes and metrics available in the provided chips
+
+    Args:
+        chips (list) : A list of dictionaries with the form
+            {'chip_object': chip, 'chip_name': name}.
+    '''
+    nodes = set()
+    metrics = set()
+    for chip_and_chip_name in chips:
+        chip = chip_and_chip_name['chip_object']
+        nodes_list, _, _, _, chip_metrics, _ = \
+            utils._collect_data(chip, format_as_string=False)
+        nodes.update(set([f'{step}{index}' for step, index in nodes_list]))
+        metrics.update(set(chip_metrics))
+    return nodes, metrics
+
+
 def get_chart_data(chips, metric, nodes):
     '''
-    Returns returns a a tuple where the first element is a 2d dictionary of
+    Returns returns a tuple where the first element is a 2d dictionary of
     data points, following the forms {step+index: {chip_name: value}} where
     each dictionary can have many keys. The second element is a string that represents the unit.
 

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/tools/_common/asic.py

@@ -1,4 +1,5 @@
 from .. import _common
+import json
 
 
 def get_mainlib(chip):
@@ -169,3 +170,49 @@ def get_tool_task_var(chip,
     _, value = _common.pick_key(chip, reversed(check_keys), step=step, index=index)
 
     return value
+
+
+class CellArea:
+    def __init__(self):
+        self.__areas = {}
+
+    def addCell(self, name=None, module=None,
+                cellarea=None, cellcount=None,
+                macroarea=None, macrocount=None,
+                stdcellarea=None, stdcellcount=None):
+        if not name and not module:
+            return
+
+        if all([metric is None for metric in (
+                cellarea, cellcount,
+                macroarea, macrocount,
+                stdcellarea, stdcellcount)]):
+            return
+
+        if not name:
+            name = module
+
+        # ensure name is unique
+        check_name = name
+        idx = 0
+        while check_name in self.__areas:
+            check_name = f'{name}{idx}'
+            idx += 1
+        name = check_name
+
+        self.__areas[name] = {
+            "module": module,
+            "cellarea": cellarea,
+            "cellcount": cellcount,
+            "macroarea": macroarea,
+            "macrocount": macrocount,
+            "stdcellarea": stdcellarea,
+            "stdcellcount": stdcellcount
+        }
+
+    def size(self):
+        return len(self.__areas)
+
+    def writeReport(self, path):
+        with open(path, 'w') as f:
+            json.dump(self.__areas, f, indent=4)

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/tools/klayout/klayout_show.py

@@ -3,7 +3,7 @@ import os
 import sys
 
 
-def show(schema, tech, input_path, output_path, screenshot=False):
+def show(schema, tech, input_path, output_path, screenshot=False, report=None):
     # Extract info from manifest
     flow = schema.get('option', 'flow')
     step = schema.get('arg', 'step')
@@ -80,6 +80,14 @@ def show(schema, tech, input_path, output_path, screenshot=False):
             __screenshot(schema, layout_view, output_path)
         else:
             __screenshot_montage(schema, layout_view, xbins, ybins)
+    else:
+        if report:
+            rdb_id = layout_view.create_rdb(os.path.basename(report))
+            rdb = layout_view.rdb(rdb_id)
+            print(f"[INFO] reading DRC report: {report}")
+            rdb.load(report)
+
+            layout_view.show_rdb(rdb_id, cell_view.index())
 
 
 def __screenshot(schema, layout_view, output_path):
@@ -215,24 +223,56 @@ def main():
     if not design:
         design = schema.get('design')
 
-    if 'show_filepath' in schema.getkeys('tool', 'klayout', 'task', task, 'var') and \
-       schema.get('tool', 'klayout', 'task', task, 'var', 'show_filepath',
-                  step=step, index=index):
-        sc_filename = schema.get('tool', 'klayout', 'task', task, 'var', 'show_filepath',
-                                 step=step, index=index)[0]
-    else:
-        sc_fileext = schema.get('tool', 'klayout', 'task', task, 'var', 'show_filetype',
-                                step=step, index=index)[0]
-        for ext in (f'{sc_fileext}.gz', sc_fileext):
-            sc_filename = f"inputs/{design}.{ext}"
-            if os.path.exists(sc_filename):
+    sc_fileext = schema.get('tool', 'klayout', 'task', task, 'var', 'show_filetype',
+                            step=step, index=index)[0]
+    sc_report = None
+    if sc_fileext in ('lyrdb', 'ascii'):
+        sc_report = schema.get('tool', 'klayout', 'task', task, 'var', 'show_filepath',
+                               step=step, index=index)[0]
+
+        sc_filename = None
+        for fileext in ('gds', 'oas'):
+            for ext in (f'{fileext}.gz', fileext):
+                sc_filename = f"inputs/{design}.{ext}"
+                if os.path.exists(sc_filename):
+                    break
+                sc_filename = None
+            if sc_filename:
                 break
 
+        if not sc_filename:
+            show_step = schema.get('arg', 'step')
+            if schema.valid('tool', 'klayout', 'task', task, 'var', 'show_step'):
+                show_index = schema.get('tool', 'klayout', 'task', task, 'var', 'show_step',
+                                        step=step, index=index)[0]
+            show_index = schema.get('arg', 'index')
+            if schema.valid('tool', 'klayout', 'task', task, 'var', 'show_index'):
+                show_index = schema.get('tool', 'klayout', 'task', task, 'var', 'show_index',
+                                        step=step, index=index)[0]
+            for fileext in ('gds', 'oas'):
+                if schema.valid('input', 'layout', fileext) and \
+                   schema.get('input', 'layout', fileext, step=show_step, index=show_index):
+                    sc_filename = schema.get('input', 'layout', fileext,
+                                             step=show_step, index=show_index)[0]
+                    if sc_filename:
+                        break
+    else:
+        if 'show_filepath' in schema.getkeys('tool', 'klayout', 'task', task, 'var') and \
+           schema.get('tool', 'klayout', 'task', task, 'var', 'show_filepath',
+                      step=step, index=index):
+            sc_filename = schema.get('tool', 'klayout', 'task', task, 'var', 'show_filepath',
+                                     step=step, index=index)[0]
+        else:
+            for ext in (f'{sc_fileext}.gz', sc_fileext):
+                sc_filename = f"inputs/{design}.{ext}"
+                if os.path.exists(sc_filename):
+                    break
+
     sc_exit = schema.get('tool', 'klayout', 'task', task, 'var', 'show_exit',
                          step=step, index=index) == ["true"]
 
     show(schema, technology(design, schema), sc_filename, f'outputs/{design}.png',
-         screenshot=(task == 'screenshot'))
+         screenshot=(task == 'screenshot'), report=sc_report)
 
     if sc_exit:
         pya.Application.instance().exit(0)

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/tools/openroad/openroad.py

@@ -17,7 +17,8 @@ from siliconcompiler import sc_open
 from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, add_common_file, \
     get_tool_task, record_metric
-from siliconcompiler.tools._common.asic import get_mainlib, set_tool_task_var, get_libraries
+from siliconcompiler.tools._common.asic import get_mainlib, set_tool_task_var, get_libraries, \
+    CellArea
 from siliconcompiler.targets import asap7_demo
 
 
@@ -268,8 +269,12 @@ def post_process(chip):
                      "timing/hold.rpt",
                      "timing/hold.topN.rpt"],
         "holdpaths": ["timing/hold.topN.rpt"],
-        "unconstrained": ["timing/unconstrained.topN.rpt"],
-        "peakpower": [f"power/{corner}.rpt" for corner in chip.getkeys('constraint', 'timing')],
+        "unconstrained": ["timing/unconstrained.rpt", "timing/unconstrained.topN.rpt"],
+        "peakpower": [
+            *[f"power/{corner}.rpt" for corner in chip.getkeys('constraint', 'timing')],
+            *[f"images/heatmap/power_density/{corner}.png"
+              for corner in chip.getkeys('constraint', 'timing')]
+        ],
         "drvs": ["timing/drv_violators.rpt",
                  "floating_nets.rpt",
                  f"{chip.design}_antenna.rpt",
@@ -277,7 +282,9 @@ def post_process(chip):
         "drcs": [f"{chip.design}_drc.rpt",
                  f"markers/{chip.design}.drc.rpt",
                  f"markers/{chip.design}.drc.json",
-                 f"images/markers/{chip.design}.drc.png"]
+                 f"images/markers/{chip.design}.drc.png"],
+        "utilization": ["images/heatmap/placement_density.png"],
+        "wirelength": [f"images/{chip.design}.routing.png"]
     }
     metric_reports["leakagepower"] = metric_reports["peakpower"]
 
@@ -300,6 +307,8 @@ def post_process(chip):
             chip.logger.error(f'Unable to parse metrics from OpenROAD: {e}')
             metrics = {}
 
+        _generate_cell_area_report(chip.top(), metrics)
+
         or_units = {}
         for unit, or_unit in [('time', 'run__flow__platform__time_units'),
                               ('capacitance', 'run__flow__platform__capacitance_units'),
@@ -424,6 +433,114 @@ def post_process(chip):
             record_metric(chip, step, index, 'drcs', drcs, get_metric_sources('drcs'))
 
 
+def _generate_cell_area_report(design, ord_metrics):
+    cellarea_report = CellArea()
+
+    prefix = "sc__cellarea__design__instance"
+
+    filtered_data = {}
+    for key, value in ord_metrics.items():
+        if key.startswith(prefix):
+            filtered_data[key[len(prefix)+2:]] = value
+
+    modules = set()
+    modules.add("")
+    for key in filtered_data.keys():
+        if "__in_module:" in key:
+            module = key[key.find("__in_module:"):]
+            modules.add(module)
+
+    def process_cell(group):
+        data = {}
+        for key, value in filtered_data.items():
+            if (group != "" and key.endswith(group)):
+                key = key[:key.find("__in_module:")]
+                data[key] = value
+            elif (group == "" and "__in_module" not in key):
+                data[key] = value
+
+        cell_type = None
+        cell_name = None
+
+        if not group:
+            cell_type = design
+            cell_name = design
+        else:
+            cell_type = group[len("__in_module:"):]
+
+        cellarea = None
+        cellcount = None
+
+        macroarea = None
+        macrocount = None
+
+        stdcell_types = (
+            'tie_cell',
+            'standard_cell',
+            'buffer',
+            'clock_buffer',
+            'timing_repair_buffer',
+            'inverter',
+            'clock_inverter',
+            'timing_Repair_inverter',
+            'clock_gate_cell',
+            'level_shifter_cell',
+            'sequential_cell',
+            'multi_input_combinational_cell',
+            'other'
+            )
+
+        stdcell_info_area = []
+        stdcell_info_count = []
+        stdcellarea = None
+        stdcellcount = None
+
+        for key, value in data.items():
+            if key == 'name':
+                cell_name = value
+            elif key == 'count':
+                cellcount = value
+            elif key == 'area':
+                cellarea = value
+            elif key.startswith('count__class'):
+                _, cell_class = key.split(':')
+                if cell_class == 'macro':
+                    macrocount = value
+                elif cell_class in stdcell_types:
+                    stdcell_info_count.append(value)
+            elif key.startswith('area__class'):
+                _, cell_class = key.split(':')
+                if cell_class == 'macro':
+                    macroarea = value
+                elif cell_class in stdcell_types:
+                    stdcell_info_area.append(value)
+
+        if stdcell_info_count:
+            stdcellcount = sum(stdcell_info_count)
+        if stdcell_info_area:
+            stdcellarea = sum(stdcell_info_area)
+
+        cellarea_report.addCell(
+            name=cell_name,
+            module=cell_type,
+            cellarea=cellarea,
+            cellcount=cellcount,
+            macroarea=macroarea,
+            macrocount=macrocount,
+            stdcellarea=stdcellarea,
+            stdcellcount=stdcellcount)
+
+        if filtered_data:
+            return True
+        return False
+
+    for module in modules:
+        process_cell(module)
+
+    if cellarea_report.size() > 0:
+        cellarea_report.writeReport("reports/hierarchical_cell_area.json")
+
+
 ######
 def get_library_timing_keypaths(chip, lib):
     step = chip.get('arg', 'step')

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/tools/openroad/scripts/sc_procs.tcl

@@ -483,3 +483,12 @@ proc sc_convert_rotation { rot } {
     default { utl::error FLW 1 "$rot not recognized" }
   }
 }
+
+proc sc_check_version { min_required } {
+  set version [split [ord::openroad_version] "-"]
+  if { [lindex $version 0] != "v2.0" } {
+    return false
+  }
+
+  return [expr { [lindex $version 1] >= $min_required }]
+}

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/tools/openroad/scripts/sc_report.tcl

@@ -168,3 +168,22 @@ foreach markerdb [[ord::get_db_block] getMarkerCategories] {
   $markerdb writeTR "reports/markers/${sc_design}.[$markerdb getName].rpt"
   $markerdb writeJSON "reports/markers/${sc_design}.[$markerdb getName].json"
 }
+
+if { [sc_check_version 17038] } {
+  utl::push_metrics_stage "sc__cellarea__{}"
+  tee -file reports/cell_usage.rpt {report_cell_usage -verbose}
+
+  foreach modinst [[ord::get_db_block] getModInsts] {
+    tee -quiet -append -file reports/cell_usage.rpt { puts "" }
+    tee -quiet -append -file reports/cell_usage.rpt {
+      puts "########################################################"
+    }
+    tee -quiet -append -file reports/cell_usage.rpt { puts "" }
+
+    utl::metric "design__instance__name__in_module:[[$modinst getMaster] getName]" \
+      [$modinst getHierarchicalName]
+    tee -quiet -append -file reports/cell_usage.rpt \
+      "report_cell_usage -verbose [$modinst getHierarchicalName]"
+  }
+  utl::pop_metrics_stage
+}

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/tools/vpr/vpr.py

@@ -128,6 +128,12 @@ def runtime_options(chip):
     # If we allow VPR to sweep dangling primary I/Os and logic blocks
     # it can interfere with circuit debugging; so disable that
     options.append('--sweep_dangling_primary_ios off')
+    # If you don't sweep dangling primary I/Os, but sweeping nets
+    # VPR can crash:
+    options.append('--sweep_dangling_nets off')
+    # If you don't sweep dangling nets then the timing engine requires
+    # you to set an option allowing dangling nodes
+    options.append('--allow_dangling_combinational_nodes on')
     options.append('--sweep_constant_primary_outputs off')
     options.append('--sweep_dangling_blocks off')
 

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/tools/yosys/syn_asic.tcl

@@ -231,6 +231,8 @@ sc_map_memory $sc_memory_libmap_files $sc_memory_techmap_files 0
 
 # Perform hierarchy flattening
 if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "true" } {
+    yosys log -push
+    yosys log -header "SC Auto flattening"
     set sc_hier_iterations \
         [lindex [sc_cfg_tool_task_get var hier_iterations] 0]
     set sc_hier_threshold \
@@ -240,6 +242,7 @@ if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "
             break
         }
     }
+    yosys log -pop
 }
 
 # Finish synthesis

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "dcba5786c8e714e3b7682a98d73de40e875699b1",
+    "git-commit": "c3e802e73aa2ca2974874e487ae481fc4f2cb8c3",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/utils/__init__.py

@@ -84,7 +84,7 @@ def get_default_iomap():
     # Record extensions:
 
     # High level languages
-    hll_c = ('c', 'cc', 'cpp', 'c++', 'cp', 'cxx', 'hpp')
+    hll_c = ('c', 'cc', 'cpp', 'c++', 'cp', 'cxx', 'hpp', 'h')
     hll_bsv = ('bsv',)
     hll_scala = ('scala',)
     hll_python = ('py',)
@@ -92,8 +92,8 @@ def get_default_iomap():
     config_chisel = ('sbt',)
 
     # Register transfer languages
-    rtl_verilog = ('v', 'verilog')
-    rtl_systemverilog = ('sv',)
+    rtl_verilog = ('v', 'verilog', 'vh')
+    rtl_systemverilog = ('sv', 'svh')
     rtl_vhdl = ('vhd', 'vhdl')
 
     # Timing libraries
@@ -116,8 +116,8 @@ def get_default_iomap():
     waveform_vcd = ('vcd',)
 
     # Constraint
-    constraint_sdc = ('sdc', )
-    constraint_upf = ('upf', )
+    constraint_sdc = ('sdc',)
+    constraint_upf = ('upf',)
 
     # FPGA constraints
     fpga_xdc = ('xdc',)
@@ -125,6 +125,10 @@ def get_default_iomap():
     fpga_vpr_place = ('place',)
     fpga_vpr_route = ('route',)
 
+    # Reports
+    report_drc = ('lyrdb', 'ascii')
+    report_log = ('log',)
+
     # Build default map with fileset and type
     default_iomap = {}
     default_iomap.update({ext: ('hll', 'c') for ext in hll_c})
@@ -160,6 +164,9 @@ def get_default_iomap():
     default_iomap.update({ext: ('fpga', 'vpr_place') for ext in fpga_vpr_place})
     default_iomap.update({ext: ('fpga', 'vpr_route') for ext in fpga_vpr_route})
 
+    default_iomap.update({ext: ('report', 'drc') for ext in report_drc})
+    default_iomap.update({ext: ('report', 'log') for ext in report_log})
+
     return default_iomap
 
 

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler/utils/showtools.py

@@ -14,6 +14,8 @@ def setup(chip):
     chip.register_showtool('oas', klayout_screenshot)
     chip.register_showtool('lef', klayout_show)
     chip.register_showtool('lef', klayout_screenshot)
+    chip.register_showtool('lyrdb', klayout_show)
+    chip.register_showtool('ascii', klayout_show)
 
     chip.register_showtool('odb', openroad_show)
     chip.register_showtool('odb', openroad_screenshot)

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.7
+Version: 0.28.8
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -25,7 +25,8 @@ Classifier: Topic :: Software Development :: Build Tools
 Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
-Requires-Dist: aiohttp==3.10.10
+Requires-Dist: aiohttp==3.10.11; python_version <= "3.8"
+Requires-Dist: aiohttp==3.11.2; python_version >= "3.9"
 Requires-Dist: requests==2.32.3
 Requires-Dist: PyYAML==6.0.2
 Requires-Dist: pandas>=1.1.5
@@ -46,7 +47,7 @@ Requires-Dist: docker==7.1.0
 Requires-Dist: importlib_metadata; python_version < "3.10"
 Requires-Dist: sc-surelog==1.84.1
 Requires-Dist: orjson==3.10.11
-Requires-Dist: streamlit==1.40.0; python_full_version != "3.9.7"
+Requires-Dist: streamlit==1.40.1; python_full_version != "3.9.7"
 Requires-Dist: streamlit_agraph==0.0.45; python_full_version != "3.9.7"
 Requires-Dist: streamlit-antd-components==0.3.2; python_full_version != "3.9.7"
 Requires-Dist: streamlit_javascript==0.1.5; python_full_version != "3.9.7"

{siliconcompiler-0.28.7 → siliconcompiler-0.28.8}/siliconcompiler.egg-info/SOURCES.txt

@@ -342,7 +342,6 @@ siliconcompiler/toolscripts/rhel8/install-klayout.sh
 siliconcompiler/toolscripts/rhel8/install-magic.sh
 siliconcompiler/toolscripts/rhel8/install-montage.sh
 siliconcompiler/toolscripts/rhel8/install-netgen.sh
-siliconcompiler/toolscripts/rhel8/install-openroad.sh
 siliconcompiler/toolscripts/rhel8/install-slang.sh
 siliconcompiler/toolscripts/rhel8/install-surelog.sh
 siliconcompiler/toolscripts/rhel8/install-sv2v.sh