silica-eda 0.1.0__tar.gz

silica_eda-0.1.0/.claude/settings.local.json

@@ -0,0 +1,23 @@
+{
+  "permissions": {
+    "allow": [
+      "Bash(/Users/simaanc/Developer/silica/.venv/bin/python --version)",
+      "Bash(/Users/simaanc/Developer/silica/.venv/bin/pip show *)",
+      "Bash(.venv/bin/pip install *)",
+      "Bash(uv add *)",
+      "Bash(uv sync *)",
+      "Bash(.venv/bin/silica config *)",
+      "Bash(.venv/bin/python *)",
+      "Bash(.venv/bin/silica unknown_cmd)",
+      "Bash(echo \"exit: $?\")",
+      "Bash(git add *)",
+      "Bash(git commit -m 'feat: add silica setup wizard and silica config status viewer *)",
+      "Bash(git commit *)",
+      "Bash(verilator *)",
+      "Bash(sby --help)",
+      "Bash(cat)",
+      "Bash(sby -f -t test.sby)",
+      "Bash(brew list *)"
+    ]
+  }
+}

silica_eda-0.1.0/.gitignore

@@ -0,0 +1,45 @@
+# Python bytecode
+__pycache__/
+*.py[cod]
+*.pyd
+.Python
+
+# Distribution / packaging
+build/
+dist/
+*.egg-info/
+*.egg
+.eggs/
+MANIFEST
+
+# Virtual environments
+.env
+.venv
+env/
+venv/
+ENV/
+
+# Testing and analysis caches
+.pytest_cache/
+.mypy_cache/
+.ruff_cache/
+.coverage
+coverage.xml
+htmlcov/
+
+# Type checkers
+.dmypy.json
+dmypy.json
+
+# Editors and OS
+.DS_Store
+.idea/
+.vscode/
+*.swp
+*.swo
+*~
+
+# Project-specific
+*.vcd
+obj_dir/
+HANDOFF.md

silica_eda-0.1.0/PKG-INFO

@@ -0,0 +1,237 @@
+Metadata-Version: 2.4
+Name: silica-eda
+Version: 0.1.0
+Summary: AI-native EDA environment — MCP server for hardware design and verification
+Author-email: Christopher Simaan <dev@getsilica.dev>
+License: MIT
+Keywords: ai,eda,fpga,hardware,mcp,rtl,systemverilog,verilog
+Classifier: Development Status :: 3 - Alpha
+Classifier: Intended Audience :: Developers
+Classifier: License :: OSI Approved :: MIT License
+Classifier: Programming Language :: Python :: 3.11
+Classifier: Programming Language :: Python :: 3.12
+Requires-Python: >=3.11
+Requires-Dist: mcp<2.0.0,>=1.9.0
+Requires-Dist: tomli-w>=1.0.0
+Provides-Extra: dev
+Requires-Dist: pytest-asyncio>=0.23; extra == 'dev'
+Requires-Dist: pytest>=8.0; extra == 'dev'
+Requires-Dist: ruff>=0.4; extra == 'dev'
+Description-Content-Type: text/markdown
+
+# Silica
+
+AI-native EDA environment — an MCP server that gives any LLM deep integration with the full EDA toolchain: simulation, synthesis, linting, formal verification, and autonomous debug loops.
+
+## What it does
+
+Silica wraps open source EDA tools (Verilator, Yosys, Verible, Icarus) in a structured MCP interface. You describe what you want to the model; Silica gives it the tool access and reasoning skills to find and fix RTL bugs, synthesize designs, and run verification workflows autonomously.
+
+The core value: **closed autonomous loops**. Run sim → parse failure → reason about RTL → propose fix → re-run — without human copy-paste.
+
+## Quick start
+
+### 1. Install Silica
+
+```bash
+pip install silica-eda
+```
+
+### 2. Run the setup wizard
+
+```bash
+silica setup
+```
+
+The wizard detects which MCP clients and EDA tools you already have installed, lets you choose what to enable, and writes the MCP client config for you. It covers Claude Desktop, Claude Code, Cursor, Zed, Windsurf, OpenCode, and Gemini CLI.
+
+When it's done, check your config anytime with:
+
+```bash
+silica config
+```
+
+### 3. Install missing tools (if any)
+
+The wizard prints install commands for any open source tools you selected but don't have yet. For example on macOS:
+
+```bash
+brew install verilator yosys icarus-verilog verible
+```
+
+**Ubuntu / Debian**
+```bash
+sudo apt update && sudo apt install verilator yosys iverilog
+# Verible: sudo apt install verible  (Ubuntu 22.04+)
+# or grab the release binary: https://github.com/chipsalliance/verible/releases
+```
+
+**Fedora / RHEL**
+```bash
+sudo dnf install verilator yosys iverilog
+```
+
+**Arch**
+```bash
+sudo pacman -S verilator yosys iverilog verible
+```
+
+**Windows**
+WSL2 is the recommended path:
+```powershell
+wsl --install   # installs Ubuntu by default
+```
+Then follow the Ubuntu instructions above inside WSL. Claude Desktop and Cursor both support MCP servers running inside WSL via the `wsl -e silica serve` command pattern.
+
+### 4. Start the server
+
+```bash
+silica serve
+```
+
+Your MCP client will launch this automatically — you typically don't need to run it manually.
+
+### 5. Test the UART example
+
+Ask Claude:
+
+> Run the UART TX simulation in examples/uart/ and tell me if it passes.
+
+Or introduce a bug and ask Claude to find and fix it autonomously:
+
+> In examples/uart/uart_tx.sv, change line 54 to use `==` instead of `== CLKS_PER_BIT - 1` for the baud counter comparison. Then run the simulation, find the bug, and fix it.
+
+## Manual client setup
+
+If you prefer to configure your MCP client by hand instead of using `silica setup`:
+
+**Claude Desktop** — `~/Library/Application Support/Claude/claude_desktop_config.json` (macOS) or `~/.config/Claude/claude_desktop_config.json` (Linux):
+
+```json
+{
+  "mcpServers": {
+    "silica": {
+      "command": "silica",
+      "args": ["serve"]
+    }
+  }
+}
+```
+
+**Claude Code**
+```bash
+claude mcp add silica silica serve
+```
+
+**Cursor** — `~/.cursor/mcp.json`:
+```json
+{
+  "mcpServers": {
+    "silica": {
+      "command": "silica",
+      "args": ["serve"]
+    }
+  }
+}
+```
+
+**Windows (WSL2)**
+```json
+{
+  "mcpServers": {
+    "silica": {
+      "command": "wsl",
+      "args": ["-e", "silica", "serve"]
+    }
+  }
+}
+```
+
+## CLI reference
+
+| Command | Description |
+|---|---|
+| `silica serve` | Start the MCP server (stdio transport). Default if no subcommand given. |
+| `silica setup` | Interactive first-run configuration wizard. |
+| `silica config` | Show current configuration and live tool status. |
+
+## MCP Tools (v0.1)
+
+| Tool | Description |
+|---|---|
+| `run_simulation` | Simulate RTL (Verilator / Icarus). Returns structured errors. |
+| `synthesize` | Synthesize to gates (Yosys). Returns utilization. |
+| `lint` | Static analysis (Verible / Verilator). Returns structured warnings. |
+| `read_rtl` | Read source file with line numbers. |
+| `write_rtl` | Propose RTL changes — always dry_run=True before writing. |
+| `get_project_structure` | Scan for RTL and constraint files. |
+| `search_rtl` | Grep across project RTL with context. |
+| `get_constraints` | Read constraint files (.xdc, .sdc, .lpf). |
+
+## Workflow Skills
+
+Silica ships reasoning scripts that teach the model how to interpret tool output and form hypotheses — not just how to call tools. Available as MCP prompts:
+
+- `debug_simulation_failure` — step-by-step triage from error list to verified fix
+- `write_testbench` — generate a complete testbench from a module interface
+- `generate_assertions` — write SVA assertions from design intent
+- `close_timing` — work through timing violations with synthesis feedback
+
+## Architecture
+
+```
+silica/
+├── silica/
+│   ├── server.py              # FastMCP server; loads skills at boot
+│   ├── cli.py                 # subcommand dispatch (serve / setup / config)
+│   ├── tools_registry.py      # canonical list of all supported EDA tools
+│   ├── clients_registry.py    # canonical list of all supported MCP clients
+│   ├── terminal.py            # OSC 8 hyperlink support
+│   ├── config.py              # ~/.silica/config.toml load/save
+│   ├── setup.py               # interactive setup wizard + config viewer
+│   ├── tools/                 # MCP tool definitions
+│   │   ├── simulation.py      # run_simulation()
+│   │   ├── synthesis.py       # synthesize()
+│   │   ├── lint.py            # lint()
+│   │   └── project.py         # read_rtl(), write_rtl(), get_project_structure(), ...
+│   ├── adapters/              # per-tool CLI wrappers + output parsers
+│   │   ├── verilator.py
+│   │   ├── icarus.py
+│   │   ├── yosys.py
+│   │   └── verible.py
+│   └── skills/
+│       ├── base/rtl_assistant.md
+│       └── workflows/
+│           └── debug_simulation_failure.md
+└── examples/
+    └── uart/                  # reference design for end-to-end testing
+```
+
+## Toolchain coverage (v0.1)
+
+| Category | Open source | Commercial (detected if on PATH) |
+|---|---|---|
+| Simulation | Verilator, Icarus Verilog | VCS (Synopsys), Questa (Siemens), Xcelium (Cadence) |
+| Synthesis | Yosys | Vivado (AMD/Xilinx), Quartus (Intel), DC Shell (Synopsys) |
+| Formal | SymbiYosys | JasperGold (Cadence), VC Formal (Synopsys) |
+| Lint | Verible, svlint | SpyGlass (Synopsys) |
+| Waveform | GTKWave, Surfer | Verdi (Synopsys) |
+
+## Development
+
+```bash
+git clone https://github.com/getsilica/silica
+cd silica
+pip install -e ".[dev]"
+
+# Run the server locally (for debugging)
+silica serve
+
+# Run the UART end-to-end test
+iverilog -g2012 -o /tmp/uart_sim examples/uart/uart_tx_tb.sv examples/uart/uart_tx.sv
+vvp /tmp/uart_sim
+```
+
+## License
+
+MIT

silica_eda-0.1.0/README.md

@@ -0,0 +1,216 @@
+# Silica
+
+AI-native EDA environment — an MCP server that gives any LLM deep integration with the full EDA toolchain: simulation, synthesis, linting, formal verification, and autonomous debug loops.
+
+## What it does
+
+Silica wraps open source EDA tools (Verilator, Yosys, Verible, Icarus) in a structured MCP interface. You describe what you want to the model; Silica gives it the tool access and reasoning skills to find and fix RTL bugs, synthesize designs, and run verification workflows autonomously.
+
+The core value: **closed autonomous loops**. Run sim → parse failure → reason about RTL → propose fix → re-run — without human copy-paste.
+
+## Quick start
+
+### 1. Install Silica
+
+```bash
+pip install silica-eda
+```
+
+### 2. Run the setup wizard
+
+```bash
+silica setup
+```
+
+The wizard detects which MCP clients and EDA tools you already have installed, lets you choose what to enable, and writes the MCP client config for you. It covers Claude Desktop, Claude Code, Cursor, Zed, Windsurf, OpenCode, and Gemini CLI.
+
+When it's done, check your config anytime with:
+
+```bash
+silica config
+```
+
+### 3. Install missing tools (if any)
+
+The wizard prints install commands for any open source tools you selected but don't have yet. For example on macOS:
+
+```bash
+brew install verilator yosys icarus-verilog verible
+```
+
+**Ubuntu / Debian**
+```bash
+sudo apt update && sudo apt install verilator yosys iverilog
+# Verible: sudo apt install verible  (Ubuntu 22.04+)
+# or grab the release binary: https://github.com/chipsalliance/verible/releases
+```
+
+**Fedora / RHEL**
+```bash
+sudo dnf install verilator yosys iverilog
+```
+
+**Arch**
+```bash
+sudo pacman -S verilator yosys iverilog verible
+```
+
+**Windows**
+WSL2 is the recommended path:
+```powershell
+wsl --install   # installs Ubuntu by default
+```
+Then follow the Ubuntu instructions above inside WSL. Claude Desktop and Cursor both support MCP servers running inside WSL via the `wsl -e silica serve` command pattern.
+
+### 4. Start the server
+
+```bash
+silica serve
+```
+
+Your MCP client will launch this automatically — you typically don't need to run it manually.
+
+### 5. Test the UART example
+
+Ask Claude:
+
+> Run the UART TX simulation in examples/uart/ and tell me if it passes.
+
+Or introduce a bug and ask Claude to find and fix it autonomously:
+
+> In examples/uart/uart_tx.sv, change line 54 to use `==` instead of `== CLKS_PER_BIT - 1` for the baud counter comparison. Then run the simulation, find the bug, and fix it.
+
+## Manual client setup
+
+If you prefer to configure your MCP client by hand instead of using `silica setup`:
+
+**Claude Desktop** — `~/Library/Application Support/Claude/claude_desktop_config.json` (macOS) or `~/.config/Claude/claude_desktop_config.json` (Linux):
+
+```json
+{
+  "mcpServers": {
+    "silica": {
+      "command": "silica",
+      "args": ["serve"]
+    }
+  }
+}
+```
+
+**Claude Code**
+```bash
+claude mcp add silica silica serve
+```
+
+**Cursor** — `~/.cursor/mcp.json`:
+```json
+{
+  "mcpServers": {
+    "silica": {
+      "command": "silica",
+      "args": ["serve"]
+    }
+  }
+}
+```
+
+**Windows (WSL2)**
+```json
+{
+  "mcpServers": {
+    "silica": {
+      "command": "wsl",
+      "args": ["-e", "silica", "serve"]
+    }
+  }
+}
+```
+
+## CLI reference
+
+| Command | Description |
+|---|---|
+| `silica serve` | Start the MCP server (stdio transport). Default if no subcommand given. |
+| `silica setup` | Interactive first-run configuration wizard. |
+| `silica config` | Show current configuration and live tool status. |
+
+## MCP Tools (v0.1)
+
+| Tool | Description |
+|---|---|
+| `run_simulation` | Simulate RTL (Verilator / Icarus). Returns structured errors. |
+| `synthesize` | Synthesize to gates (Yosys). Returns utilization. |
+| `lint` | Static analysis (Verible / Verilator). Returns structured warnings. |
+| `read_rtl` | Read source file with line numbers. |
+| `write_rtl` | Propose RTL changes — always dry_run=True before writing. |
+| `get_project_structure` | Scan for RTL and constraint files. |
+| `search_rtl` | Grep across project RTL with context. |
+| `get_constraints` | Read constraint files (.xdc, .sdc, .lpf). |
+
+## Workflow Skills
+
+Silica ships reasoning scripts that teach the model how to interpret tool output and form hypotheses — not just how to call tools. Available as MCP prompts:
+
+- `debug_simulation_failure` — step-by-step triage from error list to verified fix
+- `write_testbench` — generate a complete testbench from a module interface
+- `generate_assertions` — write SVA assertions from design intent
+- `close_timing` — work through timing violations with synthesis feedback
+
+## Architecture
+
+```
+silica/
+├── silica/
+│   ├── server.py              # FastMCP server; loads skills at boot
+│   ├── cli.py                 # subcommand dispatch (serve / setup / config)
+│   ├── tools_registry.py      # canonical list of all supported EDA tools
+│   ├── clients_registry.py    # canonical list of all supported MCP clients
+│   ├── terminal.py            # OSC 8 hyperlink support
+│   ├── config.py              # ~/.silica/config.toml load/save
+│   ├── setup.py               # interactive setup wizard + config viewer
+│   ├── tools/                 # MCP tool definitions
+│   │   ├── simulation.py      # run_simulation()
+│   │   ├── synthesis.py       # synthesize()
+│   │   ├── lint.py            # lint()
+│   │   └── project.py         # read_rtl(), write_rtl(), get_project_structure(), ...
+│   ├── adapters/              # per-tool CLI wrappers + output parsers
+│   │   ├── verilator.py
+│   │   ├── icarus.py
+│   │   ├── yosys.py
+│   │   └── verible.py
+│   └── skills/
+│       ├── base/rtl_assistant.md
+│       └── workflows/
+│           └── debug_simulation_failure.md
+└── examples/
+    └── uart/                  # reference design for end-to-end testing
+```
+
+## Toolchain coverage (v0.1)
+
+| Category | Open source | Commercial (detected if on PATH) |
+|---|---|---|
+| Simulation | Verilator, Icarus Verilog | VCS (Synopsys), Questa (Siemens), Xcelium (Cadence) |
+| Synthesis | Yosys | Vivado (AMD/Xilinx), Quartus (Intel), DC Shell (Synopsys) |
+| Formal | SymbiYosys | JasperGold (Cadence), VC Formal (Synopsys) |
+| Lint | Verible, svlint | SpyGlass (Synopsys) |
+| Waveform | GTKWave, Surfer | Verdi (Synopsys) |
+
+## Development
+
+```bash
+git clone https://github.com/getsilica/silica
+cd silica
+pip install -e ".[dev]"
+
+# Run the server locally (for debugging)
+silica serve
+
+# Run the UART end-to-end test
+iverilog -g2012 -o /tmp/uart_sim examples/uart/uart_tx_tb.sv examples/uart/uart_tx.sv
+vvp /tmp/uart_sim
+```
+
+## License
+
+MIT

silica_eda-0.1.0/examples/uart/uart_tx.sv

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+// uart_tx.sv — UART transmitter, 8N1, synchronous design
+//
+// Interface:
+//   valid/ready handshake — assert valid with data_in; ready pulses high when
+//   the transmitter accepts the byte and begins transmission.
+//   tx idles HIGH; start bit is LOW.
+
+`timescale 1ns/1ps
+
+module uart_tx #(
+    parameter int CLK_FREQ  = 50_000_000,  // Hz
+    parameter int BAUD_RATE = 115_200       // bps
+) (
+    input  logic       clk,
+    input  logic       rst_n,   // active-low async reset
+    input  logic [7:0] data_in,
+    input  logic       valid,
+    output logic       ready,
+    output logic       tx
+);
+
+    localparam int CLKS_PER_BIT = CLK_FREQ / BAUD_RATE;  // 434 @ 50 MHz / 115200
+
+    typedef enum logic [1:0] {
+        IDLE  = 2'b00,
+        START = 2'b01,
+        DATA  = 2'b10,
+        STOP  = 2'b11
+    } state_t;
+
+    state_t        state;
+    logic [15:0]   baud_cnt;
+    logic [2:0]    bit_idx;
+    logic [7:0]    shift_reg;
+
+    assign ready = (state == IDLE);
+
+    always_ff @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            state     <= IDLE;
+            baud_cnt  <= '0;
+            bit_idx   <= '0;
+            shift_reg <= '0;
+            tx        <= 1'b1;
+        end else begin
+            case (state)
+                IDLE: begin
+                    tx <= 1'b1;
+                    if (valid) begin
+                        state     <= START;
+                        shift_reg <= data_in;
+                        baud_cnt  <= '0;
+                    end
+                end
+
+                START: begin
+                    tx <= 1'b0;
+                    if (baud_cnt == 16'(CLKS_PER_BIT - 1)) begin
+                        state    <= DATA;
+                        baud_cnt <= '0;
+                        bit_idx  <= '0;
+                    end else begin
+                        baud_cnt <= baud_cnt + 1;
+                    end
+                end
+
+                DATA: begin
+                    tx <= shift_reg[0];
+                    if (baud_cnt == 16'(CLKS_PER_BIT - 1)) begin
+                        baud_cnt  <= '0;
+                        shift_reg <= {1'b0, shift_reg[7:1]};
+                        if (bit_idx == 3'd7) begin
+                            state <= STOP;
+                        end else begin
+                            bit_idx <= bit_idx + 1;
+                        end
+                    end else begin
+                        baud_cnt <= baud_cnt + 1;
+                    end
+                end
+
+                STOP: begin
+                    tx <= 1'b1;
+                    if (baud_cnt == 16'(CLKS_PER_BIT - 1)) begin
+                        state    <= IDLE;
+                        baud_cnt <= '0;
+                    end else begin
+                        baud_cnt <= baud_cnt + 1;
+                    end
+                end
+
+                default: state <= IDLE;
+            endcase
+        end
+    end
+
+endmodule