sia-script 1.0.2__tar.gz → 1.0.3__tar.gz

{sia_script-1.0.2/sia_script.egg-info → sia_script-1.0.3}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: sia-script
-Version: 1.0.2
+Version: 1.0.3
 Summary: SIA — Simplified Integrated Architecture: SiaNTT, SIA-ELS (ABAP interpreter), the HDQS server client, and hdqs_engine (offline statevector quantum simulator — no server or API token required)
 Author-email: Sia Software Innovations Private Limited <info@siasoftwareinnovations.com>
 License: # PROPRIETARY SOFTWARE LICENSE

{sia_script-1.0.2 → sia_script-1.0.3}/pyproject.toml

@@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "sia-script"
-version = "1.0.2"
+version = "1.0.3"
 description = "SIA — Simplified Integrated Architecture: SiaNTT, SIA-ELS (ABAP interpreter), the HDQS server client, and hdqs_engine (offline statevector quantum simulator — no server or API token required)"
 authors = [
     { name = "Sia Software Innovations Private Limited", email = "info@siasoftwareinnovations.com" }

sia_script-1.0.3/setup.py

@@ -0,0 +1,60 @@
+"""
+Build script for the sia-script native extension (hdqs_core).
+
+This compiles src/hdqs_core.cpp into sia/hdqs_core.<platform-tag>.so via
+pybind11 -- the same mechanism Qiskit Aer and PennyLane's lightning.qubit
+use (a thin Python package wrapping a compiled kernel).
+
+Local development build:
+    pip install pybind11
+    python setup.py build_ext --inplace
+
+This places the compiled module directly in sia/, where hdqs_engine.py's
+`from . import hdqs_core` picks it up automatically. If the build fails or
+is skipped, hdqs_engine.py still works -- it falls back to the pure NumPy
+path and sets _NATIVE_AVAILABLE = False.
+"""
+import sys
+from setuptools import setup, Extension
+from pybind11.setup_helpers import Pybind11Extension, build_ext
+
+# -O3 for standard optimization. -march=native/-mavx2/-mavx512f are
+# deliberately NOT used here, and no longer need to be: hdqs_core.cpp
+# now does its own runtime CPU dispatch (GCC/Clang function
+# multiversioning + __builtin_cpu_supports, checked once at first call)
+# for the four hottest kernels. This one build, compiled with these
+# plain flags, contains scalar/AVX2/AVX-512 code paths simultaneously
+# and picks the fastest one the *running* CPU actually supports --
+# verified: compiled with zero SIMD flags, still dispatches to AVX-512
+# on an AVX-512-capable machine, at the same speed as an explicitly
+# -mavx512f-flagged build. No crash risk on older CPUs, no separate
+# "fast" build needed. (This applies to GCC/Clang on x86_64 --  MSVC/
+# Windows builds don't yet get automatic dispatch and fall back to the
+# single compile-time path, i.e. scalar unless /arch:AVX2 is passed
+# explicitly -- a known, stated gap, not a regression from before.)
+extra_compile_args = ["-O3", "-std=c++17"]
+extra_link_args = []
+
+if sys.platform == "win32":
+    extra_compile_args = ["/O2", "/std:c++17", "/openmp"]
+else:
+    extra_compile_args += ["-fopenmp"]
+    extra_link_args += ["-fopenmp"]
+
+ext_modules = [
+    Pybind11Extension(
+        "sia.hdqs_core",
+        ["src/hdqs_core.cpp"],
+        cxx_std=17,
+        extra_compile_args=extra_compile_args,
+        extra_link_args=extra_link_args,
+    ),
+]
+
+setup(
+    packages=["sia"],
+    package_dir={"sia": "sia"},
+    ext_modules=ext_modules,
+    cmdclass={"build_ext": build_ext},
+    zip_safe=False,
+)

{sia_script-1.0.2 → sia_script-1.0.3/sia_script.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: sia-script
-Version: 1.0.2
+Version: 1.0.3
 Summary: SIA — Simplified Integrated Architecture: SiaNTT, SIA-ELS (ABAP interpreter), the HDQS server client, and hdqs_engine (offline statevector quantum simulator — no server or API token required)
 Author-email: Sia Software Innovations Private Limited <info@siasoftwareinnovations.com>
 License: # PROPRIETARY SOFTWARE LICENSE

{sia_script-1.0.2 → sia_script-1.0.3}/src/hdqs_core.cpp

@@ -1,13 +1,32 @@
 // hdqs_core.cpp — generalized native kernels for HDQS.
 //
-// Phase 1: apply_gate — a single, fully general statevector kernel that
-//   replaces both the plain-unitary and controlled-unitary NumPy paths.
-//   Handles arbitrary target-qubit count and arbitrary positive-control
-//   count in one routine, using the standard bit-scatter algorithm used
-//   by production statevector simulators.
+// Runtime CPU dispatch: the four hottest kernels (apply_1q,
+// apply_cnot_fast, apply_controlled_1q, apply_swap) are each compiled
+// in three ISA-specific variants -- scalar, AVX2+FMA, AVX-512F+FMA --
+// inside a single binary, using per-function __attribute__((target(...)))
+// (GCC/Clang function multiversioning). Which variant actually runs is
+// decided once, at first call, by checking the *running* CPU's features
+// via __builtin_cpu_supports -- not by which flags the file happened to
+// be compiled with. This is what lets one published wheel be fast on a
+// machine with AVX-512, fast (one tier down) on a machine with only
+// AVX2, and still correct (just slower) on a machine with neither,
+// without ever risking an "illegal instruction" crash from running
+// AVX-512 code on a CPU that doesn't have it -- the dispatcher only
+// picks a tier the CPU actually reports supporting.
 //
-// Phase 4: apply_kraus_1q — single-qubit Kraus-channel application on a
-//   density matrix, for the noise-channel fast path.
+// Platform note: this technique (__attribute__((target(...))) +
+// __builtin_cpu_supports) is GCC/Clang-specific and validated on Linux
+// x86_64 in this session. MSVC has no equivalent for mixing ISA levels
+// within one translation unit the same way; on an MSVC build, these
+// four kernels fall back to the single compile-time-selected path
+// (scalar unless the build explicitly passes /arch:AVX2, exactly as
+// before this change) -- see _DISPATCH_AVAILABLE below. This is a real,
+// stated gap, not silently glossed over: Windows wheels do not yet get
+// automatic runtime dispatch.
+//
+// apply_gate, apply_kraus_1q, and apply_gate_fast (the less-hot general
+// fallback paths) are unchanged from the compile-time-flag scheme --
+// runtime dispatch on those is a smaller win and out of scope here.
 #include <pybind11/pybind11.h>
 #include <pybind11/numpy.h>
 #include <pybind11/stl.h>
@@ -16,7 +35,7 @@
 #include <algorithm>
 #include <cstdint>
 #include <stdexcept>
-#if defined(__AVX2__) || defined(__AVX512F__)
+#if defined(__x86_64__) || defined(_M_X64) || defined(__i386__) || defined(_M_IX86)
 #include <immintrin.h>
 #endif
 #if defined(_OPENMP)
@@ -26,15 +45,15 @@
 namespace py = pybind11;
 using cplx = std::complex<double>;
 
-// OpenMP's parallel-region entry has real fixed overhead per call, even
-// with schedule(static) and even with a single thread. Measured directly
-// on this session's test hardware (1 core): #pragma omp parallel for was
-// slower than a plain serial loop at *every* block size tested, because
-// there was never more than one thread to spread work across. Guarding
-// every pragma with this check means we only pay that overhead when a
-// second thread could actually pick up work -- correct and safe on both
-// single-core and multi-core hardware, since it never disables real
-// parallelism, only avoids paying for parallelism that can't happen.
+// GCC and Clang both define __GNUC__ (Clang for compatibility) and both
+// support __attribute__((target(...))) + __builtin_cpu_supports on x86
+// with the same syntax -- this one check covers both compilers.
+#if defined(__GNUC__) && (defined(__x86_64__) || defined(__i386__))
+#define _DISPATCH_AVAILABLE 1
+#else
+#define _DISPATCH_AVAILABLE 0
+#endif
+
 static inline bool _omp_worth_it() {
 #if defined(_OPENMP)
     static const bool worth_it = (omp_get_max_threads() > 1);
@@ -44,6 +63,24 @@ static inline bool _omp_worth_it() {
 #endif
 }
 
+// 0 = scalar only, 1 = AVX2+FMA available, 2 = AVX-512F+FMA available.
+// Computed once (the CPUID check itself has real cost -- cache it).
+static inline int _cpu_tier() {
+#if _DISPATCH_AVAILABLE
+    static const int tier = [] {
+        __builtin_cpu_init();
+        if (__builtin_cpu_supports("avx512f") && __builtin_cpu_supports("fma"))
+            return 2;
+        if (__builtin_cpu_supports("avx2") && __builtin_cpu_supports("fma"))
+            return 1;
+        return 0;
+    }();
+    return tier;
+#else
+    return 0;
+#endif
+}
+
 // Scatter the bits of `value` into `positions` (given LSB-first), leaving
 // all other bits as given by `skeleton`.
 static inline int64_t scatter_bits(int64_t skeleton,
@@ -56,27 +93,16 @@ static inline int64_t scatter_bits(int64_t skeleton,
     return idx;
 }
 
-// -- Fast paths: single-qubit gate and CNOT, via contiguous-block ---------
-// -- iteration. These are what h/x/y/z/rx/ry/rz/p/u3/cnot route through --
-// -- from HDQS -- validated to auto-vectorize (confirmed via GCC's -----
-// -- -fopt-info-vec-optimized) and to match NumPy's BLAS-backed speed on -
-// -- a single gate, ~2.5-3.4x faster than Aer on H/RY/CNOT-only circuits -
-// -- (measured single-threaded). apply_gate above remains the fallback --
-// -- for every other gate shape (multi-qubit, multi-control). -----------
-
-#if defined(__AVX2__)
-// Complex multiplication via the standard "addsub" trick: packs 2
-// complex doubles per __m256d and computes both products in one shot
-// using shuffle + mul + addsub, operating directly on the interleaved
-// std::complex<double> memory layout (no separate real/imag arrays).
-// Measured ~2.9-3.6x faster than the scalar loop on realistic mixed-
-// bit-position circuits (the auto-vectorizer could get partial credit
-// on the block-iteration structure, per -fopt-info-vec, but never the
-// complex multiply itself -- "no vectype for stmt" on the arithmetic).
+#if _DISPATCH_AVAILABLE
+// -- AVX2 helpers: compiled with AVX2 codegen regardless of the file's
+// -- default -march setting, via the target attribute. Complex multiply
+// -- via the "addsub" trick, as validated earlier this session.
+__attribute__((target("avx2,fma")))
 static inline __m256d _bcast_complex(cplx c) {
     return _mm256_setr_pd(c.real(), c.imag(), c.real(), c.imag());
 }
 
+__attribute__((target("avx2,fma")))
 static inline __m256d _complex_mul(__m256d a, __m256d b) {
     __m256d b_re = _mm256_shuffle_pd(b, b, 0x0);
     __m256d b_im = _mm256_shuffle_pd(b, b, 0xF);
@@ -85,23 +111,15 @@ static inline __m256d _complex_mul(__m256d a, __m256d b) {
     __m256d t2 = _mm256_mul_pd(a_swap, b_im);
     return _mm256_addsub_pd(t1, t2);
 }
-#endif
 
-#if defined(__AVX512F__)
-// AVX-512 packs 4 complex doubles per __m512d. AVX-512 has no native
-// 512-bit addsub instruction (unlike AVX2 at 256-bit), so a naive
-// port (mul + mask-blend) measured *slower* than AVX2 -- the extra
-// blend instruction outweighed the wider register. Using fmaddsub
-// instead (native on AVX-512, fuses the multiply and the alternating
-// add/sub into one instruction) recovers the win: ~1.18-1.21x faster
-// than AVX2 at n>=16, roughly tied below that. Pre-splitting each
-// gate-matrix entry into separate re/im broadcast constants (outside
-// the hot loop, once per gate call) avoids repeating that shuffle
-// 4 times per inner-loop iteration.
+// -- AVX-512 helpers: fmaddsub-based, as validated (naive mul+blend
+// -- measured slower than AVX2, this recovers the win).
+__attribute__((target("avx512f,fma")))
 static inline __m512d _bcast_complex512(cplx c) {
     return _mm512_set4_pd(c.imag(), c.real(), c.imag(), c.real());
 }
 
+__attribute__((target("avx512f,fma")))
 static inline __m512d _complex_mul_fma512(__m512d a, __m512d b_re,
                                           __m512d b_im, __m512d a_swap) {
     __m512d t2 = _mm512_mul_pd(a_swap, b_im);
@@ -109,53 +127,67 @@ static inline __m512d _complex_mul_fma512(__m512d a, __m512d b_re,
 }
 #endif
 
-// Single-qubit gate: splits the statevector into contiguous blocks of
-// size 2^bitpos; within each block the two halves being combined are
-// adjacent in memory. Three-tier dispatch at compile time: AVX-512
-// (4 amplitude pairs/iteration) -> AVX2 (2 pairs/iteration) -> portable
-// scalar loop (still auto-vectorizes partially via the compiler).
-void apply_1q(py::array_t<cplx, py::array::c_style | py::array::forcecast> state,
-              int bitpos, cplx u00, cplx u01, cplx u10, cplx u11) {
-    auto buf = state.request();
-    cplx* sv = static_cast<cplx*>(buf.ptr);
-    int64_t dim = buf.shape[0];
-    int64_t block = int64_t(1) << bitpos;
+// ---------------------------------------------------------------------
+// apply_1q: single-qubit gate via contiguous-block iteration.
+// ---------------------------------------------------------------------
+
+static void _apply_1q_scalar(cplx* sv, int64_t dim, int64_t block,
+                             cplx u00, cplx u01, cplx u10, cplx u11) {
     int64_t num_blocks = dim / (2 * block);
+    #pragma omp parallel for schedule(static) if(_omp_worth_it())
+    for (int64_t blk = 0; blk < num_blocks; blk++) {
+        int64_t base = blk * 2 * block;
+        cplx* p0 = sv + base;
+        cplx* p1 = sv + base + block;
+        for (int64_t j = 0; j < block; j++) {
+            cplx a0 = p0[j], a1 = p1[j];
+            p0[j] = u00 * a0 + u01 * a1;
+            p1[j] = u10 * a0 + u11 * a1;
+        }
+    }
+}
 
-    // Small blocks can't fill even one SIMD-width iteration, so the
-    // "vectorized" path would only ever run its scalar tail anyway --
-    // skip building the SIMD constants (broadcasts + shuffles) entirely
-    // rather than paying that setup for zero benefit. Measured this as
-    // a real, if partial, fix for a >3x slowdown at tiny block sizes
-    // that persisted even with OpenMP removed entirely from the build,
-    // so the remaining effect (still ~2.5x versus large-block calls) is
-    // not fully understood -- flagging honestly rather than claiming
-    // this fully explains it. A per-iteration loop-overhead effect
-    // scaling with num_blocks (up to 2^(n-1) for bitpos=0) is the
-    // leading remaining hypothesis, not yet confirmed.
-    if (block < 4) {
-        #pragma omp parallel for schedule(static) if(_omp_worth_it())
-        for (int64_t blk = 0; blk < num_blocks; blk++) {
-            int64_t base = blk * 2 * block;
-            cplx* p0 = sv + base;
-            cplx* p1 = sv + base + block;
-            for (int64_t j = 0; j < block; j++) {
-                cplx a0 = p0[j], a1 = p1[j];
-                p0[j] = u00 * a0 + u01 * a1;
-                p1[j] = u10 * a0 + u11 * a1;
-            }
+#if _DISPATCH_AVAILABLE
+__attribute__((target("avx2,fma")))
+static void _apply_1q_avx2(cplx* sv, int64_t dim, int64_t block,
+                           cplx u00, cplx u01, cplx u10, cplx u11) {
+    int64_t num_blocks = dim / (2 * block);
+    if (block < 4) { _apply_1q_scalar(sv, dim, block, u00, u01, u10, u11); return; }
+    __m256d U00 = _bcast_complex(u00), U01 = _bcast_complex(u01);
+    __m256d U10 = _bcast_complex(u10), U11 = _bcast_complex(u11);
+    #pragma omp parallel for schedule(static) if(_omp_worth_it())
+    for (int64_t blk = 0; blk < num_blocks; blk++) {
+        int64_t base = blk * 2 * block;
+        double* p0 = reinterpret_cast<double*>(sv + base);
+        double* p1 = reinterpret_cast<double*>(sv + base + block);
+        int64_t j = 0;
+        for (; j + 2 <= block; j += 2) {
+            __m256d a0 = _mm256_loadu_pd(p0 + 2 * j);
+            __m256d a1 = _mm256_loadu_pd(p1 + 2 * j);
+            __m256d new_p0 = _mm256_add_pd(_complex_mul(a0, U00), _complex_mul(a1, U01));
+            __m256d new_p1 = _mm256_add_pd(_complex_mul(a0, U10), _complex_mul(a1, U11));
+            _mm256_storeu_pd(p0 + 2 * j, new_p0);
+            _mm256_storeu_pd(p1 + 2 * j, new_p1);
+        }
+        for (; j < block; j++) {
+            cplx a0v = sv[base + j], a1v = sv[base + block + j];
+            sv[base + j] = u00 * a0v + u01 * a1v;
+            sv[base + block + j] = u10 * a0v + u11 * a1v;
         }
-        return;
     }
+}
 
-#if defined(__AVX512F__)
+__attribute__((target("avx512f,fma")))
+static void _apply_1q_avx512(cplx* sv, int64_t dim, int64_t block,
+                             cplx u00, cplx u01, cplx u10, cplx u11) {
+    int64_t num_blocks = dim / (2 * block);
+    if (block < 4) { _apply_1q_scalar(sv, dim, block, u00, u01, u10, u11); return; }
     __m512d U00 = _bcast_complex512(u00), U01 = _bcast_complex512(u01);
     __m512d U10 = _bcast_complex512(u10), U11 = _bcast_complex512(u11);
     __m512d U00re = _mm512_shuffle_pd(U00, U00, 0x00), U00im = _mm512_shuffle_pd(U00, U00, 0xFF);
     __m512d U01re = _mm512_shuffle_pd(U01, U01, 0x00), U01im = _mm512_shuffle_pd(U01, U01, 0xFF);
     __m512d U10re = _mm512_shuffle_pd(U10, U10, 0x00), U10im = _mm512_shuffle_pd(U10, U10, 0xFF);
     __m512d U11re = _mm512_shuffle_pd(U11, U11, 0x00), U11im = _mm512_shuffle_pd(U11, U11, 0xFF);
-
     #pragma omp parallel for schedule(static) if(_omp_worth_it())
     for (int64_t blk = 0; blk < num_blocks; blk++) {
         int64_t base = blk * 2 * block;
@@ -180,81 +212,58 @@ void apply_1q(py::array_t<cplx, py::array::c_style | py::array::forcecast> state
             sv[base + block + j] = u10 * a0v + u11 * a1v;
         }
     }
-#elif defined(__AVX2__)
-    __m256d U00 = _bcast_complex(u00), U01 = _bcast_complex(u01);
-    __m256d U10 = _bcast_complex(u10), U11 = _bcast_complex(u11);
-
-    #pragma omp parallel for schedule(static) if(_omp_worth_it())
-    for (int64_t blk = 0; blk < num_blocks; blk++) {
-        int64_t base = blk * 2 * block;
-        double* p0 = reinterpret_cast<double*>(sv + base);
-        double* p1 = reinterpret_cast<double*>(sv + base + block);
-        int64_t j = 0;
-        for (; j + 2 <= block; j += 2) {
-            __m256d a0 = _mm256_loadu_pd(p0 + 2 * j);
-            __m256d a1 = _mm256_loadu_pd(p1 + 2 * j);
-            __m256d new_p0 = _mm256_add_pd(_complex_mul(a0, U00), _complex_mul(a1, U01));
-            __m256d new_p1 = _mm256_add_pd(_complex_mul(a0, U10), _complex_mul(a1, U11));
-            _mm256_storeu_pd(p0 + 2 * j, new_p0);
-            _mm256_storeu_pd(p1 + 2 * j, new_p1);
-        }
-        for (; j < block; j++) {
-            cplx a0v = sv[base + j], a1v = sv[base + block + j];
-            sv[base + j] = u00 * a0v + u01 * a1v;
-            sv[base + block + j] = u10 * a0v + u11 * a1v;
-        }
-    }
-#else
-    #pragma omp parallel for schedule(static) if(_omp_worth_it())
-    for (int64_t blk = 0; blk < num_blocks; blk++) {
-        int64_t base = blk * 2 * block;
-        cplx* p0 = sv + base;
-        cplx* p1 = sv + base + block;
-        for (int64_t j = 0; j < block; j++) {
-            cplx a0 = p0[j], a1 = p1[j];
-            p0[j] = u00 * a0 + u01 * a1;
-            p1[j] = u10 * a0 + u11 * a1;
-        }
-    }
-#endif
 }
+#endif
 
-// CNOT: a 3-region split (below/between/above the two bit positions) so
-// the innermost loop -- the swap over the bits below both control and
-// target -- stays contiguous regardless of which of the two is larger.
-// AVX2 path: swaps 2 amplitude pairs per iteration via wide load/store
-// (pure data movement, no arithmetic, so this is close to free once
-// vectorized -- the win is fewer, wider memory transactions).
-void apply_cnot_fast(py::array_t<cplx, py::array::c_style | py::array::forcecast> state,
-                     int control_bitpos, int target_bitpos) {
+void apply_1q(py::array_t<cplx, py::array::c_style | py::array::forcecast> state,
+              int bitpos, cplx u00, cplx u01, cplx u10, cplx u11) {
     auto buf = state.request();
     cplx* sv = static_cast<cplx*>(buf.ptr);
     int64_t dim = buf.shape[0];
-    int lo = std::min(control_bitpos, target_bitpos);
-    int hi = std::max(control_bitpos, target_bitpos);
-    int64_t lo_bit = int64_t(1) << lo;
-    int64_t cbit = int64_t(1) << control_bitpos, tbit = int64_t(1) << target_bitpos;
+    int64_t block = int64_t(1) << bitpos;
+
+#if _DISPATCH_AVAILABLE
+    int tier = _cpu_tier();
+    if (tier >= 2) { _apply_1q_avx512(sv, dim, block, u00, u01, u10, u11); return; }
+    if (tier >= 1) { _apply_1q_avx2(sv, dim, block, u00, u01, u10, u11); return; }
+#endif
+    _apply_1q_scalar(sv, dim, block, u00, u01, u10, u11);
+}
+
+// ---------------------------------------------------------------------
+// apply_cnot_fast: pure data movement, no arithmetic -- same dispatch.
+// ---------------------------------------------------------------------
 
+static void _apply_cnot_scalar(cplx* sv, int64_t dim, int lo, int hi,
+                               int64_t lo_bit, int64_t cbit, int64_t tbit) {
     int64_t n_outer = dim >> (hi + 1);
     int64_t n_mid = int64_t(1) << (hi - lo - 1);
+    #pragma omp parallel for collapse(2) schedule(static) if(_omp_worth_it())
+    for (int64_t outer = 0; outer < n_outer; outer++) {
+        for (int64_t mid = 0; mid < n_mid; mid++) {
+            int64_t skeleton = (outer << (hi + 1)) | (mid << (lo + 1));
+            cplx* p0 = sv + skeleton + cbit;
+            cplx* p1 = p0 + tbit;
+            for (int64_t j = 0; j < lo_bit; j++) std::swap(p0[j], p1[j]);
+        }
+    }
+}
 
+#if _DISPATCH_AVAILABLE
+__attribute__((target("avx2,fma")))
+static void _apply_cnot_avx2(cplx* sv, int64_t dim, int lo, int hi,
+                             int64_t lo_bit, int64_t cbit, int64_t tbit) {
+    int64_t n_outer = dim >> (hi + 1);
+    int64_t n_mid = int64_t(1) << (hi - lo - 1);
     #pragma omp parallel for collapse(2) schedule(static) if(_omp_worth_it())
     for (int64_t outer = 0; outer < n_outer; outer++) {
         for (int64_t mid = 0; mid < n_mid; mid++) {
             int64_t skeleton = (outer << (hi + 1)) | (mid << (lo + 1));
-            cplx* base = sv + skeleton + cbit;
-            cplx* p0 = base;
-            cplx* p1 = base + tbit;
-#if defined(__AVX512F__)
+            cplx* p0 = sv + skeleton + cbit;
+            cplx* p1 = p0 + tbit;
             double* d0 = reinterpret_cast<double*>(p0);
             double* d1 = reinterpret_cast<double*>(p1);
             int64_t j = 0;
-            for (; j + 4 <= lo_bit; j += 4) {
-                __m512d a = _mm512_loadu_pd(d0 + 2 * j);
-                __m512d b = _mm512_loadu_pd(d1 + 2 * j);
-                _mm512_storeu_pd(d0 + 2 * j, b);
-                _mm512_storeu_pd(d1 + 2 * j, a);
-            }
             for (; j + 2 <= lo_bit; j += 2) {
                 __m256d a = _mm256_loadu_pd(d0 + 2 * j);
                 __m256d b = _mm256_loadu_pd(d1 + 2 * j);
@@ -262,10 +271,30 @@ void apply_cnot_fast(py::array_t<cplx, py::array::c_style | py::array::forcecast
                 _mm256_storeu_pd(d1 + 2 * j, a);
             }
             for (; j < lo_bit; j++) std::swap(p0[j], p1[j]);
-#elif defined(__AVX2__)
+        }
+    }
+}
+
+__attribute__((target("avx512f,fma")))
+static void _apply_cnot_avx512(cplx* sv, int64_t dim, int lo, int hi,
+                               int64_t lo_bit, int64_t cbit, int64_t tbit) {
+    int64_t n_outer = dim >> (hi + 1);
+    int64_t n_mid = int64_t(1) << (hi - lo - 1);
+    #pragma omp parallel for collapse(2) schedule(static) if(_omp_worth_it())
+    for (int64_t outer = 0; outer < n_outer; outer++) {
+        for (int64_t mid = 0; mid < n_mid; mid++) {
+            int64_t skeleton = (outer << (hi + 1)) | (mid << (lo + 1));
+            cplx* p0 = sv + skeleton + cbit;
+            cplx* p1 = p0 + tbit;
             double* d0 = reinterpret_cast<double*>(p0);
             double* d1 = reinterpret_cast<double*>(p1);
             int64_t j = 0;
+            for (; j + 4 <= lo_bit; j += 4) {
+                __m512d a = _mm512_loadu_pd(d0 + 2 * j);
+                __m512d b = _mm512_loadu_pd(d1 + 2 * j);
+                _mm512_storeu_pd(d0 + 2 * j, b);
+                _mm512_storeu_pd(d1 + 2 * j, a);
+            }
             for (; j + 2 <= lo_bit; j += 2) {
                 __m256d a = _mm256_loadu_pd(d0 + 2 * j);
                 __m256d b = _mm256_loadu_pd(d1 + 2 * j);
@@ -273,12 +302,28 @@ void apply_cnot_fast(py::array_t<cplx, py::array::c_style | py::array::forcecast
                 _mm256_storeu_pd(d1 + 2 * j, a);
             }
             for (; j < lo_bit; j++) std::swap(p0[j], p1[j]);
-#else
-            for (int64_t j = 0; j < lo_bit; j++) std::swap(p0[j], p1[j]);
-#endif
         }
     }
 }
+#endif
+
+void apply_cnot_fast(py::array_t<cplx, py::array::c_style | py::array::forcecast> state,
+                     int control_bitpos, int target_bitpos) {
+    auto buf = state.request();
+    cplx* sv = static_cast<cplx*>(buf.ptr);
+    int64_t dim = buf.shape[0];
+    int lo = std::min(control_bitpos, target_bitpos);
+    int hi = std::max(control_bitpos, target_bitpos);
+    int64_t lo_bit = int64_t(1) << lo;
+    int64_t cbit = int64_t(1) << control_bitpos, tbit = int64_t(1) << target_bitpos;
+
+#if _DISPATCH_AVAILABLE
+    int tier = _cpu_tier();
+    if (tier >= 2) { _apply_cnot_avx512(sv, dim, lo, hi, lo_bit, cbit, tbit); return; }
+    if (tier >= 1) { _apply_cnot_avx2(sv, dim, lo, hi, lo_bit, cbit, tbit); return; }
+#endif
+    _apply_cnot_scalar(sv, dim, lo, hi, lo_bit, cbit, tbit);
+}
 
 // General statevector gate application.
 //
@@ -390,68 +435,92 @@ void apply_kraus_1q(py::array_t<cplx, py::array::c_style | py::array::forcecast>
     }
     for (int64_t i = 0; i < dim*dim; i++) R[i] = new_rho[i];
 }
-
-// Generalizes apply_cnot_fast to an arbitrary 2x2 unitary on the target
-// qubit, conditioned on one control. Covers cx/cy/cz/cp/crx/cry/crz --
-// the entire single-control single-target gate family -- with the same
-// 3-region contiguous-block technique. AVX2 path reuses _complex_mul,
-// same pattern as apply_1q's inner loop.
-void apply_controlled_1q(py::array_t<cplx, py::array::c_style | py::array::forcecast> state,
-                         int control_bitpos, int target_bitpos,
-                         cplx u00, cplx u01, cplx u10, cplx u11) {
-    auto buf = state.request();
-    cplx* sv = static_cast<cplx*>(buf.ptr);
-    int64_t dim = buf.shape[0];
-    int lo = std::min(control_bitpos, target_bitpos);
-    int hi = std::max(control_bitpos, target_bitpos);
-    int64_t lo_bit = int64_t(1) << lo;
-    int64_t cbit = int64_t(1) << control_bitpos, tbit = int64_t(1) << target_bitpos;
-
+// ---------------------------------------------------------------------
+// apply_controlled_1q: single-control single-target gate (cx/cy/cz/cp/
+// crx/cry/crz), same dispatch pattern as apply_1q.
+// ---------------------------------------------------------------------
+
+static void _apply_c1q_scalar(cplx* sv, int64_t dim, int lo, int hi,
+                              int64_t lo_bit, int64_t cbit, int64_t tbit,
+                              cplx u00, cplx u01, cplx u10, cplx u11) {
     int64_t n_outer = dim >> (hi + 1);
     int64_t n_mid = int64_t(1) << (hi - lo - 1);
+    #pragma omp parallel for collapse(2) schedule(static) if(_omp_worth_it())
+    for (int64_t outer = 0; outer < n_outer; outer++) {
+        for (int64_t mid = 0; mid < n_mid; mid++) {
+            int64_t skeleton = (outer << (hi + 1)) | (mid << (lo + 1));
+            cplx* p0 = sv + skeleton + cbit;
+            cplx* p1 = p0 + tbit;
+            for (int64_t j = 0; j < lo_bit; j++) {
+                cplx a0 = p0[j], a1 = p1[j];
+                p0[j] = u00 * a0 + u01 * a1;
+                p1[j] = u10 * a0 + u11 * a1;
+            }
+        }
+    }
+}
 
-    // Same rationale as apply_1q: skip SIMD constant setup entirely
-    // when the block is too small to fill even one vector-width
-    // iteration -- see apply_1q's comment for the measured effect and
-    // the honestly-flagged residual, not-fully-understood slowdown.
+#if _DISPATCH_AVAILABLE
+__attribute__((target("avx2,fma")))
+static void _apply_c1q_avx2(cplx* sv, int64_t dim, int lo, int hi,
+                            int64_t lo_bit, int64_t cbit, int64_t tbit,
+                            cplx u00, cplx u01, cplx u10, cplx u11) {
     if (lo_bit < 4) {
-        #pragma omp parallel for collapse(2) schedule(static) if(_omp_worth_it())
-        for (int64_t outer = 0; outer < n_outer; outer++) {
-            for (int64_t mid = 0; mid < n_mid; mid++) {
-                int64_t skeleton = (outer << (hi + 1)) | (mid << (lo + 1));
-                cplx* base = sv + skeleton + cbit;
-                cplx* p0 = base;
-                cplx* p1 = base + tbit;
-                for (int64_t j = 0; j < lo_bit; j++) {
-                    cplx a0 = p0[j], a1 = p1[j];
-                    p0[j] = u00 * a0 + u01 * a1;
-                    p1[j] = u10 * a0 + u11 * a1;
-                }
+        _apply_c1q_scalar(sv, dim, lo, hi, lo_bit, cbit, tbit, u00, u01, u10, u11);
+        return;
+    }
+    int64_t n_outer = dim >> (hi + 1);
+    int64_t n_mid = int64_t(1) << (hi - lo - 1);
+    __m256d U00 = _bcast_complex(u00), U01 = _bcast_complex(u01);
+    __m256d U10 = _bcast_complex(u10), U11 = _bcast_complex(u11);
+    #pragma omp parallel for collapse(2) schedule(static) if(_omp_worth_it())
+    for (int64_t outer = 0; outer < n_outer; outer++) {
+        for (int64_t mid = 0; mid < n_mid; mid++) {
+            int64_t skeleton = (outer << (hi + 1)) | (mid << (lo + 1));
+            cplx* p0 = sv + skeleton + cbit;
+            cplx* p1 = p0 + tbit;
+            double* d0 = reinterpret_cast<double*>(p0);
+            double* d1 = reinterpret_cast<double*>(p1);
+            int64_t j = 0;
+            for (; j + 2 <= lo_bit; j += 2) {
+                __m256d a0 = _mm256_loadu_pd(d0 + 2 * j);
+                __m256d a1 = _mm256_loadu_pd(d1 + 2 * j);
+                __m256d new_p0 = _mm256_add_pd(_complex_mul(a0, U00), _complex_mul(a1, U01));
+                __m256d new_p1 = _mm256_add_pd(_complex_mul(a0, U10), _complex_mul(a1, U11));
+                _mm256_storeu_pd(d0 + 2 * j, new_p0);
+                _mm256_storeu_pd(d1 + 2 * j, new_p1);
+            }
+            for (; j < lo_bit; j++) {
+                cplx a0v = p0[j], a1v = p1[j];
+                p0[j] = u00 * a0v + u01 * a1v;
+                p1[j] = u10 * a0v + u11 * a1v;
             }
         }
-        return;
     }
+}
 
-#if defined(__AVX512F__)
+__attribute__((target("avx512f,fma")))
+static void _apply_c1q_avx512(cplx* sv, int64_t dim, int lo, int hi,
+                              int64_t lo_bit, int64_t cbit, int64_t tbit,
+                              cplx u00, cplx u01, cplx u10, cplx u11) {
+    if (lo_bit < 4) {
+        _apply_c1q_scalar(sv, dim, lo, hi, lo_bit, cbit, tbit, u00, u01, u10, u11);
+        return;
+    }
+    int64_t n_outer = dim >> (hi + 1);
+    int64_t n_mid = int64_t(1) << (hi - lo - 1);
     __m512d U00 = _bcast_complex512(u00), U01 = _bcast_complex512(u01);
     __m512d U10 = _bcast_complex512(u10), U11 = _bcast_complex512(u11);
     __m512d U00re = _mm512_shuffle_pd(U00, U00, 0x00), U00im = _mm512_shuffle_pd(U00, U00, 0xFF);
     __m512d U01re = _mm512_shuffle_pd(U01, U01, 0x00), U01im = _mm512_shuffle_pd(U01, U01, 0xFF);
     __m512d U10re = _mm512_shuffle_pd(U10, U10, 0x00), U10im = _mm512_shuffle_pd(U10, U10, 0xFF);
     __m512d U11re = _mm512_shuffle_pd(U11, U11, 0x00), U11im = _mm512_shuffle_pd(U11, U11, 0xFF);
-#elif defined(__AVX2__)
-    __m256d U00 = _bcast_complex(u00), U01 = _bcast_complex(u01);
-    __m256d U10 = _bcast_complex(u10), U11 = _bcast_complex(u11);
-#endif
-
     #pragma omp parallel for collapse(2) schedule(static) if(_omp_worth_it())
     for (int64_t outer = 0; outer < n_outer; outer++) {
         for (int64_t mid = 0; mid < n_mid; mid++) {
             int64_t skeleton = (outer << (hi + 1)) | (mid << (lo + 1));
-            cplx* base = sv + skeleton + cbit;  // force control = 1
-            cplx* p0 = base;
-            cplx* p1 = base + tbit;
-#if defined(__AVX512F__)
+            cplx* p0 = sv + skeleton + cbit;
+            cplx* p1 = p0 + tbit;
             double* d0 = reinterpret_cast<double*>(p0);
             double* d1 = reinterpret_cast<double*>(p1);
             int64_t j = 0;
@@ -472,67 +541,65 @@ void apply_controlled_1q(py::array_t<cplx, py::array::c_style | py::array::force
                 p0[j] = u00 * a0v + u01 * a1v;
                 p1[j] = u10 * a0v + u11 * a1v;
             }
-#elif defined(__AVX2__)
-            double* d0 = reinterpret_cast<double*>(p0);
-            double* d1 = reinterpret_cast<double*>(p1);
-            int64_t j = 0;
-            for (; j + 2 <= lo_bit; j += 2) {
-                __m256d a0 = _mm256_loadu_pd(d0 + 2 * j);
-                __m256d a1 = _mm256_loadu_pd(d1 + 2 * j);
-                __m256d new_p0 = _mm256_add_pd(_complex_mul(a0, U00), _complex_mul(a1, U01));
-                __m256d new_p1 = _mm256_add_pd(_complex_mul(a0, U10), _complex_mul(a1, U11));
-                _mm256_storeu_pd(d0 + 2 * j, new_p0);
-                _mm256_storeu_pd(d1 + 2 * j, new_p1);
-            }
-            for (; j < lo_bit; j++) {
-                cplx a0v = p0[j], a1v = p1[j];
-                p0[j] = u00 * a0v + u01 * a1v;
-                p1[j] = u10 * a0v + u11 * a1v;
-            }
-#else
-            for (int64_t j = 0; j < lo_bit; j++) {
-                cplx a0 = p0[j], a1 = p1[j];
-                p0[j] = u00 * a0 + u01 * a1;
-                p1[j] = u10 * a0 + u11 * a1;
-            }
-#endif
         }
     }
 }
+#endif
 
-// SWAP: exchanges two qubits' amplitude pairs. Same 3-region split; the
-// innermost loop is a plain swap, no arithmetic. AVX2 path swaps 2
-// pairs per iteration via wide load/store, same technique as
-// apply_cnot_fast.
-void apply_swap(py::array_t<cplx, py::array::c_style | py::array::forcecast> state,
-                int bitpos_a, int bitpos_b) {
+void apply_controlled_1q(py::array_t<cplx, py::array::c_style | py::array::forcecast> state,
+                         int control_bitpos, int target_bitpos,
+                         cplx u00, cplx u01, cplx u10, cplx u11) {
     auto buf = state.request();
     cplx* sv = static_cast<cplx*>(buf.ptr);
     int64_t dim = buf.shape[0];
-    int lo = std::min(bitpos_a, bitpos_b);
-    int hi = std::max(bitpos_a, bitpos_b);
+    int lo = std::min(control_bitpos, target_bitpos);
+    int hi = std::max(control_bitpos, target_bitpos);
     int64_t lo_bit = int64_t(1) << lo;
-    int64_t a_bit = int64_t(1) << bitpos_a, b_bit = int64_t(1) << bitpos_b;
+    int64_t cbit = int64_t(1) << control_bitpos, tbit = int64_t(1) << target_bitpos;
 
+#if _DISPATCH_AVAILABLE
+    int tier = _cpu_tier();
+    if (tier >= 2) { _apply_c1q_avx512(sv, dim, lo, hi, lo_bit, cbit, tbit, u00, u01, u10, u11); return; }
+    if (tier >= 1) { _apply_c1q_avx2(sv, dim, lo, hi, lo_bit, cbit, tbit, u00, u01, u10, u11); return; }
+#endif
+    _apply_c1q_scalar(sv, dim, lo, hi, lo_bit, cbit, tbit, u00, u01, u10, u11);
+}
+
+// ---------------------------------------------------------------------
+// apply_swap: pure data movement -- same dispatch pattern as
+// apply_cnot_fast.
+// ---------------------------------------------------------------------
+
+static void _apply_swap_scalar(cplx* sv, int64_t dim, int lo, int hi,
+                               int64_t lo_bit, int64_t a_bit, int64_t b_bit) {
     int64_t n_outer = dim >> (hi + 1);
     int64_t n_mid = int64_t(1) << (hi - lo - 1);
+    #pragma omp parallel for collapse(2) schedule(static) if(_omp_worth_it())
+    for (int64_t outer = 0; outer < n_outer; outer++) {
+        for (int64_t mid = 0; mid < n_mid; mid++) {
+            int64_t skeleton = (outer << (hi + 1)) | (mid << (lo + 1));
+            cplx* p_ab = sv + skeleton + a_bit;
+            cplx* p_ba = sv + skeleton + b_bit;
+            for (int64_t j = 0; j < lo_bit; j++) std::swap(p_ab[j], p_ba[j]);
+        }
+    }
+}
 
+#if _DISPATCH_AVAILABLE
+__attribute__((target("avx2,fma")))
+static void _apply_swap_avx2(cplx* sv, int64_t dim, int lo, int hi,
+                             int64_t lo_bit, int64_t a_bit, int64_t b_bit) {
+    int64_t n_outer = dim >> (hi + 1);
+    int64_t n_mid = int64_t(1) << (hi - lo - 1);
     #pragma omp parallel for collapse(2) schedule(static) if(_omp_worth_it())
     for (int64_t outer = 0; outer < n_outer; outer++) {
         for (int64_t mid = 0; mid < n_mid; mid++) {
             int64_t skeleton = (outer << (hi + 1)) | (mid << (lo + 1));
             cplx* p_ab = sv + skeleton + a_bit;
             cplx* p_ba = sv + skeleton + b_bit;
-#if defined(__AVX512F__)
             double* d_ab = reinterpret_cast<double*>(p_ab);
             double* d_ba = reinterpret_cast<double*>(p_ba);
             int64_t j = 0;
-            for (; j + 4 <= lo_bit; j += 4) {
-                __m512d a = _mm512_loadu_pd(d_ab + 2 * j);
-                __m512d b = _mm512_loadu_pd(d_ba + 2 * j);
-                _mm512_storeu_pd(d_ab + 2 * j, b);
-                _mm512_storeu_pd(d_ba + 2 * j, a);
-            }
             for (; j + 2 <= lo_bit; j += 2) {
                 __m256d a = _mm256_loadu_pd(d_ab + 2 * j);
                 __m256d b = _mm256_loadu_pd(d_ba + 2 * j);
@@ -540,10 +607,30 @@ void apply_swap(py::array_t<cplx, py::array::c_style | py::array::forcecast> sta
                 _mm256_storeu_pd(d_ba + 2 * j, a);
             }
             for (; j < lo_bit; j++) std::swap(p_ab[j], p_ba[j]);
-#elif defined(__AVX2__)
+        }
+    }
+}
+
+__attribute__((target("avx512f,fma")))
+static void _apply_swap_avx512(cplx* sv, int64_t dim, int lo, int hi,
+                               int64_t lo_bit, int64_t a_bit, int64_t b_bit) {
+    int64_t n_outer = dim >> (hi + 1);
+    int64_t n_mid = int64_t(1) << (hi - lo - 1);
+    #pragma omp parallel for collapse(2) schedule(static) if(_omp_worth_it())
+    for (int64_t outer = 0; outer < n_outer; outer++) {
+        for (int64_t mid = 0; mid < n_mid; mid++) {
+            int64_t skeleton = (outer << (hi + 1)) | (mid << (lo + 1));
+            cplx* p_ab = sv + skeleton + a_bit;
+            cplx* p_ba = sv + skeleton + b_bit;
             double* d_ab = reinterpret_cast<double*>(p_ab);
             double* d_ba = reinterpret_cast<double*>(p_ba);
             int64_t j = 0;
+            for (; j + 4 <= lo_bit; j += 4) {
+                __m512d a = _mm512_loadu_pd(d_ab + 2 * j);
+                __m512d b = _mm512_loadu_pd(d_ba + 2 * j);
+                _mm512_storeu_pd(d_ab + 2 * j, b);
+                _mm512_storeu_pd(d_ba + 2 * j, a);
+            }
             for (; j + 2 <= lo_bit; j += 2) {
                 __m256d a = _mm256_loadu_pd(d_ab + 2 * j);
                 __m256d b = _mm256_loadu_pd(d_ba + 2 * j);
@@ -551,12 +638,28 @@ void apply_swap(py::array_t<cplx, py::array::c_style | py::array::forcecast> sta
                 _mm256_storeu_pd(d_ba + 2 * j, a);
             }
             for (; j < lo_bit; j++) std::swap(p_ab[j], p_ba[j]);
-#else
-            for (int64_t j = 0; j < lo_bit; j++) std::swap(p_ab[j], p_ba[j]);
-#endif
         }
     }
 }
+#endif
+
+void apply_swap(py::array_t<cplx, py::array::c_style | py::array::forcecast> state,
+                int bitpos_a, int bitpos_b) {
+    auto buf = state.request();
+    cplx* sv = static_cast<cplx*>(buf.ptr);
+    int64_t dim = buf.shape[0];
+    int lo = std::min(bitpos_a, bitpos_b);
+    int hi = std::max(bitpos_a, bitpos_b);
+    int64_t lo_bit = int64_t(1) << lo;
+    int64_t a_bit = int64_t(1) << bitpos_a, b_bit = int64_t(1) << bitpos_b;
+
+#if _DISPATCH_AVAILABLE
+    int tier = _cpu_tier();
+    if (tier >= 2) { _apply_swap_avx512(sv, dim, lo, hi, lo_bit, a_bit, b_bit); return; }
+    if (tier >= 1) { _apply_swap_avx2(sv, dim, lo, hi, lo_bit, a_bit, b_bit); return; }
+#endif
+    _apply_swap_scalar(sv, dim, lo, hi, lo_bit, a_bit, b_bit);
+}
 
 // General small-k fast kernel: replaces the slow scatter_bits-based
 // apply_gate for k<=4 target qubits (any control count already goes
@@ -652,7 +755,6 @@ void apply_gate_fast(py::array_t<cplx, py::array::c_style | py::array::forcecast
     }
 }
 
-
 PYBIND11_MODULE(hdqs_core, m) {
     m.doc() = "HDQS native statevector/density-matrix kernels";
     m.def("apply_1q", &apply_1q,
@@ -673,4 +775,12 @@ PYBIND11_MODULE(hdqs_core, m) {
           "Apply a single-qubit Kraus channel to a density matrix, in place",
           py::arg("rho"), py::arg("n_qubits"), py::arg("qubit"),
           py::arg("kraus_ops"));
-}
+    m.def("cpu_dispatch_tier", []() {
+#if _DISPATCH_AVAILABLE
+        return _cpu_tier();
+#else
+        return 0;
+#endif
+    }, "0=scalar, 1=AVX2+FMA, 2=AVX-512F+FMA -- which kernel tier this "
+       "process actually selected at runtime on the current CPU");
+}

sia_script-1.0.2/setup.py

@@ -1,48 +0,0 @@
-"""
-Adds the sia.hdqs_core native extension to the build. Everything else
-(package metadata, dependencies, version) stays in pyproject.toml — this
-file exists only because setuptools has no purely declarative way to
-build a C++ extension from pyproject.toml alone.
-
-`python -m build` picks this up automatically; no change to your
-existing build/twine workflow.
-"""
-import sys
-from setuptools import setup
-from pybind11.setup_helpers import Pybind11Extension, build_ext
-
-# -O3 for standard optimization. -march=native is deliberately NOT used
-# here: it would tie the compiled wheel to the exact CPU that builds it,
-# and could crash with an "illegal instruction" fault on an end user's
-# different (often older) CPU. This keeps published wheels portable —
-# hdqs_engine.py falls back to a slower but fully portable code path
-# automatically when the fast (AVX2/AVX-512) instructions aren't
-# available at compile time, so nothing breaks, it's just not maximally
-# fast on every machine. Building locally with -march=native (e.g. for
-# your own benchmarking) is a separate, deliberate choice — see the
-# session notes on this if you want that build instead.
-extra_compile_args = ["-O3", "-std=c++17"]
-extra_link_args = []
-
-if sys.platform == "win32":
-    extra_compile_args = ["/O2", "/std:c++17", "/openmp"]
-else:
-    extra_compile_args += ["-fopenmp"]
-    extra_link_args += ["-fopenmp"]
-
-ext_modules = [
-    Pybind11Extension(
-        "sia.hdqs_core",
-        ["src/hdqs_core.cpp"],
-        cxx_std=17,
-        extra_compile_args=extra_compile_args,
-        extra_link_args=extra_link_args,
-    ),
-]
-
-setup(
-    package_dir={"sia": "sia"},
-    ext_modules=ext_modules,
-    cmdclass={"build_ext": build_ext},
-    zip_safe=False,
-)